Introductory Assembly Language
Thorne : Chapter 3, Sections 7.1, 13.1, Appendix V.A
(Irvine, Edition IV : 4.1, 4.2, 6.2 7.2, 7.3, 7.4)
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Intel 8086 Assembly Instructions
•
•
•
Assembly instructions are readable forms of machine instructions
– They use mnemonics to specify operations in a human-oriented
short form
– Examples
MOV
(move)
SUB
(subtract)
JMP
(jump)
Instructions have two aspects : operation and operands
– Operation (Opcode): how to use state variable values
– operands: which state variables to us
Operands can be specified in a variety of ways that are called
addressing modes
– Simple modes:
register, immediate, direct
– More powerful:
indirect
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Sample Instructions
Syntax
MOV
ADD
SUB
INC
NOP
Semantics
AX, BX
DX, CX
DX, AX
AX
AX := BX
DX := DX + CX
DX := DX – AX
AX := AX + 1
(2 ops)
(2 ops)
(2 ops)
(1 op)
(0 op)
Instructions with two operands : destination (dest), source (src)
MOV
AX,
BX
Operation operand (dest), operand (src)
(Opcode)
((Order of dest and src is important,
p
, Must know on exams))
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Instruction Syntax : Operand Compatibility
• For all instructions with two operands, the two operands must be
compatible (same size).
– In high level languages : type checking
– In assembly : same size
• Examples :
MOV
AH, CL
8-bit src and dest ☺
MOV
AL, CX
?????
Example uses register mode,
mode
but compatibility is required
for all addressing modes to
come.
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Addressingg Modes
Syntax
MOV
ADD
SUB
SUB
AX, BX
DX, 1
DX, [1]
DX, var
Semantics
Addresssing Mode
AX := BX
DX := DX + 0001
DX := DX – m[DS:0001]
DX :=DX – m[DS:var]
Register,Register
Register,Immediate
Register,Direct Memory
Register,Direct Memory
A variable declared in data segment
g
(more
(
later))
INC
MOV
MOV
MOV
[BX]
m[DS:BX]:= m[DS:BX]+1 Register Indirect
AX, [BX+1] AX := m[DS:BX+1]
Based Indirect
AX, [BX+SI] AX := m[DS:BX+SI]
Based-Index
d d Indirect
di
AX, [BX+SI+1] AX := m[DS:BX+SI+1] Based-Index Indirect
with Displacement
p
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Addressing Mode : (1) Register
Register mode allows a register to be specified as an operand
As a source operand : Instruction will copy register value
A a ddestination:
As
ti ti
write
it value
l to
t register
it
Example
p :
register addressing mode for
both dest and src
MOV AX,, DX
AX := DX
Contents of DX is copied to AX
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Addressing Mode : (2) Immediate
• Immediate mode allows a constant to be specified as source
– Constant value is encoded as part of the instruction
• E
Example
ample : MOV AL,
AL 5
– Because AL is an 8-bit destination, the instruction encoding
includes 8-bit value 05h
• Example : MOV AX, 5
– Because AX is a 16-bit destination, the instruction encoding
includes the 16
16-bit
bit value 0005h
• Question : Is this possible ? MOV 4, BH ????
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Addressing Mode : (3) Direct Memory
• Direct memory mode allows the address offset of a memory
variable to be specified as an operand
– A constant address offset is encoded as part of the instruction
– The address offset is static : It must be known at assemblytime and remains constant through execution … but the
contents of that address may be dynamic
– During execution, the address offset is implicitly combined
with DS
• Example : MOV AL, [5]
• Reads contents of byte at address DS:0005 BEWARE :
Compare To
• Example : MOV var, AX
Immediate Mode!!
– Assumes a variable is declared in data segment MOV AL, 5
– Write contents of word at address DS:var
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Addressing Mode : (4a) Register Indirect
•
•
•
•
•
A register holds the address offset of the operand
The register can only be : BX,
BX SI
SI, DI
DI, BP
DS is default segment for: BX, SI, DI
SS is default segment for BP (later!)
Syntax : [ register ]
• IIndirect
di t Example:
E
l
MOV AX, [ BX ]
[ ]
= MOV AX,, DS:[BX]
AX:= m[DS:BX]
Value in BX is used as address
offset to a memory operand
CPU loads AX with contents of
contents of that memory
Indirect addressing mode use registers as a pointer,
which
hi h is
i a convenient
i t way to
t handle
h dl an array!! (later)
(l t )
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Addressing Mode : (4b) Indirect Indexed or Based
• Like register indirect, except you also specify a constant
e.g. [ BX + constant ]
• During execution, the processor uses a temporary register to
calculate BX + constant
– It then accesses memoryy addressed byy BX + constant
• Restriction: may only use BP, BX, SI or DI
same as register indirect
• Example :
MOV AX, [ BX +2 ]
In both cases :
= MOV AX, 2[BX]
CPU computes address = Value in
AX [BX][2]
= MOV AX,
BX+2
MOV AX, [ BX +var ]
= MOV AX, var[BX]
CPU loads AX with of that
address
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Addressing Mode (4c) : Indirect Based
Based-Indexed
Indexed
•
•
•
It is like indexed, except you use a second register instead of a constant
e.g. [ BX + SI ]
During execution, the processor uses a temporary register to calculate
sum of register values
– It then accesses memory addressed by sum
Restrictions:
– one must be base register: BX (or BP later!)
– one must be index register: SI or DI
– The only legal forms:
Default DS
Default SS
[ BX + SI ]
[ BP + SI ]
[ BX + DI ]
[ BP + DI ]
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base = BX
base = BP
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Addressing Mode (4c) : Indirect Based-Indexed
Based Indexed with
Displacement
• It is like based-indexed mode,, except
p includes a constant too
e.g. [ BX + SI + constant ]
• During execution, the processor uses a temporary register to
calculate sum of values
– It then accesses memory addressed by sum
• Restrictions: same as based mode
• MOV
= MOV
= MOV
AX, [ BX + SI + 2 ]
AX, [BX][SI+2]
AX 2[BX+SI]
AX,
• MOV
= MOV
AX, [ BX + SI + var ]
AX, var[BX][SI]
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In both cases :
CPU computes address = Value in
BX+SI+2
CPU loads AX with of that
address
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Loading Registers with Addresses
•
Before most instructions that use indirect addressing, the registers have
to be loaded with address.
•
Two alternatives :
MOV BX, OFFSET W
Functionally
equivalent!
•
LEA
BX, W
Both calculate and load the 16-bit effective address of a memory
operand.
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Segment Override
Required for exam : Restricted uses of registers
MOV [DX], AX
Marks will be deducted.
Recall :
DS is default segment for: BX, SI, DI
SS is default segment for BP (later!)
MOV [BX], AL = =
MOV DS:[BX], AL
MOV [BP], AL = =
MOV SS:[BP], AL
At times, you may run out of registers and need to use either the
index registers or the segment registers outside of their assigned
default roles (eg. duplicating data structures),
MOV SS:[BX], AL
MOV ES:[BX], AL
MOV DS:[BP],
DS [BP] AL
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Operand Compatibility with Memory Operands
Clear and unambiguous Examples
MOV [0BCh], AX
MOV [BX],
[BX] AL
– Why ? Because the other REGISTER operand determines
size
Ambiguous Examples :
MOV [0BCh], 1
MOV [BX], 0
– Why ? The immediate operand could be 8 bits or 16 bits ?
– How does the assembler decide ?
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Operand Compatibility with Memory Operands
• Memory Access Qualifiers
WORD PTR
BYTE PTR
word pointer – 16-bit operand
byte pointer – 8-bit operand
• Example
l :
MOV BYTE PTR [0FF3E], 1
8 bit destination, no ambiguity
g y
MOV WORD PTR [BX], 0
16 bit destination
16-bit
destination, no ambiguity
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Assembler Tip About Operand Compatibility
W
DW
0AA33h
...
MOV AL,
AL W
•
16-bit memory src operand
8 bit register dest operand
8-bit
The assembler will ggenerate an error
– Basic “type checking”
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Programs to do simple arithmetic
Problem : Write a code fragment to add the values of memory locations
at DS:0, DS:01, and DS:02, and save the result at DS:10h.
Solution:
Step 1
Processor
Memory
AL ⇐ m[DS:00]
Step 2
DS:00
10h
AL ⇐ AL + m[DS:01]
DS:01
20h
AL=10h/30h/44h
Step 3
AL ⇐ AL + m[DS:02]
[DS 02]
DS:02
14h
Step 4
DS:10 ⇐ AL
MOV AL, [0000]
ADD AL, [0001]
ADD AL,, [[0002]]
MOV [0010h], AL
DS:10h
FFh 44h
DS is default!
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Learning how to read a reference manual on assembly
instructions
We’ve seen that instructions often have restrictions – registers, addressing
mode
For each instruction – whether in textbook or in processor
processor’ss programming
manual - the permitted operands and the side-effects are given
Thorne text,
text Appendix V.A
V A “Instruction
Instruction set summary
summary”
ADD
Instruction Formats :
ADD reg, reg
ADD reg, immed
ADD mem, reg
ADD mem, immed
ADD reg, mem
ADD accum, immed
Is this permitted : ADD X, Y ?
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Flag status affected:
AF PF
AF,
PF, CF
CF, SF
SF, OF
OF, ZF
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Learning how to read a reference manual on assembly
instructions
MOV
Instruction Formats :
MOV reg, reg
MOV mem, reg
g, mem
MOV reg,
MOV reg16, segreg
MOV segreg, reg16
Fl status
Flag
t t affected:
ff t d
None
MOV reg,immed
i
d
MOV mem, immed
MOV mem16,, segreg
g g
MOV segreg, mem16
Segment registers (CS, DS, SS, ES) are 16-bit!
Question: Suppose we want to initialize DS with a constant value
45DFh ?
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Understanding High-Level Control Flow at Machine Level
•
•
•
•
Execution of data transfer/manipulation
instruction advances CS:IP to next
q
instruction.
sequential
Execution of control flow instructions
changes address for fetch of next
instruction.
For example :
– If condition is true, continue
sequentially then skip to
next statements
next_statements
– If condition is false, skip to
false_statements, then continue
sequentially
– Skip = control flow or jumps
Conditions depend on the status flags
((zero,, carry,
y, overflow,, sign,
g , parity)
p y)
( ZF, CF,
OF,
SF, PF)
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Conditional Statements :
if ( condition )
{
true_statements;
}
else
{
false_statements;
_
}
next_statements;
Skip == Change
CS:IP of next
fetched instruction
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Understanding High-Level Control Flow at Machine
Level
• Control Flow is also seen in Program Loops
for (i = n1 to n2)
for (i= n2 downto n1)
{ d
do statements
t t
t S }
{ do
d Statements
St t
t S }
while (
(condition C)
) do { statements S }
repeat {
statements S } until (condition C)
“condition” are dependent on the status flags
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Control Flow Implications of Segmented Memory Model
• The address of the next instruction is determined by CS:IP
• Intra-segment control flow : control stays in current code
segment
– Onlyy need to modifyy IP
– Need only supply (up to) 16-bit of information
• Inter-segment control flow : control passes to an address outside
off currentt code
d segmentt
– Must modify both CS and IP
– Must supply
pp y 32-bits of information.
• To begin : We will only be concerned with intrasegment control
fl (only
flow
( l modify
dif IP)
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JMP target
•
Unconditional JUMP
Control is always transferred to specified (relative) target.
Relative Addressing Example:
.LST file fragment
address
machine instruction
ASM instruction
(
(memory
contents))
0034H
E9 10 02
JMP 0247H
0037H
Not
….
….
….
E9 47 02!
0247H
CS:247
sta t oof fetch:
start
etc :
after fetch:
after execute:
IP = 003
0034H
IP = 0037H
IP = 0247H
IR = ????????
IR = E9 10 02
IR = E9 10 02
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(Little endian=0210h)
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Simple Conditional JMPs
• Specify condition in terms of FLAG values set by the execution
of the previous instruction
JZ
Jump Zero:
Jump if ZF = 1 else continue
JC
Jump Carry : Jump if C=1 else continue
JO
Jump Overflow:Jump if O=1 else continue
JS
Jump Signed : Jump if S=1 else continue
JP
Jump Parity : Jump if P=1 else continue
• For each case,, there is a “not” condition
e.g. JNZ
Jump Not Zero
Loop Example: MOV CX, 5
DoLoop:
. . .
SUB CX, 1
JNZ
DoLoop
·
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Comparison Instructions CMP
• Comparison instructions are used to simply set the flags
CMP dest, src
• Performs
P f
ddestt – src andd sets
t FLAGS (b
(butt ddoes nott store
t
result)
lt)
• CMP Example :
CMP AL, 10
JZ
EqualToTen ; or JE !
…
; Code for Not Equal
EqualToTen:
• It is often useful to think of combination as:
CMP dest, src
J*
Where the jump is taken if “dest - src” meets condition *
– in above example, jump is taken if AL == 10
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