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Design of Phase-Frequency Detectors (PFD), Charge Pumps, and Loop Filters Howard Luong EEE, HKUST eeluong@ee.ust.hk Outline • • • • Phase Detector (PD) Phase-Frequency Detector (PFD) Charge Pump Loop Filter URL: http://www.ee.ust.hk/~eeluong 852-2358-8514 PFD-CP-LF, Howard Luong 2 Analog Phase Detector Phase Detector • Performs Phase Comparison for Reference and Prescaler’s Output • Key Parameters – Phase Comparison Range – Gain – Noise and Spur • Typically Digital and Operate on Edges of Inputs • Fast Transition Edges Can Be Achieved • Can Be Implemented Using a Simple Mixer • Compared to Digital Counterparts: – Input Can Be Sinusoidal – Can Operate at Much Higher Frequencies – Input Amplitude Affects Output, Gain, PLL Loop Gain and Dynamic Behavior – Larger Power Consumption vPD fref fdiv PFD-CP-LF, Howard Luong 3 PFD-CP-LF, Howard Luong 4 XOR Phase Detector XOR Phase Detector - Gain • • • • Simple Gain Independent of Input Amplitude Require Square-Wave Inputs Locked-State Input Phase Error is 90 Degrees => Nominal Duty Cycle of 50% • Output Frequency is Twice Reference • DC Characteristic is Defined as Average of Output <VPD> as Function of Input Phase Error φe • Gain = Slope of DC Characteristic Curve • Sensitive to Both Rising and Falling Edges of Reference and Divider Output fref fref VPD VPD fdiv fdiv φe = φref −φdiv W 1 -1 T/2 t < VPD >= −1+ 2 VPD PFD-CP-LF, Howard Luong 5 XOR Phase Detector - Gain φe -1 W= φe T π < VPD >= −1+ 2 PFD-CP-LF, Howard Luong 6 • Gain Has Sign Inversion for An Increment of Phase Error of 180 Degrees • Consequently, Usable Phase Range is 180 Degrees • Locked-State Phase Error is 90 Degrees • PD Gain: 1 π PFD-CP-LF, Howard Luong XOR Phase Detector - Gain <VPD> −π W T K = φe π PD 7 2 π PFD-CP-LF, Howard Luong 8 XOR Phase Detector with Extended Range • Modified to be sensitive to only rising or falling edges XOR Phase Detector with Extended Range • Output frequency is same as reference fref fref fdiv ÷2 ÷2 <VPD> 1 fdiv VPD fref/2 2π −2π fdiv /2 φe -1 VPD PFD-CP-LF, Howard Luong 9 PFD-CP-LF, Howard Luong 10 XOR Phase Detector with Extended Range XOR Phase Detector - Limitation • Gain Has Sign Inversion for An Increment of Phase Error of 360 Degrees • Consequently, Usable Phase Range is 360 Degrees • Locked-State Phase Error is 180 Degrees • PD Gain: • Frequency Acquisition Can Be Slow • Input Square Waves Required for Digital Phase Detectors => High Harmonics • Divider Output Can Lock to Reference Harmonics Unless VCO Output Frequency Range is Limited • Solution: Phase-Frequency Detection K = PD 1 π PFD-CP-LF, Howard Luong 11 PFD-CP-LF, Howard Luong 12 Phase-Frequency Detector (PFD) Up 1 D Q ref.clk f ref R Q’ fref fdiv slave.clk 1 D Vup Q Vdown Down R Q’ fdiv PFD-CP-LF, Howard Luong 13 Phase-Frequency Detector (PFD) f <f ref.clk div> slave.clk ref • If fdiv < fref : Up=1 Down=0 – Vup = 1, VDown = 0 f ref.clk > slave.clk fdiv < fref >f slave.clk div > ref.clk ref <f fdiv > fref slave.clk > ref.clk ref.clk div> slave.clk ref • If fdiv > fref : – Vup = 0, VDown = 1 Up=0 Down=0 f Phase-Frequency Detector (PFD) – Timing Diagram • If fdiv = fref : – Vup - VDown = KPFD * (φdiv - φref ) Up=0 Down=1 PFD-CP-LF, Howard Luong 14 Phase-Frequency Detector (PFD) • Tri-state PFD • Edge-Triggering Circuits Are Used to Eliminate Dependency of Gain to Input Duty Cycle • Nominal Output Frequency is Same as Reference • Two Outputs are Subtracted => Output Has Three Possible States: –1, 0, 1 • Locked-State Phase Error is 0 Degree => Small Pulses at Outputs => Low Power, Low Noise slave.clk > ref.clk fdiv > fref PFD-CP-LF, Howard Luong 15 PFD-CP-LF, Howard Luong 16 Phase-Frequency Detector (PFD) K = <Up - Down> PD 1 1 2π Phase-Frequency Detector (PFD) • PFD Output Has Edges with Finite Slope => Affect PFD Gain, In Particular for Narrow Pulses −2π Wide Pulse 2π Narrow Pulse φe -1 • Sign of output (Up – Down) is same as phase error => frequency detection • Usable phase range is extended to 4π PFD-CP-LF, Howard Luong Gain Reduction 17 Phase-Frequency Detector (PFD) • When Phase Error is Too Small, PFD Cannot Compare, and Output Become Zero => Dead Zone => Phase Noise from Reference and VCO are NOT Suppressed => Poor Close-In Phase Noise PFD-CP-LF, Howard Luong Phase-Frequency Detector Without Dead Zone Up 1 D Q R Q’ fref <Up - Down> 18 Delay 2 −2π 1 D Q 2π -2 Dead Zone PFD-CP-LF, Howard Luong Down φe fdiv 19 R Q’ Delay Added to Remove Dead Zone PFD-CP-LF, Howard Luong 20 PFD Model Phase-Frequency Detector Without Dead Zone φref verr • For XOR-based: 1 K PFD = π PFD • Add Delay in Reset Path Which Sets Minimum Pulse Width • Remove Dead Zone => Improve PFD Gain Linearity • Generate Pulses for both Up and Down => Increase Power and Noise φdiv • For tri-state PFD: φref verr KPFD K PFD = 1 2π φdiv PFD-CP-LF, Howard Luong 21 PFD-CP-LF, Howard Luong 22 Charge-Pump Phase-Locked Loop Charge-Pump Phase-Locked Loop • Employs A Phase-Frequency Detector (PFD) and a Charge Pump (CP) instead of a Phase Detector (PD) • Transfer Function of PFD and Charge Pump Has a Pole at Zero (Integrator) • Together with Another Pole at Zero from VCO, PLL System May Be Unstable • To Ensure Stability, A Zero is Added by Including Resistor Rz in Series with Cz • In Practice, A Capacitor CP is Connected in Parallel to Suppress Ripples at VC, which Would Introduce A Third Pole ICP φref VC PFD Rz φout ICP PFD-CP-LF, Howard Luong CP Cz 23 PFD-CP-LF, Howard Luong 24 Charge-Pump Phase-Locked Loop Charge-Pump Phase-Locked Loop I CP 1 ) ; GLPF ( s ) = ( RZ + CZ s 2π H ref ( s) close = K PFD ( s)GLPF ( s) KVCO s + K PFD ( s)G LPF ( s) KVCO ( s +ω z ) = Ho s 2 + 2ζω n s +ω n 2 1 Q H o = I CP Rz KVCO ; ω z = − 2π Rz C z I CP Q ωn = KVCO 2π C z R Q ζ = z I CP C z KVCO = ω n RzC z = ω n 2 2ω z 2 2π Q ζω n = I CP Rz KVCO 4π K PFD = PFD-CP-LF, Howard Luong 25 26 Synthesizer Using Charge-Pump PhaseLocked Loop Charge-Pump Phase-Locked Loop (CPPLL) • Natural Frequency ωn Does Not Depend on RZ • Both ωn and ζ Can Be Maximized Simultaneously by Increasing ICP or KVCO • Time Constant (ζωn) and Settling Time Do NOT Depend on Cz PFD-CP-LF, Howard Luong PFD-CP-LF, Howard Luong 27 I 1 ; G ( s) = ( R + ) C s 2π K ( s )G ( s ) K H ref ( s ) close = s + K PFD ( s )G LPF ( s ) KVCO / M ( s +ω z ) = Ho 2 s + 2ζω n s +ωn 2 K PFD = CP LPF Z Z PFD PFD-CP-LF, Howard Luong LPF VCO 28 Synthesizer Using Charge-Pump PhaseLocked Loop 1 Q H = I R K ; ω =− 2π Rz C z I 1 KVCO Qω = M 2π C R 1 ω RC ω = = Qζ = z I C K 2 2ω M 2 2π 1 Q ζω = I R K 4π M CP Charge Pump z o VCO ICP z Up CP Io n z CP z n z z n VCO Down Up Down 0 0 Io 0 1 0 ICP 0 1 -ICP z CP n ICP z VCO PFD-CP-LF, Howard Luong 29 30 Charge Pump - Solutions Charge Pump - Challenges • Many solutions for sample-and-hold and switchedcapacitor circuits can be applied: – Dummy transistors – Complimentary switches – Unit-gain buffers – Differential design • Need to have fast turn-on time => Use current steering technique to keep bias current on all the times • Face same problems as sample-and-hold and switched-capacitor circuits: – Charge injection – Charge sharing – Clock feed-through • Critical to match up and down currents to minimize spur PFD-CP-LF, Howard Luong PFD-CP-LF, Howard Luong 31 PFD-CP-LF, Howard Luong 32 Charge Pump – Dummy Transistors PFD-CP-LF, Howard Luong Charge Pump – Complementary Switches 33 Charge Pump – Differential Configuration PFD-CP-LF, Howard Luong 34 Charge Pump - Solutions ICP UP DN’ DN UP’ UGB DN UP’ UP DN’ ICP PFD-CP-LF, Howard Luong 35 PFD-CP-LF, Howard Luong 36 Charge Pump – Current Mismatches • High charge-pump current: – Fast acquisition – Low stability – High phase noise and jitter • Low charge-pump current: – Slow acquisition – Good stability – Low phase noise and jitter => Start with high charge-pump current and switch to low current after lock detection! • To minimize current mismatches: – Increase channel length and width – Employ good layout techniques – Maximize Vgs ΔVt ΔI ΔW ΔL + +2 = I W L Vgs −Vt PFD-CP-LF, Howard Luong 37 CPPLL-Based Synthesizer with Lock Detector fref fo PFD CP Icp VCO LPF Lock fdiv %M Δφ=90o Charge Pump with Adaptive Current Lock PFD-CP-LF, Howard Luong 38 Loop Filter • Critical in determining synthesizer’s performance: – Phase noise – Spur – Settling time • Extra poles and zeros can be included to control the loop behavior (noise, transient) • Order of loop filter determines order and stability of the whole loop • Lock=0 => Icp = Icp1+ Icp2 • Lock=1 => Icp = Icp1 PFD-CP-LF, Howard Luong 39 PFD-CP-LF, Howard Luong 40 Zeroth-Order Loop Filter First-Order Loop Filter |Hopen(ω)| |Hopen(ω)| ωc GLP(ω) 0dB ω 1 ωc ωLP GLP(ω) ω 0dB 1 φ{Hopen(ω)} ω φ{Hopen(ω)} ωLP ω ω −90ο Zero-order LPF −90ο First-order LPF −180ο First-order PLL PFD-CP-LF, Howard Luong ω Second-order PLL 41 PFD-CP-LF, Howard Luong 42 Loop Filter – Sampling Noise CPPPL’s Loop Filter • ICP During ON, MOS Switch’s Turn-On Resistance Contributes Thermal Noise 4kTR ∞ φref vn = ∫ 4kTRon | H ( f ) |2 df 2 VC 0 PFD ∞ Rz φout = ∫ 4kTRon CP 0 ICP = Cz 1 df 1 + (ωRonCP )2 kT CP Ex : vn ~ 64 μV for CP = 1 pF PFD-CP-LF, Howard Luong 43 PFD-CP-LF, Howard Luong 44 Active Loop Filter Using Capacitive Multiplication Loop Filter • With Charge-Pump PFD, There Exist Two Poles at Zero => Need to Add Zero to Ensure Stability • The Zero is Typically Realized Using a Resistor Rz in Series with Capacitor Cz • CP Needs to Be Large Enough to Minimize kT/C Noise • Due to Large Ratio of Zero and Pole, Large Ratio of CP and Cz => Too Large Chip Area to Be Integrated On-Chip PFD-CP-LF, Howard Luong Ceff = RX C RY [Larsson, ISSCC 2001] • Employ feedback for capacitive multiplication to increase effective capacitance to reduce chip area • Extra noise from active devices and resistors 45 PFD-CP-LF, Howard Luong Dual-Path Loop Filter 46 Dual-Path Loop Filter ICP C3 C2 VC BICP ωZ ωp R4 xB R1 PFD-CP-LF, Howard Luong 47 C4 C1 PFD-CP-LF, Howard Luong 48 Dual-Path Loop Filter Dual-Path Loop Filter H LF (s) = [H int (s) + H LPF (s)]H 4 (s) 1 1 H int (s) = ≈ s(C2 +C3 ) sC3 BR1 1 H LPF (s) = ; H 4 ( s) = 1+ sC4 R4 1+ sC1R1 1 1+ sτ z 1 H LF (s) = sC3 1+ sτ p 1+ sτ 4 τ z = R1 (C1 + BC3 ); τ p = R1C1; τ 4 = R4C4 PFD-CP-LF, Howard Luong • Combine responses of an integrator and a scaled low-pass filter to generate a zero for stability • By scaling factor B, total capacitance required can be significantly reduced • Design of low-noise adder could be a limiting factor for noise and power • Separately-optimized capacitors => Two capacitors need to be large enough for kT/C noise requirement (~1nF each) 49 Dual-Path Loop Filter 50 Dual-Path Loop Filter • Unfiltered adder’s noise => noise, power consumption • Large dynamic range adder needed => Large supply voltage or limited tuning range • Increase capacitors to reduce the noise source • Reduce the VCO gain from the noise source to the VCO output => Using smaller voltage-controlled capacitors for VCO and larger signal at the filter output PFD-CP-LF, Howard Luong PFD-CP-LF, Howard Luong • Tuning signal is limited by the available dynamic range => smaller tuning range • Trade-off between capacitor size and tuning range • Outputs of dual paths can drive two varactors directly to eliminate adder to reduce noise and to save power [Lo 2002] 51 PFD-CP-LF, Howard Luong 52 Capacitance-Domain Dual-Path Loop Filter [Lo 2002] PD PU Charge pump (a) Charge pump Capacitance-Domain Dual-Path Loop Filter • Use two parallel voltage-controlled capacitors (varactors) to separately control signals in the two paths • Implement the addition in capacitance domain (by simply connecting two capacitors in parallel) • Obvious advantage: No voltage adder needed => improve noise, power consumption; lower supply voltage for same tuning range (b) LC tank PFD-CP-LF, Howard Luong 53 PFD-CP-LF, Howard Luong 54 Capacitance-Domain Dual-Path Loop Filter References • At lock, no net current to the two paths • In integrator path: non-zero net charge => average signal for phase locking • In LPF path: DC is zero, and small signal in LPF path used for stability only, not for tuning • Capacitor in LPF can be reduced without affecting the tuning and locking range => A large capacitor in integrator and a very “small” capacitor in LPF (e.g. 1nF and 0.1nF) => Reduce total capacitance further by half • B. Razavi, RF Microelectronics, Prentice Hall, 1998 • T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 2nd Edition, 2004 • H. C. Luong, and G. C. T. Leung, Low-Voltage CMOS RF Frequency Synthesizers , Cambridge University Press, August 2004 • M. Perrot, et al, “A 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation,” IEEE Journal of Solid-State Circuits (JSSC) , pp. 2048-60, Dec. 1997 PFD-CP-LF, Howard Luong PFD-CP-LF, Howard Luong 55 56 References • C. W. Lo and H. C. Luong, "A 1.5-V 900-MHz Monolithic CMOS Fast-Switching Frequency Synthesizer for Wireless Applications," IEEE Journal of Solid-State Circuits (JSSC) , Vol. 37, No. 4, pp. 459-70, April 2002. • W. Yan and H. C. Luong, "A 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Wireless Receivers," IEEE Journal of Solid-State Circuits (JSSC), Vol. 36, No. 2, pp. 204-216, February 2001 • G. Leung, and H. C. Luong, "A 1-V 5.2-GHz 27.5-mW Fully-Integrated CMOS WLAN Synthesizer," IEEE Journal of Solid-State Circuits (JSSC), Nov. 2004 • P. Larsson, “An offset-cancelled CMOS clock-recovery / demux with a half-rate linear phase detector for 2.5 Gb/s optical communication,” IEEE International Solid-State Circuits Conference, pp. 74-75, Feb. 2001 PFD-CP-LF, Howard Luong 57