Analog Dialogue
A forum for the exchange of circuits, systems, and software for real-world signal processing • Volume 49, Number 1, 2015
2
Editor’s Notes; New Product Introductions
3
FPGA-Based Systems Increase Motor-Control Performance
11
Powering ICs On and Off
15
Design a PLL Loop Filter when Only the Zero Resistor and Capacitor Are Adjustable
21
Quickly Implement JESD204B on a Xilinx FPGA
25
Power Management for Integrated RF ICs
31
Design Reliable Digital Interfaces for Successive-Approximation ADCs
analog.com/analogdialogue
Editor’s Notes
IN THIS ISSUE
FPGA-Based Systems Increase Motor-Control
Performance
Advanced motor-control systems combine control algorithms,
industrial networks, and user interfaces, so they require
additional processing power to execute all tasks in real time.
Multichip architectures are used to implement modern motorcontrol systems: a DSP executes motor-control algorithms, an
FPGA implements high-speed I/O and networking protocols,
and a microprocessor handles executive control. (Page 3)
Powering ICs On and Off
Modern integrated circuits employ sophisticated circuits
to ensure that they turn on in a known state; and preserve
memory, boot quickly, and conserve power when they are
powered down. This two-part article provides tips for using
power-on reset and power-down functions. (Page 11)
Design a PLL Loop Filter when Only the Zero Resistor and
Capacitor Are Adjustable
A standard procedure uses open-loop bandwidth and phase
margin to determine the component values for a PLL loop
filter, solving for the pole capacitor and deriving the remaining
values. In some cases this capacitor may be integrated, so the
standard procedure can’t be used. This article proposes an
alternative procedure that can be used when the value of the
pole capacitor is fixed. (Page 15)
Quickly Implement JESD204B on a Xilinx FPGA
The JESD204 high-speed serial interface connects data
converters to logic devices. As the speed and resolution of
converters continues to increase, this interface has become
common in ADCs, DACs, and RF transceivers. Serializer/
deserializer designs in FPGAs implement the physical layer.
This article describes how to quickly set up a project using a
Xilinx® FPGA to implement the JESD204B interface. (Page 21)
Power Management for Integrated RF ICs
As more building blocks are added to a radio-frequency
integrated circuit, more sources of noise coupling arise, making
power management increasingly important. This article
describes how power-supply noise can affect the performance
of RF ICs. The ADRF6820 quadrature demodulator with integrated phase-locked loop and a voltage-controlled oscillator is
used as an example, but the results are broadly applicable to
other high-performance RF ICs. (Page 25)
Design Reliable Digital Interfaces for SuccessiveApproximation ADCs
SAR ADCs provide up to 18-bit resolution at up to 5 MSPS.
A host processor can access the ADC via a variety of serial
and parallel interfaces such as SPI, I2C, and LVDS. This article
discusses design techniques for reliable, integrated digital
interfaces, including the digital power-supply level and
sequence, I/O state during turn on, interface timing, signal
quality, and errors caused by digital activity. (Page 31)
Jim Surber [jim.surber@analog.com]
2
Product Introductions: Volume 49, Number 1
Data sheets for all ADI products can be found by entering the
part number in the search box at analog.com.
February
ADC, Σ-∆, 3-channel, SPI interface....................................................ADE7903
ADC, Σ-∆, 3-channel, SPI interface....................................................ADE7923
Amplifier, operational, 200-MHz BW, RRIO...............................ADA4807-1
Codec, audio, four ADCs, two DACs............................................ ADAU1372
Data-acquisition system, 4-channel, 16-bit.................................. ADAR7251
Data recovery IC, 614.4-Mbps to 10.3125-Gbps.............................. ADN2905
Input protection device, high-voltage............................................ ADM1270
Mixer, receive, passive, dual, 700-MHz to 3000-MHz.................. ADRF6612
Mixer, receive, wideband, dual, integrated IF amplifiers............ ADRF6658
Multiplexer, 4-channel, 10-Ω, fault detection/protection............ADG5404F
Receiver, IF diversity, 385-MHz BW.................................................... AD6674
Receiver, optical, 11.3-Gbps..........................................................ADN3010-11
Regulator, buck, triple, 1800-mA.......................................................ADP5135
March
ADC, pipelined, dual, 16-bit, 125-MSPS, LVDS outputs................... AD9655
ADC, pipelined, 14-bit, 1-GSPS/500-MSPS......................................... AD9690
Amplifier, operational, quad, EMI/overvoltage protection.......ADA4177-4
Channel protector, quad, user-defined fault
protection/detection....................................................................ADG5462F
Controller, digital, isolated power supply with
PMBus interface..............................................................................ADP1052
DAC, nanoDAC+, octal, 16-bit, I2C interface....................................... AD5675
DACs, voltage-output, 12-/16-bit, unipolar/bipolar...........AD5721/AD5761
DACs, voltage-output, 12-/16-bit, unipolar/bipolar,
2-ppm/°C reference...................................................... AD5721R/AD5761R
Detectors, voltage, ultralow-power..............................ADM8641/ADM8642
Modulator, Σ-∆, 16-bit, isolated........................................................... AD7402
Regulators, switching, 2-channel, bipolar rails..............ADP5070/ADP5071
Switch, dual SPDT, 10-Ω, fault protection/detection...................ADG5436F
Switch, power, high-side, 12-V, 2-A, logic-controlled.....................ADP1290
Supervisory ICs, ultralow-power, manual reset........ADM8611/ADM8612
Supervisory ICs, ultralow-power, watchdog timer,
manual reset........................................... ADM8613/ADM8614/ADM8615
Analog Dialogue
Analog Dialogue, www.analog.com/analogdialogue, the technical
magazine of Analog Devices, discusses products, applications,
technology, and techniques for analog, digital, and mixed-signal
processing. Published continuously for 49 years—starting in 1967—it
is available in two versions. Monthly editions offer technical articles;
timely information including recent application notes, circuit notes, newproduct briefs, webinars, and published articles; and a universe of links
to important and relevant information on the Analog Devices website,
www.analog.com. Printable quarterly issues and ebook versions feature
collections of monthly articles. For history buffs, the Analog Dialogue
archive, www.analog.com/library/analogdialogue/archives.html,
includes all regular editions, starting with Volume 1, Number 1 (1967),
and three special anniversary issues. To subscribe, please go to
www.analog.com/library/analogdialogue/subscribe.html. Your comments
are always welcome: Facebook: www.facebook.com/analogdialogue;
EngineerZone: ez.analog.com/blogs/analogdialogue; Email: dialogue.
editor@analog.com or Jim Surber, Editor [jim.surber@analog.com].
Analog Dialogue Volume 49 Number 1
FPGA-Based Systems Increase
Motor-Control Performance
By Andrei Cozma and Eric Cigan
Introduction
Used in a wide range of industrial, automotive, and commercial applications, electric motors are controlled by drives that
vary the electrical input power to control the torque, speed,
and position. High-performance motor drives can increase
efficiency and deliver faster, more accurate control. Advanced
motor-control systems combine control algorithms, industrial networks, and user interfaces, so they require additional
processing power to execute all tasks in real time. Multichip architectures are typically used to implement modern
motor-control systems: a digital signal processor (DSP)
executes motor-control algorithms, an FPGA implements
high-speed I/O and networking protocols, and a microprocessor handles executive control.1
With the advent of system-on-chip (SoC) devices such as the
Xilinx Zynq All Programmable SoC, which combines the
versatility of a CPU and the processing power of an FPGA,
designers have the means to consolidate motor-control functions and additional processing tasks into a single device.
Control algorithms, networking, and other processing intensive tasks are offloaded to the programmable logic, while
supervisory control, system monitoring and diagnosis, user
interface, and commissioning are handled by the processing
unit. The programmable logic can include multiple control
cores that run in parallel to implement multiaxis machines or
multiple control systems. Having the complete controller on
a single chip allows the hardware design to be simpler, more
reliable, and less expensive.
In recent years, software modeling and simulation tools, such
as Simulink® from MathWorks®, have allowed model-based
design to evolve into a complete design flow—from model
creation to implementation.2 Transforming the way engineers and scientists work, model-based design is moving
design tasks from the lab and field to the desktop. Now the
entire system—including the plant and the controller—can
be modeled, allowing the engineer to tune the controller’s
behavior before deploying it in the field. This reduces the risk
of damage, accelerates system integration, and reduces dependency on equipment availability. Once the control model is
complete, it can be automatically translated by the Simulink
environment into C and HDL code that will be run by the control system, saving time and avoiding manual coding errors.
The risk is further reduced by linking the system model to
a rapid prototyping environment that allows observation of
how the controller will operate in real-life conditions.
A complete development environment for achieving increased
motor-control performance uses the Zynq SoC from Xilinx for
implementing the controller, Simulink from MathWorks for
model-based design and automatic code generation, and the
Intelligent Drives Kit from Analog Devices for rapid prototyping of the drive system.
Xilinx FPGA and SoC Motor-Control Solutions
Advanced motor-control systems must execute a combination
of control, communication, and user interface tasks, each of
which has different processing bandwidth requirements and
real-time constraints. The hardware platform chosen to implement such a control system must be robust and scalable while
allowing for future system improvements and expansion.
The Zynq All Programmable SoC fulfills these requirements
by combining a high-performance processing system with
programmable logic, as shown in Figure 1. This combination
delivers superior parallel-processing power, real-time performance, fast computation, and versatile connectivity. The SoC
integrates two Xilinx analog-to-digital converters (XADC) for
monitoring the system or external analog sensors.
PROCESSING SYSTEM
PROCESSOR I/O MUX
FLASH CONTROLLER
NOR, NAND, SRAM, QUAD SPI
MULTIPORT DRAM CONTROLLER
DDR3, DDR3L, DDR2
2×
SPI
2×
I2C
2×
CAN
2×
UART
AMBA® INTERCONNECT
GPIO
512kB L2 CACHE
GENERAL INTERRUPT
WATCHDOG
CONTROLLER
TIMER
CONFIGURATION
TIMERS
DMA
2× SDIO
WITH DMA
2× USB
WITH DMA
2× GigE
WITH DMA
ARM® CoreSight® MULTICORE DEBUG AND TRACE
NEON® DSP/FPU ENGINE
NEON DSP/FPU ENGINE
CORTEX®—A9 MPCORE
32kB/32kB I/D CACHES
CORTEX—A9 MPCORE
32kB/32kB I/D CACHES
AMBA INTERCONNECT
EMIO
XADC
2× ADC, MUX,
THERMAL SENSOR
AMBA® INTERCONNECT
SNOOP
CONTROL
UNIT
AMBA® INTERCONNECT
SECURITY
AES, SHA, RSA
GENERAL-PURPOSE
AXI PORTS
PROGRAMMABLE LOGIC
(SYSTEM GATES, DSP, RAM)
MULTISTANDARD I/Os (3.3V AND HIGH-SPEED 1.8V)
256kB
ON-CHIP
MEMORY
ACP
HIGH-PERFORMANCE
AXI PORTS
PCIe GEN2
1 TO 8 LANES
MULTIGIGABIT TRANCEIVERS
Figure 1. Xilinx Zynq SoC block diagram.
Analog Dialogue Volume 49 Number 1
3
The processing side of the Zynq consists of a dual-core ARM
Cortex-A9 processor, a NEON coprocessor, and floating-point
extensions that accelerate software execution. The processing
system addresses tasks such as supervisory control, motion
control, system management, user interface, and remote
maintenance functions that are well-suited to software implementation. Embedded Linux or real-time operating systems
can be deployed to take advantage of the system’s capabilities.
The self-contained processor can be used without the need to
configure the programmable logic. This allows software developers to write code in parallel with hardware engineers who
design the FPGA fabric.
On the programmable logic side, the device has up to
444,000 logic cells and 2200 DSP slices that supply massive
processing bandwidth. The FPGA fabric is scalable, so a user
can choose from a small device with 28,000 logic cells all the
way up to a high-end device, which can tackle the most
challenging signal-processing applications. Five AMBA-4 AXI
high-speed interconnects tightly couple the programmable
logic to the processing system, giving the equivalent of more
than 3000 pins of effective bandwidth. The programmable
logic is suitable for implementing time critical, processing
intensive tasks such as real-time industrial Ethernet protocols,
and it can accommodate multiple control cores that run in
parallel for multiaxis machines or multiple control systems.
Xilinx All Programmable SoC-based solutions and platforms
meet the critical timing and performance requirements posed
by today’s complex control algorithms such as field-oriented
control (FOC) and complex modulation schemes such as the
regenerative pulse frequency modulator3 designed by Xilinx
and Qdesys.
Model-Based Design Using Simulink from MathWorks
Simulink is a block diagram environment for multidomain
simulation and model-based design that is well-suited to
simulating systems that include control algorithms and plant
models. Motor-control algorithms regulate speed, torque,
and other parameters, often for precision positioning. Evaluating control algorithms using simulation is an effective way to
determine the suitability of motor-control designs and reduce
the time and cost of algorithm development before committing
to expensive hardware testing. Figure 2 depicts an efficient
workflow for designing a motor-control algorithm:
• Build accurate controller and plant models, often from
libraries of motors, drive electronics, sensors, and loads
• Simulate system behavior to verify that the controller is
performing as expected
• Generate C code and HDL for real-time testing and implementation
• Test control algorithms using prototyping hardware
• Deploy the controller onto the final production system
once the control system has proven to be satisfactory
through simulation and testing on prototyping hardware
BUILD ACCURATE
SYSTEM MODELS
VERIFY AND TEST
CONTROL ALGORITHMS
ON PROTOTYPING
HARDWARE
SIMULATE SYSTEM
BEHAVIOR
GENERATE C AND HDL
CODE FOR TESTING
AND IMPLEMENTATION
Figure 2. Workflow for motor-control algorithm design.
MathWorks products including the Control System Toolbox,™
SimPowerSystems,™ and Simscape™ provide industry-standard
algorithms and applications for systematically analyzing,
designing, and tuning linear control systems, as well as
component libraries and analysis tools for modeling and simulating systems spanning mechanical, electrical, hydraulic,
and other physical domains. These tools provide the means to
create high-fidelity plant and controller models that can verify
the behavior and performance of the control system before
moving to the physical implementation. The simulation environment is the perfect place to verify functionality corner cases
and extreme operating conditions to ensure that the controller
is prepared for such situations, and its real-life operation will
be safe for both equipment and operating personnel.
Once the control system is fully verified in the simulation
environment using the embedded coder and the HDL coder
tools, it can be translated into C code and HDL and deployed
on prototyping hardware for testing and to the final production system afterwards. At this point software and hardware
implementation such as fixed-point and timing behavior
requirements are specified. Automatic code generation helps
to reduce the time needed to move from concept to actual
system implementation, eliminates coding errors, and ensures
that the actual implementation matches the model. Figure 3
depicts the real-life steps needed to model a motor controller
in Simulink and transfer it to the final production system.
SIMULATION
PROTOTYPE
PRODUCTION
SIMULINK
ZYNQ
ZYNQ
ARM
ALGORITHM
MODEL
ALGORITHM
MODEL
EMBEDDED CODER
HDL CODER
ALGORITHM
C
LINUX
DRIVER
VIVADO
LINUX
DRIVER
AXI BUS
AXI
INTRFACE
AXI
INTERFACE
PROG. LOGIC
MOTOR
MODEL
ARM
ALGORITHM
C
AXI BUS
ALGORITHM
HDL
MOTOR
IMPLEMENT CONTROL
ALGORITHMS ON
PRODUCTION
CONTROL SYSTEM
VIVADO
ALGORITHM
HDL
SYSTEM
CODE
IP1
IP2
IP3
PROGRAMMABLE LOGIC
MOTOR
SYSTEM
Figure 3. Path from simulation to production.
4
Analog Dialogue Volume 49 Number 1
The first step is to model and simulate the controller and the
plant in Simulink. At this stage, the controller algorithm is
partitioned into blocks that will be implemented in software,
and blocks that will be implemented in programmable logic.
Once the partitioning and the simulation are complete, the
controller model is converted into C code and HDL using the
embedded coder and HDL coder. A Zynq-based prototyping
system verifies the performance of the control algorithm and
helps further tune the controller model before moving to the
production stage. In the production stage, the automatically
generated C code and HDL are integrated into the complex
production system framework. This workflow ensures that
once the control algorithm reaches the production stage it is
fully verified and tested, thus providing high confidence in
the system robustness.
The controller board is a mixed-signal FPGA mezzanine
card (FMC), designed to connect to any Xilinx FPGA or SoC
platforms with low pin count (LPC) or high pin count (HPC)
FMC connectors. It features:
• Current and voltage measurement using isolated ADCs
• An isolated Xilinx XADC interface
• Fully isolated digital control and feedback signals
• Hall, differential Hall, encoder, and resolver interfaces
• 2-Gb Ethernet PHYs to enable high-speed industrial
communication protocols such as EtherCAT, ProfiNET,
Ethernet/IP, or Powerlink
• FMC signals voltage adaptation interface for seamless
operation on all FMC voltage levels
Rapid Prototyping with the Analog Devices
Intelligent Drives Kit
Choosing the right prototyping hardware is a major step in
the design process. The Analog Devices Intelligent Drives Kit
enables rapid, efficient prototyping. Combining the Zynq-7000
All Programmable SoC ARM dual-core Cortex-A9 with 28 nm
programmable logic with the latest generation Analog Devices
high-precision data converters and digital isolation, the Avnet
Zynq-7000 All Programmable SoC/Analog Devices Intelligent
Drives Kit enables high-performance motor control and dual
gigabit Ethernet industrial networking connectivity. The kit
comes with an Avnet ZedBoard 7020 baseboard and ADI’s
AD-FMCMOTCON1-EBZ module, which is a complete drive
system providing efficient control for multiple motor types. In
addition, the kit can be extended with ADI’s AD-DYNO1-EBZ
dynamometer drive system, a dynamically adjustable load
that can be used to test real-time motor-control performance.
The AD-FMCMOTCON1-EBZ module consists of a controller
and a drive board, as shown in Figure 4.
Isolation, a critical aspect of any motor-control system, is
required to protect the controller as well as the user. Full
isolation of the analog and digital signals on the controller
board ensures that the FPGA platform is always protected
from dangerous voltages that can arise on the motor drive side.
The drive board contains all the power electronics needed to
drive the motors as well as current and voltage sensing and
protection circuits. The board features:
• Drives BLDC (brushless dc)/PMSM (permanent-magnet
synchronous motor)/brushed dc/stepper motors in the 12-V
to 48-V range with 18-A maximum current
• Dynamic braking capability and integrated overcurrent and
reverse voltage protection
• Phase-current measurement using isolated ADCs; programmable-gain amplifiers maximize the current
measurement input range
• Provides dc bus voltage, phase current, and total current
feedback signals to the controller board
• Integrated BEMF zero-crossing detection for sensorless
control of PMSM or BLDC motors
ISOLATION
ANALOG
SIGNALS
DIGITAL
I/O SIGNALS
ISOLATION
DIGITAL
SIGNALS
POSITION
SENSORS
INTERFACES
ISOLATION
RJ45
CONNECTOR
(HALL + ENCODER + RDC)
POWER
ISOLATION
Gb INDUSTRIAL
ETHERNET INTERFACE
EXTERNAL
12V TO 48V
POWER
SUPPLY
DRIVE BOARD CONNECTOR
VOLTAGE
TRANSLATION
XADC
INTERFACE
DRIVE BOARD CONNECTOR
ISOLATION
ANALOG
SIGNALS
HALL + DIFFERENTIAL HALL
+ ENCODER + RESOLVER
CONNECTORS
VOLTAGE
TRANSLATION
CURRENT
AND VOLTAGE
MEASUREMENT
VOLTAGE
TRANSLATION
LOW-VOLTAGE DRIVE BOARD
VOLTAGE
TRANSLATION
FMC LPC/HPC
XADC
CONNECTR
CONTROLLER BOARD
POWER
DIGITAL
SIGNALS
OVERCURRENT
AND REVERSE
VOLTAGE
PROTECTION
DIGITAL
SIGNALS
MOSFET
DRIVER IC
ANALOG
SIGNALS
CURRENT AND
VOLTAGE ANALOG
SIGNALS
CONDITIONING
DIGITAL
SIGNALS
CURRENT
MEASUREMENT
ADCs
DIGITAL
SIGNALS
BEMF DETECTION
FOR SENSORLESS
CONTROL
PWM
MOSFET
BRIDGE
SHUNT
RESISTORS
MOTOR
CONNECTOR
Figure 4. AD-FMCMOTCON1-EBZ block diagram.
Analog Dialogue Volume 49 Number 1
5
The dynamometer, which is a dynamically adjustable load
that can be used to test real-time motor-control performance,
consists of two BLDC motors directly coupled through a rigid
connection. One of the BLDC motors acts as a load and is
controlled by the dynometer’s embedded control system; the
second motor is driven by the ADI Intelligent Drives Kit, as
shown in Figure 5. The system, equipped with a user interface
that displays information about the load current and speed,
allows different load profiles to be set. External control can be
achieved by using the Analog Discovery USB oscilloscope for
load signal capture and control directly from MATLAB® using
the MathWorks Instrument Control Toolbox.™
close to the shunt resistor, the signal path is very short and
less prone to noise coupling. The small differential voltage on
the shunt resistor is measured directly with the AD7401 isolated Σ-Δ modulator without the need for extra interfacing and
signal conditioning circuitry. When the ADC is far from the
shunt resistor, the signal path is long and prone to noise coupling, especially from power supply switching noise and the
motor. Special care must be taken to ensure that the PC board
traces and signal conditioning circuitry between the ADC and
the shunt resistor are properly shielded. The small differential
voltage on the shunt resistor is amplified on the drive board
with the AD8207 difference amplifier, which is placed close
to the shunt resistor to avoid noise coupling. The signal is
amplified from a ±125-mV full-scale input range to a ±2.5-V
range to minimize the effect of the coupled noise. The amplified signal goes through another amplification stage using the
AD8251 programmable-gain instrumentation amplifier (PGIA),
ensuring that the ADC always receives input signals that are
properly scaled to fit the input range. The amplified analog
signals go through the connector to the controller board. The
connector includes shielding for each analog signal to mitigate
noise coupling. The analog signals coming from the drive
board are shifted back to the AD7401 input range using the
ADA4084-2 operational amplifier.
The performance of any motor-control system is greatly
influenced by the quality of motor current and voltage
measurements. By using high-performance analog signal
conditioning components and ADCs, the ADI Intelligent
Drives Kit provides precise current and voltage measurements. The measurement paths are divided between the
controller and the drive board as shown in Figure 6.
The phase currents are sensed by measuring the voltage across
shunt resistors. Two possible measurement paths aim to get
the best measurement accuracy depending on whether the
ADC is close to the shunt resistor or not. When the ADC is
INSTRUMENT
CONTROL TOOLBOX
ANALOG DISCOVERY
30-PIN CONNECTOR
DYNAMOMETER DRIVE SYSTEM
CURRENT AND
SPEED
MEASUREMENT
INTEGRATED
CONTROLLER
USER
INTERFACE
(KEYS AND LCD)
ZYNQ INTELLIGENT
DRIVES PLATFORM
3-PHASE
MOSFET
BRIDGE
G
RIGID COUPLING
M
EMBEDDED
CONTROL BOARD
Figure 5. Dynamometer drive system.
CONTROLLER BOARD
(0 ... 15)
SINC3
FILTER
CLOCK
20MHz
ISOLATION
DATA
DATA
AD7401
RC LPF
𝚺-𝚫
±250mV
MODULATOR
LOW-VOLTAGE DRIVE BOARD
ADA4084-2
±250mV
AMPLIFIER
AD8251
±2.5V
PGA
(0 ... 15)
SINC3
FILTER
±2.5V DIFFERENCE
AMPLIFIER
±2.5V
LP
AD8207
±125mV
SHUNT
RESISTOR
LN
CUTOFF
76kHz
GAIN 0.1
GAIN
1/2/4/8
DATA
DATA
RC LPF
CLOCK
20MHz
CUTOFF
100kHz
ISOLATION
FPGA
GAIN 20
AD7401
RC LPF
𝚺-𝚫
±250mV
MODULATOR
CUTOFF
76kHz
Figure 6. Phase-current signal chain.
6
Analog Dialogue Volume 49 Number 1
propagation time divided by n. The data selector outputs
the ADC code with a periodicity equal to T.
The most important part in the current and voltage feedback signal chain is the AD7401A second-order isolated Σ-Δ
modulator. This high-performance ADC features 16-bit resolution with no missing codes, 13.3 effective number of bits
(ENOB), and 83-dB SNR. The 2-wire digital interface includes
a 20-MHz clock input and a 1-bit digital bitstream output.
The ADC output is reconstructed using a sinc3 digital filter.
A filter model and HDL implementation are provided in the
data sheet for a 16-bit output and a 78-kHz sampling rate.
The output resolution and sampling rate can be controlled by
changing the filter model and decimation. While the 78-kHz
sampling rate might be good enough for many applications,
some situations require a higher rate. In these cases, filter
banks, as shown in Figure 7, can be used to increase the sampling rate of the system up to 10 MSPS of true 16-bit data. The
filter bank contains n sinc3 filters with sampling clocks that
are delayed by multiples of T, which is the sinc3 filter
AD7401
𝚺-𝚫
MODULATOR
Phase-current measurements can be also performed by the
Zynq XADC. The XADC signal measurement chain uses the
entire path of the regular measurement chain and adds a
Sallen-Key analog reconstruction filter after the AD7401 Σ-Δ
modulator. This filter is implemented on the controller board
using AD8646 operational amplifiers, as shown in Figure 8.
The combination of the isolated Σ-Δ modulator and the analog
reconstruction filter provides a convenient, low-cost way to
achieve analog isolation of the XADC input signals without
compromising the quality of the measurement.
The Analog Devices Intelligent Drives Kit comes with a set of
Simulink controller models, a complete Xilinx Vivado framework, and an ADI Linux infrastructure, allowing a user to go
through all the steps needed to design a motor-control system,
starting with simulation, going through prototyping, and finishing with the production system implementation.
DATA
SINC 3 FILTER
CLOCK
DATA
SELECTOR
SINC 3 FILTER
DELAY
ADC CODE
T
N
.
.
.
SINC 3 FILTER
DELAY
N×T
Figure 7. Filter bank.
ISOLATION
CONTROLLER BOARD
AD7401
LOW-VOLTAGE DRIVE BOARD
RC LPF
𝚺-𝚫
±250mV
±
MODULATOR
ADA4084-2
±250mV
CUTOFF
76kHZ
AMPLIFIER
GAIN 0.1
AD8251
±2.5V
PGA
GAIN
1/2/4/8
RC LPF
±2.5V
AD8207
LP
±2.5V DIFFERENCE ±125mV SHUNT
AMPLIFIER
RESISTOR
LN
GAIN 20
CUTOFF
100kHz
DIGITAL BITSTREAM
FPGA
ANALOG ISOLATION
VAUX_P
XADC
VAUX_N
ADG759
VP
AD8137
MULTI- UNIPOLAR 0V TO 1V DIFFERENTIAL 0V TO 1V
V
PLEXER
ADC DRIVER
VN
ANALOG
RECONSTRUCTION
FILTER
SALLEN-KEY,
CUTOFF 100kHz
Figure 8. XADC signal measurement chain.
Analog Dialogue Volume 49 Number 1
7
Two controller models—a six-step controller and a PMSM
field-oriented controller—can be used to start the design
process. Figure 9 shows the top-level views of these two
controllers. The six-step controller implements a trapezoidal
controller for BLDC motors; the FOC controller provides an
FOC core for integration within the control system.
The plant and controller models are created in the simulation
stage, and the behavior of the complete system is simulated
to verify that the controller is performing as expected. The
controller model is partitioned into components that will be
implemented in C code and HDL, and constraints such as
timing, fixed-point implementation, sampling rates, and loop
times are specified to ensure that the controller model behaves
as it will in the hardware implementation. Figure 10 shows
the partitioning of the six-step controller between software
and HDL.
SIX-STEP CONTROLLER AND PERIPHEREAL SIMULATION TESTBENCH
COPYRIGHT 2014 THE MATHWORKS, INC.
SYSTEM
INPUTS
MOTOR_ON
SYSTEM
ANALYSIS
ZYNQ C AND HCL COMPONENTS
VELOCITY_COMMAND
CD
M
INVERTER_GATES
HALL_A
DC
CONTINUOUS
IDEAL SWITCH
HALL_B
POWERGUI
HALL_C
ZYNQ C AND HCL COMPONENTS
PMSM FIELD-ORIENTED CONTROLLER TESTBENCH
COPYRIGHT 2010-2013 THE MATHWORKS, INC.
SYSTEM
INPUTS
SYSTEM
ANALYSIS
PMSM FOCHDIFIXPFWRAP
MOTOR_ON
INVERTER_ENABLE
COMMAND_VELOCITY
CD
M
DC
ROTOR_VELOCITY
PHASE_CURRENTS
ELECTRICAL_POSITION
PHASE_VOLTAGES
Figure 9. Simulink controller models.
ALGORITHM C
SPECIFICATION MODEL
ALGORITHM HDL
SPECIFICATION MODEL
1kHz
10MHz
SIX-STEP
SIX-ST
TEP CONTROLLER AND PERIPHEREAL
ERIPH
HEREAL SIMULATION TESTBENCH
COPYRIGHT 2014
4 THE
HE MATHWORKS, INC.
SYSTEM
INPUTS
MOTOR_ON
SYSTEM
ANALYSIS
ZYNQ
ZY
YN C AND HCL COMPONENTS
NTS
S
VELOCITY_COMMAND
D
CD
M
INVERTER_GATES
HALL_A
DC
CONTINUOUS
IDEAL SWITCH
HALL_B
POWERGUI
HALL_C
ZYNQ C AND HCL COMPONENTS
Figure 10. Controller partitioning in C code and HDL.
8
Analog Dialogue Volume 49 Number 1
Once the controller is fully verified in simulation, the next
step is to prototype it on the hardware platform. The Zynq
SoC guided workflow generates the C code and HDL from
the Simulink model partitioned into subsystems targeting the
ARM core and the programmable logic. With this workflow,
the HDL coder generates the HDL that targets the programmable logic, while the embedded coder generates the C code
targeting the ARM. The MathWorks Zynq support package
enables the generation of the ARM executable consisting of
algorithmic C code from models, which interfaces to the AXI
bus, as well as bitstream generation consisting of HDL code
from models, which interfaces to programmable logic pins
and AXI bus. Figure 11 shows the controller implementation
and the relationship with the ADI Intelligent Drive hardware.
Once the bitstream and executable are loaded into the
hardware, operational testing of the controller can begin.
Hardware-in-the-loop (HIL) testing is performed using an
Ethernet link between Simulink and the embedded system
running an open-source Linux OS. Motor parameters such
as shaft speed can be captured in Simulink and compared
against simulation results to make sure that the physical
system implementation matches the model. Once the control
algorithm testing is complete, the controller can be transferred to the production system.
PROCESSING SYSTEM
Together with the Intelligent Drives Kit, Analog Devices
provides a complete Vivado framework and a Linux
infrastructure that can be used for both prototyping and final
production. Figure 12 shows the Zynq Infrastructure that
supports the Intelligent Drives Kit. This high-level diagram
shows how the ADI reference design is partitioned on a
Xilinx Zynq SoC. The programmable logic implements the
IP cores for interfacing with the ADCs, position sensors, and
the motor drive stage. The HDL, generated by the HDL coder
to represent the motor-control algorithm, is integrated into
the Analog Devices IP. All the IPs have low-speed AXI-Lite
interfaces for configuration and control, and high-speed
AXI-Streaming interfaces that allow them to transfer realtime data through DMA channels to the software level. The
high-speed Ethernet interfaces can be implemented using
either the hard MAC peripherals of the ARM processing
system or the Xilinx Ethernet IPs in the programmable logic.
The ARM Cortex-A9 processing system runs Ubuntu Linux,
provided by Analog Devices. This includes the Linux IIO
drivers needed to interface with the Analog Devices Intelligent
Drive hardware, the IIO Oscilloscope (Scope) user space application for monitoring and control, a libiio server that allows
real-time data acquisition and system control over TCP, clients
running on a remote computer, and optional user applications
that incorporate C code generated by the embedded coder.
PROGRAMMABLE LOGIC
ZYNQ
CORTEX-A9
MOTOR FMC CARD
INVERTER
MODULE
AXI-LITE
ISOLATION
ALGORITHM HDL
SPECIFICATION MODEL
ALGORITHM C
SPECIFICATION MODEL
HALL
INTERFACE
OPEN-SOURCE
LINUX
ETHERNET
Figure 11. Controller implementation on the prototyping system.
PROGRAMMABLE LOGIC
USER APPLICATION
UART
DMA
ENCODER
(POSITION, SPEED)
DMA
HDMI/S/P-DIF
USB 2.0
ETHERNET
POWER
INVERTERS
ENCODER
INTERFACE
AD-FMCMOTCON1
USB 2.0
C CODE
ISOLATION
MOTOR
CONTROLLER
PWM
DMA
𝚺-𝚫 ADC
AXI
LIBIIO SERVER
ADC
(IA, IB, VBUS)
AXI
IIO SCOPE
DMA
AXI INTERCONNECT
ADI
UBUNTU
LINUX
AXI
ZYNQ
CORTEX-A9
AXI
PROCESSING SYSTEM
HDL CODE
Figure 12. ADI Linux infrastructure.
Analog Dialogue Volume 49 Number 1
9
All the ADI Linux drivers are based on the Linux Industrial
I/O (IIO) subsystem, which is now included in all mainline
Linux kernels. The IIO Scope, an open-source Linux application developed by Analog Devices that runs on the dual ARM
Cortex-A9s inside the Xilinx Zynq, has the ability to display
real-time data acquired from any Analog Devices FMC card
connected to the Xilinx Zynq platform. The data can be displayed either in the time domain, frequency domain, or as
a constellation plot. Different popular file formats, such as
comma separated values or .mat Matlab files, are supported to
save the captured data for further analysis. The IIO Scope provides a graphical user interface for changing or reading back
the configuration of the Analog Devices FMC cards.
The libiio server allows real-time data acquisition and
system control over TCP together with clients running on a
remote computer. The server runs on an embedded target
under Linux and manages real-time data exchange over TCP
between the target and a remote client. An IIO client is available as a system object to be integrated in native MATLAB and
Simulink applications. An HDMI output is used to display the
Linux interface on a monitor while a keyboard and mouse can
be connected to the system on a USB 2.0 port.
The Linux software and HDL infrastructure provided by ADI
for the Intelligent Drives Kit, together with the tools provided by MathWorks and Xilinx, are ideal for prototyping
motor-control applications. They also contain productionready components that can be integrated into the final control
system, thus helping to reduce the time and cost needed to
move from concept to production.
Conclusion
This article illustrates the requirements and trends of the
modern FPGA-enabled motor-control systems and the tools
and systems that MathWorks, Xilinx, and Analog Devices
bring to the market in order to meet these constraints and help
drive toward more efficient and accurate motor-control solutions. By combining the model-based design and automatic
code generation tools from MathWorks with the powerful
Xilinx Zynq SoCs and the Analog Devices isolation, power,
signal conditioning, and measurement solutions, the design,
verification, testing, and implementation of motor drive systems can be more effective than ever, leading to improved
motor-control performance and reduced time to market. The
Analog Devices Intelligent Drives Kit paired with the Avnet
Zynq-7000 All Programmable SoC provides a great prototyping environment for the motor-control algorithms designed
using Simulink from MathWorks. The Intelligent Drives Kit
comes with a set of reference designs4 intended to give a starting point for anyone who wants to evaluate the system and
help kick-start any new motor control project.
References
1. Hill, Tom. “Motor Drives Migrate to Zynq SoC with Help
from Matlab.” Xcell Journal, Issue 87, Second Quarter 2014.
2. O’Sullivan, Dara, Jens Sorensen, and Anders Frederiksen.
“Model Based Design Tools in Closed Loop Motor Control.”
PCIM Europe, 2014.
3. Corradi, Dr. Giulio. “Fpga High Efficiency, Low Noise Pulse
Frequency Space Vector Modulation—Part I.” EDN Network,
October 04, 2012.
4. AD-FMCMOTCON1-EBZ User Guide.
Andrei Cozma
Andrei Cozma [andrei.cozma@analog.com] is an engineering manager
for ADI, supporting the design and development of system level reference
designs. He holds a B.S. degree in industrial automation and informatics
and a Ph.D. in electronics and telecommunications. He has been involved in
the design and development of projects from different industry fields such
as motor control, industrial automation, software-defined radio,
and telecommunications.
Eric Cigan
Eric Cigan [Eric.Cigan@mathworks.com] is in MathWorks technical
marketing, supporting SoC and FPGA design workflows. Prior to joining
MathWorks, he held technical marketing roles at MathStar, AccelChip,
and Mentor Graphics. Eric earned a B.S. and M.S. degree in mechanical
engineering from the Massachusetts Institute of Technology.
10
Analog Dialogue Volume 49 Number 1
Powering ICs On and Off
Modern integrated circuits employ sophisticated circuits to ensure that they turn on in a known state, preserve memory, boot
quickly, and conserve power when they are powered down. This two-part article provides tips for using power-on reset and
power-down functions.
Power-On Reset
By Miguel Usach Merino
Introduction
The power-on reset (POR) circuit included in many ICs guarantees that the analog and digital blocks initialize in a known
state after the power supply is applied. The basic POR function
generates an internal reset pulse to avoid race conditions and
keep the device static until the supply voltage reaches a threshold that guarantees correct operation. Note that this threshold
voltage is not the same as the minimum power-supply voltage
shown in the data sheet. Once the supply reaches the threshold
voltage, the POR circuit releases the internal reset signal and
the state machine initializes the device. Until initialization is
complete, the device should ignore external signals, including
transmitted data. The only exception is the reset pin, which,
if included, would be internally gated with the POR signal.
A POR circuit can be represented as a window comparator,
as shown in Figure 1. The comparator level, VT2, is defined
during the circuit design depending on the device’s operational voltage and process geometry.
VDD
Brownout Detector
V1
VOLTAGE (V)
V2
I
R1
RESET
V2
R2
VT1 = VTHRESOLD
VT2
V1
RESET
VT1
VT2 = VDD × R2 / (R1+R2)
These voltages can change depending on the process and other
design variations, but these are reasonable approximations.
The threshold tolerance can be 20% or more; some old designs
had up to 40% tolerance. The high tolerance is related to
power consumption. The POR must be enabled all of the time,
so the ever-present trade-off between accuracy and power
consumption is important, as higher accuracy will make the
circuit dissipate more power in standby mode without making
a real difference in functionality.
TIME
Figure 1. Simplified POR circuit.
POR Strategy
The comparator window is typically defined by the digital
supply level. The digital block controls the analog block, and
the voltage required for the digital block to be fully functional
is similar to the minimum voltage required for the analog block
to function, as shown in Figure 2.
DIGITAL AND ANALOG
BLOCKS MALFUNCTION
The POR circuit sometimes integrates a brownout detector
(BOD), which avoids malfunction by preventing a reset if
the voltage drops unexpectedly for only a short time. From
a practical perspective, the brownout circuit adds hysteresis,
typically around 300 mV, to the threshold voltages defined in
the POR block. The BOD guarantees that once the supply falls
above VT2, the POR will not generate a reset pulse unless the
supply drops below a different threshold, VBOD, as shown in
Figure 3.
VDD SUPPLY (V)
VDD
A higher threshold for VT2 is better for the analog block, but
making it too close to the minimum recommended supply
voltage could inadvertently trigger a reset if the voltage drops
slightly. If the device includes separate analog and digital supplies, a strategy to avoid malfunctions is to add a second POR
circuit that keeps both blocks reset until the supply voltage is
high enough to ensure functionality. For example, in a 3-V IC
process, VT1 ≈ 0.8 V and VT2 ≈ 1.6 V.
2.7V
VT2 1.6V
VBOD 1.3V
POR PULSE
VT1 0.6V
DIGITAL AND ANALOG
BLOCK FUNCTIONAL
POR LEVEL
ANALOG BLOCK
RECOMMENDED
OPERATION
VT1
1.25
VT2
2.5
3.75
5
INPUT VOLTAGE (V)
Figure 2. POR threshold voltages.
DIGITAL & ANALOGUE BLOCKS MALFUNCTION
TIME
Figure 3. Brownout detector.
The brownout threshold level is high enough to guarantee
that the digital circuit retains the information, but is not high
enough to guarantee functionality. This allows the controller
to halt activity if the supply drops below some level, without
requiring the device to be reinitialized if the supply level
drops for a limited amount of time.
DIGITAL & ANALOGUE BLOCK FUNCTIONAL
ANALOG BLOCK RECOMMENDED OPERATION
Analog Dialogue Volume 49 Number 1
11
Practical POR circuits are more complex than the simple version
shown in Figure 1; using MOS transistors in place of resistors,
for example. Thus, parasitic models must be considered. Also,
the POR circuit requires a start-up block to generate the start
pulse, and this could fail under some conditions. Other important considerations are described in the following paragraphs.
It is important to use a monotonic power supply, as a nonmonotonic ramp could cause a problem if the deviation is
close to any threshold level. The high threshold variation can
cause the same nonmonotonic sequence to work in one unit,
but fail in others, as shown in Figure 4.
must be initialized first. It does not matter which supply starts
to ramp first, but the digital supply must cross the threshold
before the analog supply, as shown in Figure 6. If the delay
between supplies is on the order of 100 µs, the impact should
be minor and the device should initialize correctly.
DIGITAL SUPPLY
INPUT VOLTAGE (V)
Correct Device Power Up
VT2
ANALOG SUPPLY
0V
INPUT VOLTAGE (V)
TIME
Figure 6. Recommended supply sequence.
VT1 + 10%
VT1
VT1 − 10%
TIME
Figure 4. Nonmonotonic supply ramp.
INPUT VOLTAGE (V)
Sometimes, even when the supply is disconnected (LDO
disabled), storage capacitors retain some residual voltage, as
shown in Figure 5. This voltage should be kept as small as
possible to guarantee that the supply drops below VT1 or the POR
will not reset correctly and the device will not initialize correctly.
A poor ground connection, for example, from a board
connected to the supply with a thin cable, will have a high
ground impedance, which could generate glitches during
power up. In addition, in some electromagnetic environments
(EME), the parasitic gate capacitance of the MOS transistor
can charge, causing the transistor to malfunction until the
capacitance is discharged. This could cause a failure in the
POR initialization.
Drift and tolerance need to be considered as well. In some
cases, discrete components such as capacitors have high tolerances—up to 40%—and high drift vs. temperature, voltage,
and time. In addition, the threshold voltages have a negative
temperature coefficient. For example, VT1 could vary from 0.8 V
at room temperature to 0.9 V at –40°C and 0.7 V at +105°C.
RESIDUAL
VOLTAGE
VT1
TIME
Figure 5. Residual voltage.
Some data sheets define the recommended supply sequence
that should be applied to devices that have more than one
supply pin. It is important that this sequence be followed. For
example, consider a device with two independent supplies.
The recommended supply sequence states that the digital
supply must be powered before the analog supply (this is
common, as the digital block controls the analog block so it
must be powered first). The sequence states that the block
Power Off or Power Down?
By Dushyant Juneja
“Power down, of course!” those alarmed by the question would exclaim. Others might wonder about the
difference between the two proposals. Power-down
modes often promise memory retention, shorter boot
12
Due to internal transistor parasitics, slow supply ramps on
the order of 100 ms can cause problems. The POR circuit is
evaluated at various slew rates to guarantee correct operation
within normal power conditions. The data sheet will state
whether a fast supply ramp (100 µs or less) is required.
Conclusion
This article describes some common problems when
powering a board that could cause system problems, and
provides basic rules to guarantee correct board initialization.
The supply is often overlooked, but both its final voltage
accuracy and its transitional behavior are important.
References
Merino, Miguel Usach. “Insight into digiPOT Specifications
and Architecture Enhances AC Performance.” Analog Dialogue,
Volume 45, Number 3.
up time, and ultralow leakage current, while turning off
or gating the power does none of these things. But what
if these features are not needed? Would the designer be
wasting power by keeping the supplies stable and using
the power-down mode? Can’t we reduce the leakage
current by simply shutting off the power? Are there any
basic, underlying requirements for power-down modes?
Intrigued? Read on.
Analog Dialogue Volume 49 Number 1
Temptation and Risk
Modern systems bloom with a rich set of features, achieved
through multiple levels of design complexity that often
encompass more than one chip. Power is a concern for
many applications such as portable medical devices, so
these chips often include one or more power-down modes.
These modes provide features such as memory retention,
peripheral usage, and fast turn-on, all while drawing minimal supply current. An alternative is to do a complete
power shutdown. This tactic completely cuts the power
supplied to the chip, not allowing any current flow to its
supply pins. This reduces the power dissipation, but not
without serious side effects.
Consider the example of a complex system comprising
multiple chips connecting through a multiplexed bus. If
the system is intended for a power-constrained application, it might seem lucrative to simply shut off power to a
chip that is not currently being used, especially if the other
features offered by power-down modes are not required.
Shutting off the supplies reduces the leakage current,
but without supplies, the pins can act as low-impedance
nodes to incoming signals, resulting in unpredictable
operation and potential system-level threats. Tempting as
the power-cut option may be, power-down modes offer a
fundamental advantage for complex systems: they keep the
individual chips in known, desirable states and maintaining safe, reliable operation even as the chip cycles between
low-power and high-performance modes. The details can
be shown by looking at an I/O node.
A Simple Example
The pin in Figure 7 connects to a multiplexed node, with its
operation set by a verified system architecture. As an I/O
pin, it has both input and output functions.
M IN, P
TO INTERNAL
CIRCUIT
EXTERNAL SYSTEM
I/O LINE
M IN, N
VIO
SIMPLIFIED I/O SUBSYSTEM
DURING GENERAL OPERATION
MOUT, P
VINTERNAL
in red). A high current would ensue, possibly maxing out
the drive capacity of the previous stage, causing damage
to the MOS circuit in the chip, or both. If it did not damage
the system, it could still decrease its performance.
VF LOAT
M IN, P
TO INTERNAL
CIRCUIT
EXTERNAL SYSTEM
I/O LINE
M IN, N
VIO
EQUIVALENT I/O SUBSYSTEM
DURING POWER SHUT-OFF
VF LOAT
MOUT, P
VUNKNOWN
MOUT, N
CHIP INTERNALS
Figure 8. I/O circuit in power-cut mode. Note the unknown
state of the internal gates.
Power-Down Mode
Power-down modes equip the chip with an extra layer of
protection against these undesired operating conditions.
The implementation differs for different modes, product
families, and vendors, but the essential focus is providing a safe I/O boundary while the core of the chip sleeps,
maintaining a known, dependable, low-power state. The
advantage is that I/O operations between system components, with a system-wide multiplexed bus, for example,
do not pose a threat to the sleeping device. One implementation could put the I/O pins in a high-impedance state
during low-power mode, allowing the internal nodes connecting to the boundary pin to be in a well-defined state.
A simplified implementation is shown in Figure 9. Signals
will have no impact on the internal circuit, keeping them
intrinsically safe. Other implementations, such as lightsleep modes might keep the I/O periphery powered up as
well, while ensuring that the interaction between the chip’s
peripherals and core are verified during power-down
mode. This enables the chip to handle active use situations,
while keeping power consumption low. In addition, this
system reduces the cost of the power switch, which would
otherwise need to be a large, low-resistance device that
would consume significant leakage and on-state power.
MOUT, N
M IN, P
CHIP INTERNALS
Figure 7. Simplified I/O circuit.
Disregarding issues with the device used for the power
switch, turning off the supplies for this chip (assuming
that none of the chip operations are required) would lead
to the situation shown in Figure 8, with unknown states
scattered throughout the chip core. In the worst case, the
floating gate output devices (MOUT, p and MOUT, n) could
be exposed to unexpected external voltages while they
are electrically asleep. With a CMOS I/O, as shown in this
example, this could lead to a low-impedance connection to
ground via the drain connection of the NMOS (highlighted
Analog Dialogue Volume 49 Number 1
TO INTERNAL
CIRCUIT
EXTERNAL SYSTEM
I/O LINE
M IN, N
EQUIVALENT I/O SUBSYSTEM
IN POWER-DOWN MODE
MOUT, P
MOUT, N
CHIP INTERNALS
Figure 9. I/O circuit in power-down mode. Note that all internal
nodes are well defined.
13
Power-down modes vary from chip to chip and vendor
to vendor, so names such as “light-sleep mode” might not
always mean the same thing. Some of these enable memory
retention, while others might permit an increased number
of interrupts or other similar features. One prominent
advantage of these modes is reduced system response time,
as compared to full-power shutdown. Some circuits provide separate I/O and core supplies. One advantage of this
decoupling is that the board designer can shut off the core
supplies to reduce leakage, while keeping the I/O powered.
It is always advisable to get the exact details from the data
sheet to ensure that the required features and protection
methods are supported.
Effect of Shrinking Geometries
Modern IC process technologies offer higher density packaging as a natural consequence of reduced device sizes,
making optimal use of power-down modes increasingly
important. This also reduces the stress handling capacity
of the device, however. For instance, a 28-nm device has a
thinner gate oxide than its 180-nm technology counterpart.
Thus, the stress applied by the gate voltage in power-cut
mode would be more likely to rupture the smaller device.
In addition, layout dependent parameters could also cause
catastrophic failures in smaller geometry devices.
All of these effects make power-down modes increasingly desirable for modern devices. Packed with features,
the modern chip comprises of millions of devices, each
of which can contribute to the leakage current when
kept on. Optimizing feature usage and powering down
unused parts of the chip can save a major portion of
this leakage. Make sure that the vendor supports these
modes explicitly though, rather than trying to develop
your own power-down capability.
A Few More Situations
The power-down puzzle has more pieces. What if we cut
the ground connection as well, since that opens another
low-impedance path? This is similar to an ESD situation
where I/O pins are forced directly without enabling supplies, and if the signal strength is sufficient, it might trigger
the ESD protection structure, causing high currents to flow
through other connected I/O pins and creating a false
power-up situation. A more probable case is a signal that
is somewhat weaker, but still powerful enough to reach
the supplies through a path, such as the I/O clamp. The
signal may not be able to trigger the supply clamp, but
could create unexpected ghost voltages on the supplies,
which could cause unknown states of operation depending
on the topology of the chip. In either case, if the situation
persists, the chip might be damaged, unless the previous
stage has already stopped supplying high current. If the
signal strength is not sufficient to trigger the I/O clamp, it
still might stress the first transistor it encounters, possibly
damaging it after prolonged operation.
How about disconnecting the supplies and pulling the
supply inputs low? Now the chip has no floating supplies
and no chance of triggering any ESD structure, but the
PMOS drain can reach a higher voltage than the body, forward biasing the drain-to-body diode. The current from the
preceding stage would then flow through the PMOS device
to ground until the device burns out, the previous stage
gives up, or the designer notices the alarm.
Conclusion
Power-down modes result in a faster, safer system-wide
response, making them an indispensable feature, especially
when looking at the full signal chain in complex systems.
Complete power cutoff could be considered if interactions
between components are limited, or the system as a whole
is simple enough to ensure no complications occur.
Miguel Usach Merino
Miguel Usach Merino [miguel.usach@analog.com] received his degree in
electronic engineering from Universitat de València. Miguel joined ADI in
2008 and works as an applications engineer in the Linear and Precision
Technology Group in Valencia, Spain.
Also by this Author:
Insight into digiPOT Specifications
and Architecture Enhances
AC Performance
Volume 45, Number 3
Dushyant Juneja
Dushyant Juneja [dushyant. juneja@analog.com] is a CAD engineer at
Analog Devices. He works predominantly in AMS verification, behavioral
modeling, and ESD protection for AMS designs. He received his master’s
degree in instrumentation engineering from the Indian Institute of
Technology Kharagpur (2012), and his bachelor’s degree in electrical
engineering from the Institute of Technology (BHU) Varanasi (2010).
14
Analog Dialogue Volume 49 Number 1
Design a PLL Filter when Only the Zero
Resistor and Capacitor Are Adjustable
By Ken Gentile
Introduction
PLL System Function
As described in the references, a standard procedure can be
used to determine the values of R0, C0, and CP for a secondorder loop filter in a phase-locked loop (PLL). It uses openloop bandwidth (ω0) and phase margin (ϕM ) as design
parameters, and can be extended to third-order loop filters
to determine R2 and C2 (Figure 1). The procedure solves for
CP directly and subsequently derives the remaining values.
The small signal model shown in Figure 2 provides the
means for formulating the PLL response and a template for
analyzing phase variation at the output resulting from a phase
disturbance at the input. Note that the voltage-controlled
oscillator (VCO), being a frequency source, behaves like an
ideal phase integrator, so its gain (KV ) has a 1/s factor (the
Laplace transform equivalent of integration). Hence, the small
signal model of a PLL has frequency dependence (s = σ + jω).
In some cases, CP , R2, and C2 may be fixed-value components
integrated within the PLL, leaving only R0 and C0 available
for controlling the loop response. This nullifies the
aforementioned procedure because CP cannot be adjusted.
This article proposes an alternative procedure that can be
used when the value of CP is fixed, and addresses limitations
imposed by the inability to control the value of CP .
TO
VCO
CHARGE
PUMP
R0
CP
TO
VCO
R2
R0
CHARGE
PUMP
CP
C0
C2
C0
SECOND-ORDER
LOOP FILTER
THIRD-ORDER LOOP FILTER
Figure 1. Typical second-order and third-order passive loop filters.
This loop filter design method relies on two assumptions
that are typically used in third-order passive filter designs
that extend a second-order loop filter design to third-order
by compensating for the presence of R2 and C2 through
adjustment of R0 and C0.
(1)
) 𝑇𝑇2 (2)
𝑃𝑃 +𝐶𝐶0
𝐶𝐶𝑃𝑃
(𝐶𝐶𝑇𝑇1+𝐶𝐶=function,
)(𝑇𝑇2𝐶𝐶𝑃𝑃 )(2)
𝑇𝑇1 = transfer
The loop filter’s
in𝑇𝑇terms
of T1, T2, and CP ,
(2)
2
𝑃𝑃
0 𝐶𝐶 +𝐶𝐶
𝑃𝑃
2
(3)
1
𝐻𝐻𝐿𝐿𝐿𝐿 (𝑠𝑠𝑠
𝐻𝐻𝑂𝑂𝑂𝑂 (𝑠𝑠) = −𝐾𝐾 𝐾
)
𝑠𝑠𝑠𝑠
𝐻𝐻𝐿𝐿𝐿𝐿 (𝑠𝑠𝑠 𝐻𝐻𝐿𝐿𝐿𝐿 (𝑠𝑠𝑠
𝐻𝐻𝑂𝑂𝑂𝑂 (𝑠𝑠)𝐻𝐻=𝑂𝑂𝑂𝑂−𝐾𝐾
𝐾
)
(𝑠𝑠) =49𝑠𝑠𝑠𝑠
−𝐾𝐾
𝐾 𝑠𝑠𝑠𝑠 1(4)
)
Analog Dialogue Volume
Number
𝐻𝐻𝑂𝑂𝑂𝑂 (𝑠𝑠𝑠
(4)
(4)
(1)
) 𝑇𝑇2
FEEDBACK
𝑃𝑃 +𝐶𝐶0DIVIDER
𝐶𝐶𝑃𝑃
Figure 2. Small signal PLL model.
𝑇𝑇1 = (𝐶𝐶
𝑃𝑃 +𝐶𝐶0
(2)
(2)
) 𝑇𝑇2
The closed-loop transfer function (HCL ) for a PLL is defined
1
𝑇𝑇1
𝑠𝑠𝑠𝑠2 +1
transfer
function
(HOL ),)defined
as θOUT /θIN . The𝐻𝐻open-loop
)
(
)
(
(3)
𝐿𝐿𝐿𝐿 (𝑠𝑠𝑠 𝑠𝑠
𝐶𝐶𝑃𝑃
𝑠𝑠(𝑠𝑠𝑠𝑠1 +1)
𝑇𝑇2 transfer
as θFB /θIN , is related to the closed-loop
function. It
1
𝑇𝑇1
𝑠𝑠𝑠𝑠2 +1
) (𝑇𝑇 ) (𝑠𝑠(𝑠𝑠𝑠𝑠 +1))
(3)
is instructive to𝐻𝐻
express
𝐿𝐿𝐿𝐿 (𝑠𝑠𝑠H𝑠𝑠
CL in terms of HOL because the
𝐶𝐶𝑃𝑃
2
1
open-loop transfer function contains
clues about
closed-loop
𝐻𝐻𝐿𝐿𝐿𝐿 (𝑠𝑠𝑠
stability:
𝐻𝐻𝑂𝑂𝑂𝑂 (𝑠𝑠) = −𝐾𝐾 𝐾
(4)
)
𝑠𝑠𝑠𝑠
𝐻𝐻𝐿𝐿𝐿𝐿 (𝑠𝑠𝑠
𝑠𝑠𝑠𝑠
)
𝐻𝐻𝑂𝑂𝑂𝑂 (𝑠𝑠𝑠
(4)
(5)
)
(5)
)
(𝑗𝑗𝑗𝑗)2 𝑁𝑁𝑁𝑁𝑃𝑃
𝐶𝐶𝑃𝑃
𝑇𝑇1 1 𝑠𝑠𝑠𝑠𝑇𝑇21+1 𝑠𝑠𝑠𝑠2 +1
𝐻𝐻𝐿𝐿𝐿𝐿 (𝑠𝑠𝑠 𝐻𝐻
𝑠𝑠
)
(
) (𝑠𝑠(𝑠𝑠𝑠𝑠
(3)
𝑠𝑠
(𝑇𝑇1 +1)
) ()𝑠𝑠(𝑠𝑠𝑠𝑠 +1)
)
𝐿𝐿𝐿𝐿 (𝑠𝑠𝑠
𝐶𝐶𝑃𝑃
𝑇𝑇2 𝐶𝐶𝑃𝑃 )
2
1
𝐶𝐶𝑃𝑃
𝛉OUT
1/N
𝐻𝐻𝐶𝐶𝐶𝐶 (𝑠𝑠) = −𝑁𝑁 𝑁
A second-order loop filter has two time constants (T1 and T2)
𝑇𝑇2components:
= 𝑅𝑅0 𝐶𝐶0
(1)
associated with its
1
𝑇𝑇1 = (𝐶𝐶
VCO
(1)
1−𝐻𝐻
(𝑠𝑠𝑠
K represents the combined gains of
the𝑂𝑂𝑂𝑂phase-frequency
detector (PFD), charge pump, and𝐾𝐾VCO—that
is,2K
𝑇𝑇1
𝑠𝑠𝑠𝑠
+1= KD KV ,
𝐻𝐻charge
)
(
)
(
)
(6)
= − (current
where KD is the
in
amperes
and
𝑂𝑂𝑂𝑂 (𝑠𝑠) pump
2
𝑠𝑠 𝑁𝑁𝑁𝑁𝑃𝑃
𝑠𝑠𝑠𝑠1 +1 KV is
𝑇𝑇2
𝐾𝐾 HL F 𝑇𝑇
𝑠𝑠𝑠𝑠
+1
the VCO gain in Hz/V. HO L , HC L , and
are
all
functions
1
(𝑠𝑠) = − ( 24 shows
𝐻𝐻𝑂𝑂𝑂𝑂
) (𝑇𝑇the
) phase
(𝑠𝑠𝑠𝑠2 +1
)
(6)
of s. The negative
sign in Equation
inversion
𝑠𝑠 𝑁𝑁𝑁𝑁𝑃𝑃
2
1
implied by the negative feedback to the summing node in
𝐾𝐾
𝑇𝑇1 subtraction
𝑗𝑗𝑗𝑗𝑇𝑇 +1
in Equation
Figure 2. Defining
O L as =
(𝑗𝑗𝑗𝑗)
− ((𝑗𝑗𝑗𝑗)24 leads
𝐻𝐻𝑂𝑂𝑂𝑂H
) (to
) (𝑗𝑗𝑗𝑗𝑇𝑇2 +1)
𝑁𝑁𝑁𝑁
𝑇𝑇2an intuitive
in the denominator of Figure 5, which
provides
𝑃𝑃
1
𝐾𝐾
𝑇𝑇
𝑗𝑗𝑗𝑗𝑇𝑇 +1
explanation of closed-loop
stability.
𝐻𝐻𝑂𝑂𝑂𝑂 (𝑗𝑗𝑗𝑗) =
−(
) ( 1) ( 2 )
Transfer Function of a Second-Order Loop Filter
𝐻𝐻𝐿𝐿𝐿𝐿 (𝑠𝑠𝑠 𝑠𝑠𝐶𝐶 ) (𝑇𝑇 ) (𝑠𝑠(𝑠𝑠𝑠𝑠 +1))
FB
KV /s
1−𝐻𝐻𝑂𝑂𝑂𝑂 (𝑠𝑠𝑠
𝐻𝐻𝑂𝑂𝑂𝑂 (𝑠𝑠𝑠
2. T
he load of the series combination of R2 and C2 on the
R0-C0-CP network should be negligible.
0
is important because it plays𝑃𝑃a significant
role in the overall
1
𝑇𝑇1
𝑠𝑠𝑠𝑠2 +1
response of the PLL:
+ 𝑇𝑇2 = 𝑅𝑅 𝐶𝐶
− 𝛉 𝑇𝑇2 = 𝑅𝑅0 𝐶𝐶0
HLF(s)
LOOP
FILTER
𝐻𝐻𝐶𝐶𝐶𝐶 (𝑠𝑠) = −𝑁𝑁 𝑁
1. T
he pole frequency resulting from R2 and C2 should
be at least an order of magnitude greater than ω0 (the
desired open-loop unity-gain bandwidth); specifically
f0 ≤ 0.1/(2πR2C2), where f0 = ω0/(2π).
𝑇𝑇1 = (𝐶𝐶
KD
PFD AND
CHARGE
0 0
PUMP
𝐻𝐻𝑂𝑂𝑂𝑂 (𝑠𝑠) = −𝐾𝐾 𝐾
Assumptions
𝑇𝑇2 = 𝑅𝑅0𝑇𝑇𝐶𝐶20= 𝑅𝑅0(1)
𝐶𝐶0
𝛉IN
𝛉ERR
(3)
𝑇𝑇2
𝑗𝑗𝑗𝑗𝑇𝑇1 +1
(7)
(7)
Inspection of Equation 5 reveals a𝐾𝐾potential
stability
𝑇𝑇1 loop
𝑗𝑗𝑗𝑗𝑇𝑇
2 +1
problem. Given𝐻𝐻that
HOL is=a function
frequency
(𝜔𝜔2 𝑁𝑁𝑁𝑁 )of(complex
)
(
) (8)
𝑂𝑂𝑂𝑂 (𝑗𝑗𝑗𝑗)
𝑗𝑗𝑗𝑗𝑇𝑇
𝑇𝑇
𝑃𝑃 dependent
2
1 +1
(s = σ + jω), it necessarily has frequency
𝐾𝐾
𝑇𝑇1
𝑗𝑗𝑗𝑗𝑇𝑇magnitude
2 +1
𝐻𝐻𝑂𝑂𝑂𝑂 (𝑗𝑗𝑗𝑗)Therefore,
= (𝜔𝜔2 𝑁𝑁𝑁𝑁
) (𝑗𝑗𝑗𝑗𝑇𝑇 +1) (8)
and phase components.
if H)O(
simultaneously
𝑃𝑃 L 𝑇𝑇2
1
exhibits unity gain and zero phase shift (or any integer
𝐾𝐾
𝑇𝑇1
multiple of 2π radians) for any particular
s,1the
|𝐻𝐻 (𝑗𝑗𝑗𝑗)|
=zero,
(𝜔𝜔2 𝑁𝑁𝑁𝑁
) (value
) (of
) √(1 + 𝜔𝜔
denominator of H𝑂𝑂𝑂𝑂
becomes
the
closed-loop
gain1 )2
1+(𝜔𝜔𝜔𝜔
𝑇𝑇
CL
𝑃𝑃
2
𝐾𝐾
𝑇𝑇
1
1
becomes undefined,
the=
system
becomes
|𝐻𝐻𝑂𝑂𝑂𝑂and
(𝑗𝑗𝑗𝑗)|
(𝜔𝜔2 𝑁𝑁𝑁𝑁
) (𝑇𝑇 )completely
(1+(𝜔𝜔𝜔𝜔 )2 ) √(1 + 𝜔𝜔
unstable. This implies that stability
is governed
by the 1
𝑃𝑃
2
frequency-dependent magnitude and phase characteristics of
arctan(𝜔𝜔𝜔𝜔
𝑂𝑂𝑂𝑂(𝑗𝑗𝑗𝑗) =for
2) − arctan(𝜔𝜔𝜔𝜔
HOL . In fact, at ∠𝐻𝐻
the frequency
which the magnitude
of HOL 1) (1
is unity, the phase of HOL must stay far enough from zero (or
= arctan(𝜔𝜔𝜔𝜔2) − arctan(𝜔𝜔𝜔𝜔
∠𝐻𝐻 of(𝑗𝑗𝑗𝑗)
1) (1
any integer multiple𝑂𝑂𝑂𝑂
2π) to avoid a zero denominator
in
Equation 5.
1=(
𝐾𝐾
𝜔𝜔0 2 𝑁𝑁𝑁𝑁𝑃𝑃
𝐾𝐾
1=(
𝑇𝑇
1
) (𝑇𝑇1 ) (1+(𝜔𝜔
𝜔𝜔0 2 𝑁𝑁𝑁𝑁𝑃𝑃
2
𝑇𝑇1
2
0 𝑇𝑇1 )
1
) (𝑇𝑇 ) (1+(𝜔𝜔
2
) √(1 + 𝜔𝜔0 2 𝑇𝑇1 𝑇𝑇2 )
2
0 𝑇𝑇1 )
) √(1 +15
𝜔𝜔0 2 𝑇𝑇1 𝑇𝑇2
1
)1 𝑇𝑇)(3)
𝐻𝐻𝐿𝐿𝐿𝐿 (𝑠𝑠𝑠 𝑠𝑠𝐶𝐶 ) (𝑇𝑇 ) (𝐻𝐻𝑠𝑠(𝑠𝑠𝑠𝑠
+12
1 ( )𝑠𝑠𝑠𝑠
𝐿𝐿𝐿𝐿 (𝑠𝑠𝑠
+1)𝑠𝑠
𝑇𝑇(21 (2𝑠𝑠(𝑠𝑠𝑠𝑠
𝑠𝑠𝑠𝑠21+1
𝑃𝑃
2
1𝑠𝑠
(𝑠𝑠𝑠
)
(
)+1))) (3) (3)
𝐻𝐻
𝐶𝐶1
𝑃𝑃 ) 𝑇𝑇
𝐿𝐿𝐿𝐿
)
(
(3)
𝐻𝐻𝐿𝐿𝐿𝐿 𝐻𝐻
(𝑠𝑠𝑠𝐿𝐿𝐿𝐿 (𝑠𝑠𝑠 𝑠𝑠
𝐶𝐶𝑃𝑃
𝑇𝑇)2 ( 𝑠𝑠(𝑠𝑠𝑠𝑠
1 +1)
𝐶𝐶𝑃𝑃
𝑠𝑠(𝑠𝑠𝑠𝑠1 +1)
𝑇𝑇2
(4)
𝐻𝐻𝑂𝑂𝑂𝑂 (𝑠𝑠) = −𝐾𝐾 𝐾 𝑠𝑠𝑠𝑠 )
𝐻𝐻𝐻𝐻𝐿𝐿𝐿𝐿
(𝑠𝑠𝑠
(𝑠𝑠𝑠
𝐿𝐿𝐿𝐿
(𝑠𝑠) = −𝐾𝐾
(4)
𝐻𝐻𝐻𝐻𝑂𝑂𝑂𝑂
𝐾𝐾 𝑠𝑠𝑠𝑠 ))
−𝐾𝐾
(4)
𝑂𝑂𝑂𝑂 (𝑠𝑠)of=
The frequency, ω0, at which the magnitude
HOL
is unity,
𝑠𝑠𝑠𝑠holds great importance. The phase of HOL at ω0 defines the phase
𝐻𝐻𝐿𝐿𝐿𝐿 (𝑠𝑠𝑠
𝐻𝐻
(𝑠𝑠𝑠
𝐿𝐿𝐿𝐿OL .
margin of the system
ϕM . Both
ω0 and
ϕM can
be derived
from
H
𝐻𝐻𝑂𝑂𝑂𝑂 (𝑠𝑠)
= −𝐾𝐾
𝐾 𝑠𝑠𝑠𝑠
(4)
𝐻𝐻𝐿𝐿𝐿𝐿
𝐻𝐻)(𝑠𝑠)
= −𝐾𝐾
𝐾 𝐻𝐻(𝑠𝑠𝑠
𝑂𝑂𝑂𝑂 (𝑠𝑠)
𝐿𝐿𝐿𝐿
𝐻𝐻𝐻𝐻𝑂𝑂𝑂𝑂
=
−𝐾𝐾
𝐾
)(𝑠𝑠𝑠)) (4) (4)
𝑠𝑠𝑠𝑠
(𝑠𝑠𝑠
(𝑠𝑠)
(4)
𝐻𝐻
=
−𝐾𝐾
𝐾
𝑂𝑂𝑂𝑂
𝑠𝑠𝑠𝑠
𝑂𝑂𝑂𝑂 )
(5)
= −𝑁𝑁
𝑁01−𝐻𝐻
𝐻𝐻
(𝑠𝑠𝑠
Defining R0 and 𝐻𝐻
C0𝐶𝐶𝐶𝐶
in(𝑠𝑠)
Terms
of 𝛚
and𝑂𝑂𝑂𝑂𝛟(𝑠𝑠𝑠
𝐻𝐻𝑂𝑂𝑂𝑂
(𝑠𝑠𝑠 𝑠𝑠𝑠𝑠
M
𝑂𝑂𝑂𝑂
(𝑠𝑠)
𝐻𝐻𝐻𝐻𝐶𝐶𝐶𝐶
)
(5)
==−𝑁𝑁
−𝑁𝑁𝑁𝑁1−𝐻𝐻
(5)
𝐶𝐶𝐶𝐶 (𝑠𝑠)
(𝑠𝑠𝑠 )
𝑂𝑂𝑂𝑂
Using the design parameters ω0 and ϕ𝐻𝐻
determine the
values
1−𝐻𝐻
M to
𝑂𝑂𝑂𝑂 (𝑠𝑠𝑠of R0 and C0 requires expressions containing those four variables
𝑂𝑂𝑂𝑂 (𝑠𝑠𝑠
𝐻𝐻
(𝑠𝑠𝑠
𝑂𝑂𝑂𝑂 H . This includes H , which includes R and C via T and T .
(𝑠𝑠) =
𝐻𝐻𝐶𝐶𝐶𝐶
−𝑁𝑁
𝑁1−𝐻𝐻
)4, because
and other constant
terms.
Start
with
Equation
it 𝐻𝐻
defines
(𝑠𝑠𝑠
OL )
LF
0
0
1
2
𝐻𝐻(𝑠𝑠)
=(5)
−𝑁𝑁
𝑁𝑂𝑂𝑂𝑂
(5)
𝐶𝐶𝐶𝐶 (𝑠𝑠)
𝐻𝐻and
(𝑠𝑠𝑠
𝑂𝑂𝑂𝑂 (𝑠𝑠𝑠
𝑂𝑂𝑂𝑂
=
−𝑁𝑁
𝑁
1−𝐻𝐻
(𝑠𝑠𝑠
𝑂𝑂𝑂𝑂)ϕ
Since HOL has magnitude and phase, it𝐻𝐻
stands
to
reason
that
ω
can(5)
be incorporated
as well.
𝐶𝐶𝐶𝐶
0
M)
(5)
=
𝑁1−𝐻𝐻
𝐾𝐾 𝐻𝐻𝐶𝐶𝐶𝐶𝑇𝑇(𝑠𝑠)
𝑠𝑠𝑠𝑠2−𝑁𝑁
+11−𝐻𝐻
1
𝑂𝑂𝑂𝑂 (𝑠𝑠𝑠
(𝑠𝑠𝑠+1
𝐻𝐻𝑂𝑂𝑂𝑂 (𝑠𝑠) = − (𝑠𝑠2 ) ( ) (𝑠𝑠𝑠𝑠𝐾𝐾𝐾𝐾 ) 𝑇𝑇𝑇𝑇11(6)
𝑂𝑂𝑂𝑂
𝑠𝑠𝑠𝑠
22 +1
𝑠𝑠𝑠𝑠
𝑁𝑁𝑁𝑁
𝑇𝑇2− ( 1 +1terms
𝑃𝑃 =
(𝑠𝑠)
𝐻𝐻𝐻𝐻𝑂𝑂𝑂𝑂
)
(
)
(
)) (6)
Substituting Equation 3 into Equation
4
and
rearranging
yields
Equation
6,(6)
which presents HOL in terms of T1 and T2 along
(𝑠𝑠)
=
−
(
)
(
)
(
𝑂𝑂𝑂𝑂
𝑠𝑠𝑠𝑠22𝑁𝑁𝑁𝑁
𝑠𝑠𝑠𝑠
𝑇𝑇
22
11+1
𝑠𝑠𝑠𝑠
+1
𝐾𝐾
𝑇𝑇1
𝑠𝑠𝑠𝑠2 +1𝑁𝑁𝑁𝑁𝑃𝑃𝑃𝑃 𝐾𝐾𝑇𝑇
with constants K, N, and CP :
𝑇𝑇
𝑠𝑠𝑠𝑠
+1
(𝑇𝑇𝑂𝑂𝑂𝑂)(𝑠𝑠)
( =+1−) (𝐾𝐾 (6)𝑇𝑇)1 ( 1𝑠𝑠𝑠𝑠
𝐻𝐻𝑂𝑂𝑂𝑂 (𝑠𝑠) = − (𝑠𝑠2 𝑁𝑁𝑁𝑁 )𝐻𝐻
+12 )
2 𝑁𝑁𝑁𝑁
𝐾𝐾
𝑇𝑇(21) 2(𝑠𝑠𝑠𝑠
𝑠𝑠𝑠𝑠12)+1
+1 (6) (6)
2 =𝑠𝑠𝑠𝑠
1 (
𝐻𝐻𝑃𝑃𝑂𝑂𝑂𝑂𝐾𝐾𝐻𝐻(𝑠𝑠)
)
(
)
−
𝑠𝑠
𝑇𝑇
𝑃𝑃
2𝑗𝑗𝑗𝑗𝑇𝑇
(𝑠𝑠)
=
−
(
)
(
)
(
)
(6)
𝑇𝑇
+1
𝑠𝑠
𝑠𝑠𝑠𝑠
𝑁𝑁𝑁𝑁
𝑇𝑇
+1
1
2
𝑂𝑂𝑂𝑂
2
1
2𝑃𝑃
𝑠𝑠𝑠𝑠21+1
𝑇𝑇2 𝑗𝑗𝑗𝑗𝑇𝑇
+1
𝐻𝐻𝑂𝑂𝑂𝑂 (𝑗𝑗𝑗𝑗) = − ((𝑗𝑗𝑗𝑗)2 𝑁𝑁𝑁𝑁
) (𝑇𝑇 ) (𝑗𝑗𝑗𝑗𝑇𝑇
𝐾𝐾𝐾𝐾𝑠𝑠 𝑁𝑁𝑁𝑁𝑃𝑃) 𝑇𝑇𝑇𝑇
11 (7)
𝑗𝑗𝑗𝑗𝑇𝑇
+1
2
+1
𝑃𝑃=−
1 ))(( ))((
(𝑗𝑗𝑗𝑗)
𝐻𝐻𝐻𝐻𝑂𝑂𝑂𝑂
=
)) (7)
−of(2((𝑗𝑗𝑗𝑗)
(7)
𝑂𝑂𝑂𝑂 (𝑗𝑗𝑗𝑗)
Evaluation at s = jω, yields the frequency
response
HOL :22𝑁𝑁𝑁𝑁
𝑗𝑗𝑗𝑗𝑇𝑇
22
11+1
𝑗𝑗𝑗𝑗𝑇𝑇
𝑁𝑁𝑁𝑁𝑃𝑃𝑃𝑃 𝑇𝑇𝑇𝑇
+1
𝐾𝐾
𝑇𝑇1 (𝑗𝑗𝑗𝑗)
𝑗𝑗𝑗𝑗𝑇𝑇2 +1
𝐾𝐾 (7) 𝑇𝑇1
𝑗𝑗𝑗𝑗𝑇𝑇2 +1
𝐻𝐻𝑂𝑂𝑂𝑂 (𝑗𝑗𝑗𝑗) = − ((𝑗𝑗𝑗𝑗)2 𝑁𝑁𝑁𝑁
)
(
)
(
)
𝐾𝐾
𝑇𝑇) ( 𝑗𝑗𝑗𝑗𝑇𝑇
(𝑗𝑗𝑗𝑗)
=(−1(+1
2 +1
𝑂𝑂𝑂𝑂
𝑇𝑇=
2 ) ( 1 ) 𝑇𝑇
𝐾𝐾
𝑇𝑇(21) (𝑗𝑗𝑗𝑗𝑇𝑇
𝑗𝑗𝑗𝑗𝑇𝑇12)+1
+1)(7) (7)
𝑃𝑃
2 −𝑗𝑗𝑗𝑗𝑇𝑇
𝐻𝐻 𝐻𝐻(𝑗𝑗𝑗𝑗)
2 𝑁𝑁𝑁𝑁 𝑁𝑁𝑁𝑁𝑃𝑃𝑇𝑇
)
(
)
(
) (7)
=2 +1
−
((𝑗𝑗𝑗𝑗)
(𝑗𝑗𝑗𝑗)
𝐾𝐾 𝑂𝑂𝑂𝑂𝐻𝐻𝑂𝑂𝑂𝑂𝑇𝑇1(𝑗𝑗𝑗𝑗)
𝑗𝑗𝑗𝑗𝑇𝑇
𝑗𝑗𝑗𝑗𝑇𝑇
+1
1
2𝑃𝑃𝑁𝑁𝑁𝑁 2 𝑇𝑇
𝑗𝑗𝑗𝑗𝑇𝑇1 +1
) (𝑗𝑗𝑗𝑗)
𝐻𝐻𝑂𝑂𝑂𝑂 (𝑗𝑗𝑗𝑗) = (𝜔𝜔2 𝑁𝑁𝑁𝑁 ) (𝑇𝑇 ) (2 𝑗𝑗𝑗𝑗𝑇𝑇
𝑃𝑃2 +1 2
𝐾𝐾𝐾𝐾
𝑇𝑇𝑇𝑇
11(8)𝑗𝑗𝑗𝑗𝑇𝑇
𝑗𝑗𝑗𝑗𝑇𝑇
+1
2
2
+1
𝑃𝑃
2–ω
(𝑗𝑗𝑗𝑗)
The (jω) term in the denominator 𝐻𝐻
simplifies
to=
( : 1 ))(( ))((𝑗𝑗𝑗𝑗𝑇𝑇 )) (8)
𝐻𝐻𝑂𝑂𝑂𝑂
(8)
𝑂𝑂𝑂𝑂 (𝑗𝑗𝑗𝑗) = (𝜔𝜔𝜔𝜔22𝑁𝑁𝑁𝑁
22
11+1
𝑗𝑗𝑗𝑗𝑇𝑇
𝑁𝑁𝑁𝑁𝑃𝑃𝑃𝑃 𝑇𝑇𝑇𝑇
+1
𝐾𝐾
𝑇𝑇1
𝑗𝑗𝑗𝑗𝑇𝑇2 +1
𝐾𝐾
𝑇𝑇
𝑗𝑗𝑗𝑗𝑇𝑇
+1
1
2
𝐻𝐻𝑂𝑂𝑂𝑂 (𝑗𝑗𝑗𝑗) = (𝜔𝜔2 ) 𝐻𝐻
(𝑇𝑇𝑂𝑂𝑂𝑂)(𝑗𝑗𝑗𝑗)
(𝑗𝑗𝑗𝑗𝑇𝑇 =
) (8)𝑇𝑇)1 ( 𝑗𝑗𝑗𝑗𝑇𝑇
2 +1
𝑁𝑁𝑁𝑁𝐻𝐻
+1(𝐾𝐾𝜔𝜔 2 𝐾𝐾
𝑗𝑗𝑗𝑗𝑇𝑇12)+1
+1)(8) (8)
𝑃𝑃
2
(𝑗𝑗𝑗𝑗)
) ( ) 𝑇𝑇𝑇𝑇(1)) ((𝑗𝑗𝑗𝑗𝑇𝑇
= (1=
𝑁𝑁𝑁𝑁
) 2 (8) 2
𝐾𝐾𝑂𝑂𝑂𝑂𝐻𝐻𝑂𝑂𝑂𝑂 (𝑗𝑗𝑗𝑗)
𝑇𝑇1
1 2𝑃𝑃 𝑃𝑃𝑇𝑇)2 ( 2𝑗𝑗𝑗𝑗𝑇𝑇
𝜔𝜔 2(𝑁𝑁𝑁𝑁
1 +1
2
𝑗𝑗𝑗𝑗𝑇𝑇
𝑇𝑇2+1𝜔𝜔
) + 𝜔𝜔 2(𝑇𝑇2 −2𝑇𝑇1 )2 2 (9)
(𝜔𝜔2 𝑁𝑁𝑁𝑁 ) (𝑇𝑇 ) (1+(𝜔𝜔𝜔𝜔
)
√(1
𝑇𝑇
𝑇𝑇
11+1
𝐾𝐾𝐾𝐾 𝜔𝜔 𝑁𝑁𝑁𝑁
𝑇𝑇𝑃𝑃
The magnitude and|𝐻𝐻
phase
of HOL=are:
𝑂𝑂𝑂𝑂 (𝑗𝑗𝑗𝑗)|
2
1
2
𝑇𝑇
1
1
)( ) (
𝑃𝑃
2
1
|𝐻𝐻
(𝑗𝑗𝑗𝑗)|
=
(
)
)
√(1
+ 𝜔𝜔 2𝑇𝑇11𝑇𝑇𝑇𝑇22))2++𝜔𝜔𝜔𝜔 2(𝑇𝑇
(𝑇𝑇22−−𝑇𝑇𝑇𝑇11))22 (9)
|𝐻𝐻𝑂𝑂𝑂𝑂
) (𝑇𝑇𝑇𝑇2 ) (1+(𝜔𝜔𝜔𝜔
(9)
𝑂𝑂𝑂𝑂 (𝑗𝑗𝑗𝑗)| = (𝜔𝜔𝜔𝜔22𝑁𝑁𝑁𝑁
)2)2 ) √(1 + 𝜔𝜔 𝑇𝑇
𝑃𝑃𝑃𝑃
1
1+(𝜔𝜔𝜔𝜔
𝑁𝑁𝑁𝑁
2
1
𝐾𝐾
𝑇𝑇1
1
2
2
2
2
𝐾𝐾
𝑇𝑇
1
1
(𝑇𝑇2+−𝜔𝜔𝑇𝑇21𝑇𝑇) 𝑇𝑇 )2(9)
|𝐻𝐻𝑂𝑂𝑂𝑂 (𝑗𝑗𝑗𝑗)| = ( 2 |𝐻𝐻
2
) (𝑂𝑂𝑂𝑂
) (1+(𝜔𝜔𝜔𝜔
𝑇𝑇)1+
1 𝑇𝑇2 ) +)𝜔𝜔
(𝐾𝐾2 ) √(1
( 𝑇𝑇(𝜔𝜔
) (𝑇𝑇1+(𝜔𝜔𝜔𝜔
+2 (𝑇𝑇
𝜔𝜔 2 (𝑇𝑇
2 𝑇𝑇 𝑇𝑇 1)22+ 𝜔𝜔
21 ) (9) (9)
2𝑇𝑇−)𝑇𝑇
𝜔𝜔 𝑁𝑁𝑁𝑁
𝑇𝑇2 (𝑗𝑗𝑗𝑗)|
2 √(1
1 )1 )√(1
1 ) 𝜔𝜔 2 𝐾𝐾
|𝐻𝐻𝑃𝑃𝑂𝑂𝑂𝑂
1
(𝑗𝑗𝑗𝑗)|
= (=
)
(
+
𝜔𝜔
−
𝑁𝑁𝑁𝑁
2
2
2
2
𝑃𝑃 ) 𝑇𝑇
2
1
2
2
1
2
2
)
(𝑇𝑇
)
|𝐻𝐻
(𝑗𝑗𝑗𝑗)|
=
(
)
(
)
(
)
√(1
+
𝜔𝜔
𝑇𝑇
𝑇𝑇
+
𝜔𝜔
−
𝑇𝑇
(9)
𝜔𝜔 𝑁𝑁𝑁𝑁2𝑃𝑃
1+(𝜔𝜔𝜔𝜔1 )
𝑇𝑇
𝑂𝑂𝑂𝑂 ) − arctan(𝜔𝜔𝜔𝜔
1 2
2
1
∠𝐻𝐻𝑂𝑂𝑂𝑂(𝑗𝑗𝑗𝑗) = arctan(𝜔𝜔𝜔𝜔
𝜔𝜔 𝑁𝑁𝑁𝑁𝑃𝑃 21) 𝑇𝑇2 (10)
1+(𝜔𝜔𝜔𝜔1 )2
2
(𝑗𝑗𝑗𝑗)
)
)
= arctan(𝜔𝜔𝜔𝜔22)−−arctan(𝜔𝜔𝜔𝜔
∠𝐻𝐻
arctan(𝜔𝜔𝜔𝜔11) (10)
(10)
∠𝐻𝐻𝑂𝑂𝑂𝑂
𝑂𝑂𝑂𝑂(𝑗𝑗𝑗𝑗) = arctan(𝜔𝜔𝜔𝜔
(𝑗𝑗𝑗𝑗)
∠𝐻𝐻
=shorthand
arctan(𝜔𝜔𝜔𝜔
− arctan(𝜔𝜔𝜔𝜔
(10)
Keep in mind that
T1𝑂𝑂𝑂𝑂
and
T2 are
expressions
forarctan(𝜔𝜔𝜔𝜔
algebraic
of R0, C0, and
C
P. Evaluating Equation 9 at
2)(𝑗𝑗𝑗𝑗)
1)combinations
=
− arctan(𝜔𝜔𝜔𝜔
(10)
∠𝐻𝐻
𝑂𝑂𝑂𝑂
2)arctan(𝜔𝜔𝜔𝜔
1)(10)
(𝑗𝑗𝑗𝑗)
)
)
=
arctan(𝜔𝜔𝜔𝜔
−
ω = ω0 and setting |HOL | = 1 defines the∠𝐻𝐻
unity-gain
frequency,
ω
,
as
the
frequency
at
which
the
magnitude
of HOL is unity.
𝑂𝑂𝑂𝑂
2
1
0
∠𝐻𝐻𝑂𝑂𝑂𝑂(𝑗𝑗𝑗𝑗) = arctan(𝜔𝜔𝜔𝜔2) − arctan(𝜔𝜔𝜔𝜔1) (10)
𝐾𝐾
𝑇𝑇
1
) (𝑇𝑇1 ) (1+(𝜔𝜔
𝜔𝜔0 2 𝑇𝑇1 𝑇𝑇2 )2 + 𝜔𝜔022 (𝑇𝑇2 −2 𝑇𝑇1 )2 2 (11) 2
𝐾𝐾𝐾𝐾
𝑇𝑇)
11√(1 +11
)2 𝑇𝑇
𝑇𝑇1(
0)
11==2 ((𝜔𝜔 2𝑁𝑁𝑁𝑁
)
(
(11)
(𝑇𝑇22−−𝑇𝑇𝑇𝑇11))2
) ( 2 ) (1+(𝜔𝜔
√(1++𝜔𝜔𝜔𝜔00 2𝑇𝑇𝑇𝑇11𝑇𝑇𝑇𝑇22))2++𝜔𝜔𝜔𝜔00 2(𝑇𝑇
(11)
2 ))√(1
11))2
𝜔𝜔00 21𝑁𝑁𝑁𝑁𝑃𝑃𝑃𝑃 𝑇𝑇𝑇𝑇
1+(𝜔𝜔00𝑇𝑇𝑇𝑇
2
𝐾𝐾
𝑇𝑇1
2
2
2
2
𝐾𝐾
𝑇𝑇
1
Similarly, evaluating
Equation
10
at
ω
=
ω
and
setting
∠H
=
ϕ
defines
the
phase
margin,
ϕ
,
as
the
phase
of
H
at
frequency
1
0
OL
2
2
1 = ( 2 )( )(1
𝜔𝜔0 (𝑇𝑇
−0 2𝑇𝑇𝑇𝑇1M1)𝑇𝑇22 )2 +(11)
𝑇𝑇)1OL
1𝑇𝑇1 𝑇𝑇2 ) +
=0(𝑇𝑇𝐾𝐾1)22)𝐾𝐾)√(1
(+𝑇𝑇(1𝜔𝜔
)M(0 1+(𝜔𝜔
+22𝜔𝜔𝑇𝑇
(11)
21 )
2𝜔𝜔(𝑇𝑇
0 (𝑇𝑇
2𝑇𝑇−)𝑇𝑇
𝜔𝜔0 𝑁𝑁𝑁𝑁𝑃𝑃
1+(𝜔𝜔
𝑇𝑇2 1 =
2 ) √(1
10 𝑇𝑇)1 )√(1
ω0 (the unity gain frequency).
)
(
+
𝜔𝜔
𝑇𝑇
+
𝜔𝜔
−
𝜔𝜔0 𝑁𝑁𝑁𝑁(𝑃𝑃 ) 𝑇𝑇
2
2 (11)
2
2
2
2
1
0
1
2
0
2
2
)
(𝑇𝑇
)
1
=
(
)
(
)
(
)
√(1
+
𝜔𝜔
𝑇𝑇
𝑇𝑇
+
𝜔𝜔
−
𝑇𝑇
(11)
)
𝜔𝜔
1+(𝜔𝜔
𝑁𝑁𝑁𝑁
𝑇𝑇
𝑇𝑇
0
1
2
0
2
1
0
𝑃𝑃
2
0
1
2
2
Φ𝑀𝑀 = arctan(𝜔𝜔0𝑇𝑇2) − arctan(𝜔𝜔
(12)
𝜔𝜔0 𝑁𝑁𝑁𝑁𝑃𝑃 0𝑇𝑇
𝑇𝑇21) 1+(𝜔𝜔
0 𝑇𝑇1 )
Φ
Φ𝑀𝑀𝑀𝑀==arctan(𝜔𝜔
arctan(𝜔𝜔00𝑇𝑇𝑇𝑇22))−−arctan(𝜔𝜔
arctan(𝜔𝜔00𝑇𝑇𝑇𝑇11)) (12)
(12)
)Φ
)𝑇𝑇
Φ𝑀𝑀to=
arctan(𝜔𝜔
−
arctan(𝜔𝜔
(12)
It is a trivial matter
expand
Equation
and
Equation
12
substituting
Equation
1 for T2(12)
and Equation 2 for T1, which brings
0𝑇𝑇211
0𝑇𝑇by
10
=
arctan(𝜔𝜔
− arctan(𝜔𝜔
𝑀𝑀arctan(𝜔𝜔
2)arctan(𝜔𝜔
0𝑇𝑇1)2(12)
2
)
Φ
=
𝑇𝑇
−
2 along )+(𝐶𝐶
2
0𝑇𝑇
1)𝑇𝑇
𝑀𝑀
0
2
have
succeeded
in
relating
ω−
ϕM to
the
variables
R𝑃𝑃0𝑁𝑁𝑁𝑁
and
R0 and C0 into the equations. Hence,𝜔𝜔we
(Φ
)
𝐾𝐾) +2𝐾𝐾𝐾𝐾
𝑁𝑁𝑁𝑁0 2 ) K, N,
)
0 and
0
0 Ccos(Φ
𝑀𝑀 with𝑃𝑃constants
Φ
=
arctan(𝜔𝜔
𝑇𝑇
arctan(𝜔𝜔
(12)
𝑀𝑀
0 𝐾𝐾𝐾𝐾√1−cos
𝑀𝑀
0
2
0
1
2
2 22
2
2
𝑅𝑅
=
𝐶𝐶
=
−
(
)𝑀𝑀)+(𝐶𝐶
2
2
𝐾𝐾𝐾𝐾 +2𝐾𝐾𝐾𝐾
cos(Φ𝑀𝑀
𝜔𝜔𝜔𝜔00𝐾𝐾𝐾𝐾√1−cos
2(Φ )
0𝐴𝐴
𝑃𝑃𝑃𝑃𝑁𝑁𝑁𝑁
and CP .
)+(𝐶𝐶𝑃𝑃𝑃𝑃𝑁𝑁𝑁𝑁
2 (𝐶𝐶 𝑁𝑁𝑁𝑁
2 cos(Φ )+(𝐶𝐶
2+2𝐾𝐾𝐾𝐾
𝑁𝑁𝑁𝑁0𝑀𝑀
𝑁𝑁𝑁𝑁00 2))
𝐾𝐾𝐾𝐾√1−cos
0 ))cos(Φ
𝑁𝑁𝑁𝑁=
+𝐾𝐾 cos(Φ
𝑁𝑁𝑁𝑁=
𝑁𝑁𝑁𝑁0 2 )2 (Φ𝑀𝑀𝑀𝑀 ) 0𝐴𝐴
𝐾𝐾2 +2𝐾𝐾𝐾𝐾
0
0
𝑀𝑀
𝑃𝑃
𝑃𝑃
0
𝑅𝑅𝑅𝑅𝑃𝑃0𝐴𝐴
𝐶𝐶
−
(
))
𝐶𝐶0𝐴𝐴 = −
(
2
2 2
2
2
0𝐴𝐴 =𝐾𝐾𝐾𝐾22+2𝐾𝐾𝐾𝐾
cos(Φ
00 2(𝐶𝐶
𝑃𝑃𝑃𝑃𝑁𝑁𝑁𝑁
𝑀𝑀𝑀𝑀))
2 cos(Φ 𝑁𝑁𝑁𝑁
20)022+𝐾𝐾
(𝐶𝐶
))
)+(𝐶𝐶𝑃𝑃𝑃𝑃𝑁𝑁𝑁𝑁
+2𝐾𝐾𝐾𝐾
𝑁𝑁𝑁𝑁00 2cos(Φ
cos(Φ𝑀𝑀𝑀𝑀)+(𝐶𝐶
𝑁𝑁𝑁𝑁00 2))2 𝐾𝐾2 +2𝐾𝐾𝐾𝐾0𝐴𝐴
𝑁𝑁𝑁𝑁
𝑁𝑁𝑁𝑁
+𝐾𝐾
cos(Φ
2 (Φ𝑃𝑃𝑃𝑃𝑁𝑁𝑁𝑁
)+(𝐶𝐶
)
𝑁𝑁𝑁𝑁
𝑁𝑁𝑁𝑁
𝜔𝜔
𝐾𝐾𝐾𝐾√1−cos
2
2
®
2
2
𝑃𝑃
0 2 available
𝑀𝑀 𝐾𝐾 +2𝐾𝐾𝐾𝐾
𝑃𝑃 Mathcad
0 𝑁𝑁𝑁𝑁
𝑀𝑀 2
(Φ=
)
Simultaneously solving
for R
C
no trivial
task.
The
symbolic
processor
in
2 +2𝐾𝐾𝐾𝐾
𝜔𝜔)00is
𝐾𝐾𝐾𝐾√1−cos
𝑃𝑃 022 )
𝑀𝑀 )+(𝐶𝐶𝑃𝑃 𝑁𝑁𝑁𝑁
0 and
)+(𝐶𝐶
2)
(Φ𝑀𝑀
)0 cos(Φ
cos(Φ
𝑁𝑁𝑁𝑁
𝜔𝜔𝑅𝑅
2 (Φ
𝑅𝑅0𝐴𝐴 =the2 resulting0 equations
𝐶𝐶𝑀𝑀
𝑃𝑃 𝑁𝑁𝑁𝑁
0 =
0 𝐾𝐾𝐾𝐾√1−cos
)+(𝐶𝐶
) 𝑀𝑀 − ( 𝐾𝐾 𝑁𝑁𝑁𝑁
𝐾𝐾2cos(Φ
+2𝐾𝐾𝐾𝐾
𝑁𝑁𝑁𝑁
𝜔𝜔
2 cos(Φ
2 )2substituted
2 (𝐶𝐶
22+𝐾𝐾
=)+(𝐶𝐶
𝐶𝐶
−
(𝑀𝑀
𝑃𝑃𝑃𝑃))
0 cos(Φ
𝑀𝑀
𝑃𝑃 𝑁𝑁𝑁𝑁
0 𝐾𝐾𝐾𝐾√1−cos
2)cos(Φ
2𝑁𝑁𝑁𝑁
22cos(Φ
2 202
2𝐶𝐶(Φ
22(Φ0𝐴𝐴
0𝐴𝐴 arccos
0𝐴𝐴 −
+2𝐾𝐾𝐾𝐾
𝑁𝑁𝑁𝑁
𝑁𝑁𝑁𝑁
𝑁𝑁𝑁𝑁
( equations,
)
=
−
(
𝑅𝑅0𝐵𝐵 =𝐾𝐾 −
)+(𝐶𝐶
can solve the two simultaneous
but
must
be
for
arctan.
This
transformation
enables
the
symbolic
2
2
2
2
2
2
)
2
)+(𝐶𝐶
𝐾𝐾
+2𝐾𝐾𝐾𝐾
𝑁𝑁𝑁𝑁
𝑁𝑁𝑁𝑁
)
𝜔𝜔
𝐾𝐾𝐾𝐾√1−cos
𝐾𝐾
+2𝐾𝐾𝐾𝐾
𝑁𝑁𝑁𝑁
𝑃𝑃
0
𝑀𝑀
𝑃𝑃
0
0
𝑃𝑃
0
𝑀𝑀
𝜔𝜔
𝐾𝐾𝐾𝐾√1−cos
)+(𝐶𝐶
)
(𝐶𝐶
))
𝑃𝑃
0
𝑀𝑀
0𝐵𝐵
𝑀𝑀
0
𝑃𝑃
0
𝑀𝑀
𝑃𝑃
00 2)𝑃𝑃
𝑅𝑅
=
𝐶𝐶
=
(
+2𝐾𝐾𝐾𝐾
𝑁𝑁𝑁𝑁
cos(Φ
𝑁𝑁𝑁𝑁
𝑁𝑁𝑁𝑁
𝑁𝑁𝑁𝑁
+𝐾𝐾
cos(Φ
𝐾𝐾
0
𝑀𝑀
)+(𝐶𝐶
(Φ
)
)
2 cos(Φ
2 )2
2 (𝐶𝐶 𝑁𝑁𝑁𝑁
2+2𝐾𝐾𝐾𝐾
𝐾𝐾
𝑁𝑁𝑁𝑁
cos(Φ
𝑁𝑁𝑁𝑁
𝜔𝜔
𝐾𝐾𝐾𝐾√1−cos
𝑃𝑃
0
𝑀𝑀
𝑃𝑃
0
0
𝑃𝑃
0
𝑀𝑀
0𝐴𝐴
0𝐴𝐴
𝑃𝑃
0
𝑀𝑀
𝑃𝑃
0
𝑀𝑀
)+(𝐶𝐶
))
+2𝐾𝐾𝐾𝐾=
𝑁𝑁𝑁𝑁
𝑁𝑁𝑁𝑁
𝑁𝑁𝑁𝑁
+𝐾𝐾
cos(Φ
𝐾𝐾2𝑅𝑅
2
2
2
2
2
2
𝑃𝑃 the
𝑀𝑀𝑃𝑃
0 (R
0
𝑃𝑃R
𝑅𝑅−0𝐴𝐴
𝐶𝐶−0𝐴𝐴
( See
(𝐶𝐶Appendix
((𝐾𝐾=2+2𝐾𝐾𝐾𝐾
𝐶𝐶𝐶𝐶
=and
((0D=,0C−0D𝑁𝑁𝑁𝑁
𝑁𝑁𝑁𝑁
𝑁𝑁𝑁𝑁0𝑃𝑃 2cos(Φ
𝑁𝑁𝑁𝑁
0 𝑀𝑀
𝑀𝑀 )+(𝐶𝐶
𝑃𝑃
𝑃𝑃2𝑁𝑁𝑁𝑁
0 +𝐾𝐾2cos(Φ
𝑀𝑀 )) ))
−0following
−
𝑅𝑅0𝐵𝐵
solution
sets
, C)+(𝐶𝐶
R0B0𝑁𝑁𝑁𝑁
,2)C
R
,0𝐵𝐵
C
).
the
processor to solve for R0 and C0, yielding
2 +2𝐾𝐾𝐾𝐾
2 0C
2 cos(Φ
2;)
20B2)
22(𝐶𝐶
222+𝐾𝐾
0A
0A ;𝑁𝑁𝑁𝑁
0C ; =
0𝐵𝐵 =
0𝐵𝐵
(𝐶𝐶
)
)+(𝐶𝐶
)
))
𝑁𝑁𝑁𝑁
𝑁𝑁𝑁𝑁
𝑁𝑁𝑁𝑁
+𝐾𝐾
cos(Φ
𝐾𝐾
𝑁𝑁𝑁𝑁
cos(Φ
𝑁𝑁𝑁𝑁
cos(Φ
𝐾𝐾𝐾𝐾2+2𝐾𝐾𝐾𝐾
2
2
𝑃𝑃 00 0cos(Φ
𝑀𝑀 𝑃𝑃𝑃𝑃 𝑁𝑁𝑁𝑁
𝑃𝑃 0 )0 2
0200 𝑃𝑃
0
𝑀𝑀 ))
𝑀𝑀𝑀𝑀 )+(𝐶𝐶
𝑃𝑃𝑃𝑃 𝑁𝑁𝑁𝑁
𝑀𝑀
2
+2𝐾𝐾𝐾𝐾
𝑁𝑁𝑁𝑁002 𝑃𝑃(𝐶𝐶
2 (Φ𝑃𝑃𝑃𝑃)𝑁𝑁𝑁𝑁
) +𝐾𝐾
𝑁𝑁𝑁𝑁
𝜔𝜔0to
𝐾𝐾𝐾𝐾√1−cos
2 cos(Φ𝑀𝑀 ))
2 (Φ 0 ) 𝐾𝐾 +2𝐾𝐾𝐾𝐾𝑃𝑃 𝑁𝑁𝑁𝑁0 cos(Φ𝑀𝑀 )+(𝐶𝐶
0 𝑁𝑁𝑁𝑁
𝑀𝑀function.
for details on transforming Equation 12
use the arccos
𝐾𝐾 +2𝐾𝐾𝐾𝐾
𝜔𝜔0 𝐾𝐾𝐾𝐾√1−cos
𝑃𝑃 2 )0 cos(Φ𝑀𝑀 )+(𝐶𝐶𝑃𝑃 𝑁𝑁𝑁𝑁
𝑀𝑀(
2
2
)
𝐶𝐶
=
−
𝑅𝑅0𝐵𝐵 = − (𝐾𝐾2 +2𝐾𝐾𝐾𝐾 𝑁𝑁𝑁𝑁
)+(𝐶𝐶𝑃𝑃 𝑁𝑁𝑁𝑁0 2 )
𝐾𝐾 cos(Φ
𝑁𝑁𝑁𝑁0 cos(Φ
𝜔𝜔0 𝐾𝐾𝐾𝐾√1−cos
0𝐵𝐵(Φ2 )
2 cos(Φ
2 )2
2 −
=(−𝑀𝑀()+(𝐶𝐶
)2 𝐶𝐶=
=
(+2𝐾𝐾𝐾𝐾
𝑅𝑅0𝐵𝐵
𝑃𝑃 ))
𝑀𝑀
2 cos(Φ
0𝐵𝐵 −
)+(𝐶𝐶𝑃𝑃 𝑁𝑁𝑁𝑁
2 +2𝐾𝐾𝐾𝐾
2 cos(Φ 𝑀𝑀
2 )20𝐶𝐶(𝐶𝐶𝑃𝑃 𝑁𝑁𝑁𝑁
2 +𝐾𝐾𝑀𝑀cos(Φ
(Φ
𝐾𝐾2 +2𝐾𝐾𝐾𝐾
𝑃𝑃
𝑃𝑃 𝑁𝑁𝑁𝑁0𝜔𝜔𝑁𝑁𝑁𝑁
0 +𝐾𝐾
𝑀𝑀
)+(𝐶𝐶
(𝐶𝐶
))
𝑃𝑃2𝑁𝑁𝑁𝑁
0𝑁𝑁𝑁𝑁
0 𝐾𝐾𝐾𝐾√1−cos
𝑀𝑀 )𝑃𝑃 𝑁𝑁𝑁𝑁0𝑁𝑁𝑁𝑁
)
(
𝑅𝑅
𝑁𝑁𝑁𝑁
𝐾𝐾
𝑃𝑃
0
𝑀𝑀
0
𝑃𝑃
0
0𝐵𝐵𝑅𝑅0= −
0𝐵𝐵
2
2 2
2 (𝐶𝐶 𝑁𝑁𝑁𝑁 2 +𝐾𝐾 cos(Φ )) 𝑀𝑀
𝐶𝐶0𝐵𝐵 = − ( 𝑁𝑁𝑁𝑁02𝑁𝑁𝑁𝑁
+2𝐾𝐾𝐾𝐾
𝐾𝐾2(
2 𝑃𝑃2
0𝐵𝐵 = −
𝑃𝑃 𝑁𝑁𝑁𝑁0 cos(Φ
𝑀𝑀 )+(𝐶𝐶)+(𝐶𝐶
𝑃𝑃 𝑁𝑁𝑁𝑁0 ) 2 )2 )
0
𝑀𝑀
2 +2𝐾𝐾𝐾𝐾
2 cos(Φ
2 +𝐾𝐾 cos(Φ
2
2
(𝐶𝐶
2
𝑁𝑁𝑁𝑁
𝑁𝑁𝑁𝑁
𝑁𝑁𝑁𝑁
𝐾𝐾
𝑃𝑃
0
𝑀𝑀𝐾𝐾𝐾𝐾 + 2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝑃𝑃 𝑃𝑃𝑃𝑃0
𝑃𝑃
0
𝑀𝑀 ))
𝜔𝜔𝜔𝜔0𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1− cos ( Φ𝑀𝑀𝑀𝑀)
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 cos( Φ𝑀𝑀𝑀𝑀) + �𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 � 0
�
𝑅𝑅𝑅𝑅0𝐴𝐴𝐴𝐴 = 2
𝐶𝐶𝐶𝐶0𝐴𝐴𝐴𝐴 = − �
2
2 2
2
2
1=(
𝜔𝜔0 2 𝑁𝑁𝑁𝑁𝑃𝑃
𝐾𝐾𝐾𝐾 + 2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 cos( Φ𝑀𝑀𝑀𝑀) + ( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 )
𝜔𝜔𝜔𝜔0𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−cos2( Φ𝑀𝑀𝑀𝑀)
�
2
𝐾𝐾𝐾𝐾 + 2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 cos( Φ𝑀𝑀𝑀𝑀) + ( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 ) 2
𝑅𝑅𝑅𝑅0𝐵𝐵𝐵𝐵 = − �
𝑅𝑅𝑅𝑅 0𝐶𝐶𝐶𝐶 =
𝜔𝜔𝜔𝜔0 𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1− cos2( Φ𝑀𝑀𝑀𝑀)
2
𝐾𝐾𝐾𝐾 − 2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 cos( Φ𝑀𝑀𝑀𝑀) + ( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 ) 2
𝑅𝑅𝑅𝑅0𝐷𝐷𝐷𝐷 = − �
𝜔𝜔𝜔𝜔0 𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1− cos2( Φ𝑀𝑀𝑀𝑀)
�
2
𝐾𝐾𝐾𝐾 − 2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 cos( Φ𝑀𝑀𝑀𝑀) + ( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 ) 2
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 ( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 + 𝐾𝐾𝐾𝐾 cos( Φ𝑀𝑀𝑀𝑀))
𝐾𝐾𝐾𝐾2 + 2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 cos( Φ𝑀𝑀𝑀𝑀) + �𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 2�
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 ( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 + 𝐾𝐾𝐾𝐾 cos( Φ𝑀𝑀𝑀𝑀))
𝐶𝐶𝐶𝐶0𝐵𝐵𝐵𝐵 = − �
𝐾𝐾𝐾𝐾2 −2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 2 cos( Φ𝑀𝑀𝑀𝑀) + �𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02�
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 2( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 − 𝐾𝐾𝐾𝐾 cos( Φ𝑀𝑀𝑀𝑀))
𝐶𝐶𝐶𝐶0𝐶𝐶𝐶𝐶 = − �
2
𝐾𝐾𝐾𝐾2 −2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 2 cos( Φ𝑀𝑀𝑀𝑀) + �𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02�
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 2( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 − 𝐾𝐾𝐾𝐾 cos( Φ𝑀𝑀𝑀𝑀))
𝐶𝐶𝐶𝐶0𝐷𝐷𝐷𝐷 = − �
2
�
�
2
�
𝐾𝐾𝐾𝐾 2 − 2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃 𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁0 2 𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐( Φ𝑀𝑀𝑀𝑀 ) + (𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁0 2) 2 (13)
16
b 2 = a 2 + c 2 – ( 2ac) cosβ)
𝑅𝑅𝑅𝑅 0 =
2
𝜔𝜔𝜔𝜔0𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1− cos2( Φ𝑀𝑀𝑀𝑀)
2
(
) (
(14)
2) 2
(15)
Analog Dialogue Volume 49 Number 1
This result is problematic because the goal was to solve for R0
and C0 given ω0 and ϕM , but this indicates four possible R0, C0
pairs instead of a unique R0, C0 pair. However, closer
inspection of the four results leads to a single solution set as
follows.
0 to 1—and its denominator is the same as Expression 13, which
positive. The numerator
also cosβ)
the same(14)
as Expression 13,
b 2 = a 2 +ofc 2C–0 (is2ac)
denominator satisfies the following condition:
This is depicted graphically in Figure 3, in which the left and
2
𝐾𝐾 cos(Φ
right sides
of Equation
are 0each equated
to y (17)
(blue and
𝑀𝑀 ) > 𝐶𝐶17
𝑃𝑃 𝑁𝑁𝑁𝑁
𝜔𝜔𝜔𝜔0𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1− cos2( Φ𝑀𝑀𝑀𝑀)
green curves)𝑅𝑅𝑅𝑅with
the
horizontal
axis
sharing
ω
and ϕM .
=
(15)
0
2 cos( Φ3, )where
2 2
This
depicted 0graphically
the
( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾2−2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔Figure
𝑃𝑃𝑃𝑃 in
0 marks
𝑀𝑀𝑀𝑀
0 )left and right s
Theisintersection
of the
two curves
the+boundary
equated
to yfor(blue
and
curves)under
withwhich
the horizontal
ϕM .green
The condition
Equation 17axis shar
condition
ω0 and
is
true
appears
as
the
red
arc.
The
portion
of
the
horizontal
of
the
two
curves
marks
the
boundary
condition
for ω0 and φM. T
This result is problematic because the goal was to solve for R0 and C0 given ω0 and φM, but this
Note that in the context of modeling a PLL, all of the variables Equation
2 cos
2 2
2 −2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
axis
beneath
the
red
arc
defines
the
range
of
ϕ
and
2�M
(
)
𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
Φ
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
+
𝐶𝐶𝐶𝐶
17
is
true
appears
as
the
red
arc.
The
portion
𝑃𝑃𝑃𝑃
0
𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃
0ω�0 thatof the hori
2
2
2
2( Φ ) of a unique R0,C0 pair. Closer
,C
pairs
instead
inspection
of
the
four
indicates
four
possible
R
(
)
�
�
0
0
𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−
cos
𝐾𝐾𝐾𝐾
+
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
cos
Φ
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
+
𝐶𝐶𝐶𝐶
0
0
𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃
0 horizontal axis (16)
𝐶𝐶𝐶𝐶0 =𝑃𝑃𝑃𝑃 Note
in the
above
possess
positive𝑀𝑀𝑀𝑀
values, including
ensures
is positive.
the
on) the
2 ( point
�C0range
�C002is
𝑅𝑅𝑅𝑅0𝐴𝐴𝐴𝐴
= equations
𝐶𝐶𝐶𝐶0𝐴𝐴𝐴𝐴
= −the
( Φensures
) positive. Note t
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
of(φ
and
𝑀𝑀𝑀𝑀 ))− 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
0 that
2 cos( Φsolution
20 ω𝐾𝐾𝐾𝐾cos
results,
however,
to
a 0single
set02as
( Φblue
) 2 follows.
𝐾𝐾𝐾𝐾2leads
+ϕ2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
+ ( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃M𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
cos(ϕ
constrained
to
between
0 and π/2. defines
𝑀𝑀𝑀𝑀)values
0 + 𝐾𝐾𝐾𝐾ofcos
𝑀𝑀𝑀𝑀
directly below𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
the02intersection
the
and green curves
M ) because
M is𝑃𝑃𝑃𝑃
directly
below
intersection ofvalue
the blue
green curves estab
As a result, C0A and R0B are clearly negative quantities.
of ϕ and
establishes
ϕ the
2to ensure C0
_M A X , the maximum
2 possess
2( Φ ) all of the variables in the above
NoteTherefore,
that in the
context
ofR modeling
a PLL,
equations
(positive.
𝜔𝜔𝜔𝜔,0C
𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−cos
𝐾𝐾𝐾𝐾2to+Mensure
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
Φ𝑀𝑀𝑀𝑀) + �𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 2�M
𝑀𝑀𝑀𝑀are immediately
𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔C
0 0cos
solution
sets
and
R
,
C
is
value
of
φ
M
is
positive.
0A
0A
0B
0B
� 2
�
�
= − �between 20((and )π/2.
𝑅𝑅𝑅𝑅0𝐵𝐵𝐵𝐵 = −
𝐶𝐶𝐶𝐶
2 ) because
2 )2
2 𝐾𝐾𝐾𝐾
positive
values,
including
isnot
to0𝐵𝐵𝐵𝐵values
As
a(Φ0𝑀𝑀𝑀𝑀2)) (17)
( Φ𝑀𝑀𝑀𝑀
) + (φ
M𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾negative
+ 2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾cos(φ
𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃
𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
cos
𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁
ruled
out because
component
values
are
𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
0Mcos
0constrained
0 𝐶𝐶𝐶𝐶Φ
𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝑀𝑀𝑀𝑀 0 >+𝐶𝐶𝐶𝐶
𝑃𝑃𝑃𝑃cos
2
𝐶𝐶
𝑁𝑁𝑁𝑁
𝑃𝑃 ,C00B
acceptable.
, C0D results
require further
result,
C0A andThe
R0BRare
negative
quantities.
Therefore, solution
sets
R0A
0A and(R0B
0C , Cclearly
0C and R0D
=,Carccos
(18)
Φ𝑀𝑀_𝑀𝑀𝑀𝑀𝑀𝑀
radians
2 2
( Φ𝑀𝑀𝑀𝑀𝐾𝐾
)+
�𝐶𝐶𝐶𝐶)2𝑃𝑃𝑃𝑃(𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝜔𝜔𝜔𝜔0 𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1− cos2( Φ𝑀𝑀𝑀𝑀)
𝐾𝐾𝐾𝐾2 −2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 2𝜔𝜔𝜔𝜔cos
𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−
cos
Φ𝑀𝑀𝑀𝑀0) � �
analysis,
however.
0
are immediately
out
because
negative
component
values
are
not
acceptable.
The
R
�
0C,C0C
𝐶𝐶𝐶𝐶
=
−
𝑅𝑅𝑅𝑅0𝐶𝐶𝐶𝐶 = ruled
𝑅𝑅𝑅𝑅
=
𝐶𝐶𝐶𝐶0𝐴𝐴𝐴𝐴
0𝐶𝐶𝐶𝐶
2 𝐶𝐶𝐶𝐶 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔 2 −2𝐾𝐾𝐾𝐾 cos
0𝐴𝐴𝐴𝐴 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
( Φ𝑀𝑀𝑀𝑀
))than
2 2
𝐾𝐾𝐾𝐾2 − 2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 cos( Φ𝑀𝑀𝑀𝑀) + ( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 ) 2
2 (Φ
( 𝐶𝐶𝐶𝐶0𝑃𝑃𝑃𝑃2𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝑃𝑃𝑃𝑃 𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
0 0
𝐾𝐾𝐾𝐾20+ (2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
cos
Equation 18 requires
that
C
K in
𝑀𝑀𝑀𝑀𝐶𝐶𝐶𝐶)𝑃𝑃𝑃𝑃+
0 )order
𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
P Nω0 be less
and RNote
require
further
analysis,
however.
0D,Cthat
0D results
the four equations involving R0C , C0C , and R0D , C0D
Φ𝑀𝑀𝑀𝑀_𝑀𝑀𝑀𝑀𝐴𝐴𝐴𝐴𝑀𝑀𝑀𝑀2=of𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐
� function
(18)
2� radians
to satisfy 𝐾𝐾𝐾𝐾
the
constraints
the
arccos
2 −2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾2(02� )for ϕM_MAX
( Φ𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−cos
𝜔𝜔𝜔𝜔0 𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1− cos2( Φ𝑀𝑀𝑀𝑀)
𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 cos𝜔𝜔𝜔𝜔
𝑀𝑀𝑀𝑀) + �𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
possess
the
common
factor:
Φ
0
𝑀𝑀𝑀𝑀
� 0D,C0D possess
between
0common
and
π/2.
establishes
ω
, the�upper limit
the
factor:
Note that𝑅𝑅𝑅𝑅the
four
involving R0C,C0C and R
− �equations
=−
𝐶𝐶𝐶𝐶0𝐷𝐷𝐷𝐷
�0 2(This
�
0𝐷𝐷𝐷𝐷 =
=𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
−
𝑅𝑅𝑅𝑅�0𝐵𝐵𝐵𝐵
𝐶𝐶𝐶𝐶0𝐵𝐵𝐵𝐵
2 𝐾𝐾𝐾𝐾 cos
( Φ0_MAX
𝐾𝐾𝐾𝐾2− 2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 cos( Φ𝑀𝑀𝑀𝑀) + ( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 ) 2
0 −
𝐾𝐾𝐾𝐾2𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃
+𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 cos
Φ)) ) + ( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 ) 2
on
ensure
22�22(𝑀𝑀𝑀𝑀
2cos
0 is((positive.
��𝐶𝐶𝐶𝐶 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝜔𝜔𝜔𝜔 𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1− cos22((Φ ))
𝐾𝐾𝐾𝐾22ω+0 to
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔 2C
Φ )) + 𝑃𝑃𝑃𝑃
� 𝑀𝑀𝑀𝑀
𝜔𝜔𝜔𝜔00𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−
Φ𝑀𝑀𝑀𝑀
2 cos Φ𝑀𝑀𝑀𝑀
2 2
𝑀𝑀𝑀𝑀
𝑀𝑀𝑀𝑀 + 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃
𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔00
(13)
𝐾𝐾22 − 2𝐾𝐾𝐾𝐾
� 𝐾𝐾𝐾𝐾 + 2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃2 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔00 cos
�
𝑅𝑅𝑅𝑅0𝐴𝐴𝐴𝐴
𝐶𝐶𝐶𝐶0𝐴𝐴𝐴𝐴
𝑃𝑃𝑁𝑁𝑁𝑁0 cos(Φ𝑀𝑀) + (𝐶𝐶
𝑃𝑃𝑁𝑁𝑁𝑁0 )
0𝐴𝐴𝐴𝐴 = 𝐾𝐾𝐾𝐾
0𝐴𝐴𝐴𝐴 = −
2
((Φ
) + ((𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
))
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾2 +
+ 2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0022cos
cos((Φ
Φ𝑀𝑀𝑀𝑀
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0022))22
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔002((𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0022 +
+ 𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔cos
cos
Φ
𝐾𝐾𝐾𝐾𝑀𝑀𝑀𝑀
0 𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−
𝑀𝑀𝑀𝑀) +
𝑀𝑀𝑀𝑀))cos ( Φ𝑀𝑀𝑀𝑀)
2
2
=
𝐶𝐶𝐶𝐶0𝐶𝐶𝐶𝐶
𝑅𝑅𝑅𝑅
𝜔𝜔𝜔𝜔
=
radians/s
(19)
� cos
0𝐶𝐶𝐶𝐶 + c0_𝑀𝑀𝑀𝑀𝐴𝐴𝐴𝐴𝑀𝑀𝑀𝑀
Closer
inspection
reveals
that
Expression
13
has
the
form
(2ac)cos(β)
2 .−Equating
22) + ( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 ) 2
2
2) 2a –(13)
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0𝐶𝐶𝐶𝐶2𝑃𝑃𝑃𝑃this
𝐾𝐾𝐾𝐾 ( Φ
Closer
inspection
reveals
that
Expression
13
has
the
form
22 cos
22�𝑀𝑀𝑀𝑀
22 + 2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔 𝐾𝐾𝐾𝐾
(
)
(
220((2
𝐾𝐾𝐾𝐾
−
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁
𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐
Φ
𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁
+
𝐶𝐶𝐶𝐶
(
)
)
�
𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−cos
𝐾𝐾𝐾𝐾
Φ
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
Φ
+
𝐶𝐶𝐶𝐶
𝑃𝑃𝑃𝑃
𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃
0
(
)
)
�
�
2
𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−cos
𝐾𝐾𝐾𝐾
+
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
cos
Φ
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
Φ
+
𝐶𝐶𝐶𝐶
0
𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃
00
𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃
00
𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃
𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃
2
with
the
arbitrary
quantity,
b , this
yields:
� 2
�
�
�
–−
(2ac)cos(β)
+ c2.0Equating
with
the arbitrary
quantity,
𝑅𝑅𝑅𝑅0𝐵𝐵𝐵𝐵
𝐶𝐶𝐶𝐶0𝐵𝐵𝐵𝐵
0𝐵𝐵𝐵𝐵a=
0𝐵𝐵𝐵𝐵 = −
22 cos((Φ )) + ((𝐶𝐶𝐶𝐶 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔 22))22
22((𝐶𝐶𝐶𝐶 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔 22 + 𝐾𝐾𝐾𝐾 cos𝜔𝜔𝜔𝜔
2+
((Φ
))
𝐾𝐾𝐾𝐾
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−
cos2( Φ𝑀𝑀𝑀𝑀)
))
𝐾𝐾𝐾𝐾
+
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
cos
Φ
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
+
𝐾𝐾𝐾𝐾
cos
Φ
+
𝐶𝐶𝐶𝐶
𝐶𝐶𝐶𝐶
2
𝑃𝑃𝑃𝑃
0
𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃
0
0
𝑃𝑃𝑃𝑃
0
𝑀𝑀𝑀𝑀
0
𝑃𝑃𝑃𝑃
0
𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃
0
0
𝑃𝑃𝑃𝑃
0
𝑀𝑀𝑀𝑀
b , yields:
�
2
2
2
𝑅𝑅𝑅𝑅
𝐶𝐶𝐶𝐶0𝐷𝐷𝐷𝐷
y 0𝐷𝐷𝐷𝐷 = − �
(14)
b = a + c – (2ac)cos(β)
2 2
2− 2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔 2 cos
𝑃𝑃𝑃𝑃
0 22 22( Φ𝑀𝑀𝑀𝑀) + ( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 )
22−2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔 22cos𝐾𝐾𝐾𝐾
22((Φ ))
(
)
�
�
𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−
cos
𝐾𝐾𝐾𝐾
Φ
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
+
𝐶𝐶𝐶𝐶
(
)
�
�
2
2
2
𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−
cos
𝐾𝐾𝐾𝐾
−2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
cos
Φ
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
Φ
+
𝐶𝐶𝐶𝐶
𝑃𝑃𝑃𝑃
00
𝑃𝑃𝑃𝑃
00
𝑃𝑃𝑃𝑃
𝑃𝑃𝑃𝑃
ΔΦ = –𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀arctan(ω
C2) (20)
b00 = a + c –𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀( 2ac) cosβ) (14) 𝐶𝐶𝐶𝐶0𝐶𝐶𝐶𝐶 = − �
0R2�
𝑅𝑅𝑅𝑅0𝐶𝐶𝐶𝐶
0𝐶𝐶𝐶𝐶 = 𝐾𝐾𝐾𝐾
0𝐶𝐶𝐶𝐶 lengths of𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
2 𝐾𝐾𝐾𝐾 cos
Equation
the𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃Law
of
the0022three
triangle
2−
((Φ
((Φ
) + ((𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃relates
((𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
)) y = C N𝛚
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾214,
− 2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0022 cos
cosCosines,
Φ𝑀𝑀𝑀𝑀
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0022))22 a, b, and c as the
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔sides
− 𝐾𝐾𝐾𝐾 of
cosa
Φ
002−
𝑀𝑀𝑀𝑀
𝑀𝑀𝑀𝑀) +
𝑀𝑀𝑀𝑀))
2
K b is the square of the
with Equation
β being the
interior
angle of
the vertex
opposite side b. Because
2 22
22−2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔 22cos
2−
14, the 𝜔𝜔𝜔𝜔
Law
of Cosines,
a, b, and c as the
((Φ
)
) + ��𝑃𝑃𝑃𝑃𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃
cos
𝐾𝐾𝐾𝐾
)
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁
𝜔𝜔𝜔𝜔00𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−
𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−
cos22((Φ
𝐾𝐾𝐾𝐾
−2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
cos
Φ𝑀𝑀𝑀𝑀
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔00022��𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐( Φ𝑀𝑀𝑀𝑀 ) + (𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁0 2) 2 (13)
Φrelates
𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃
𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔00 𝐾𝐾𝐾𝐾
𝑀𝑀𝑀𝑀) +
𝑃𝑃𝑃𝑃𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
length
of
one
side
of
a
triangle,
it
must
be
a
positive
quantity,
which
implies
the
right
side
of
�
�
�
� ΦM + 2arctan(ω0R2C2)
𝑅𝑅𝑅𝑅0𝐷𝐷𝐷𝐷
= − of22the three sides
𝐶𝐶𝐶𝐶0𝐷𝐷𝐷𝐷
of((Φ
a 0triangle
with
the interior
𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−
cos222()β
0𝐷𝐷𝐷𝐷lengths
0𝐷𝐷𝐷𝐷 = −
Φ(Φ
=
22being
𝑀𝑀𝑀𝑀)
M_02MAX
M𝑀𝑀𝑀𝑀–))
2−
)) +
((𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃2𝑃𝑃𝑃𝑃𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾
cos
)Φ
(𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶2𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃Φ
))ΔΦ
𝐾𝐾𝐾𝐾 −
− 2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0022𝜔𝜔𝜔𝜔cos
cos
Φ𝑀𝑀𝑀𝑀
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0022(𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
−𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾=
cos
Φ
+cos
𝑃𝑃𝑃𝑃
00
2(
𝑃𝑃𝑃𝑃
𝑀𝑀𝑀𝑀
0
𝑀𝑀𝑀𝑀
𝑅𝑅𝑅𝑅
=
(15)
2
(
(
)
)
�𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 2�
𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−
+
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
cos
Φ
Φ
+
0also
Equation
must
positive.
Thus,𝑀𝑀𝑀𝑀
13
must be
a positive
which
means
0 side b.2 Since
𝑃𝑃𝑃𝑃
0
𝑀𝑀𝑀𝑀
angle 14
of the
opposite
b Expression
is the square
of the
2 2
2−2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾be
�
) > C N𝛚
𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 cos( Φ𝑀𝑀𝑀𝑀) + ( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 )
𝑅𝑅𝑅𝑅
=vertex
𝐶𝐶𝐶𝐶0𝐴𝐴𝐴𝐴
= −K� (𝚽quantity,
0𝐴𝐴𝐴𝐴
2
2
2
2
2
2
(
(
)
(
)
(
𝐾𝐾𝐾𝐾 R
+of
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
ΦThe
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 𝐶𝐶𝐶𝐶R
+ 𝐾𝐾𝐾𝐾 cos
+numerator
length of one side
a is
triangle,
it must
a𝐶𝐶𝐶𝐶positive
the denominator
of
positive.
of R0D is also positive, therefore
beK Φ𝑀𝑀𝑀𝑀(𝚽))) = C N𝛚
𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
0 cos
𝑀𝑀𝑀𝑀 be
𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 quantity,
𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
0D
0D 0must
2
2
2
a + c – ( 2ac) cosβ)2 (14)
whichwhich
implies
the right
sideRof Equation
14 must also
be leaves only the R ,Cb =
pair
as2 a= (Φ
negative,
rules
out 22the
2
0D,C0D solution
0C2Φ
0CMAX_NEW
2
22) 22This
2( Φ ) set.
ΔΦ
𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾
+ M_
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
ΦM_
+ �𝐶𝐶𝐶𝐶+
)
(
𝐾𝐾𝐾𝐾𝑅𝑅𝑅𝑅22 −Thus,
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁
𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐
Φ
𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁
(13)
+
𝐶𝐶𝐶𝐶
0(𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−cos
𝑀𝑀𝑀𝑀 0 quantity,
𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 cos
𝑀𝑀𝑀𝑀)MAX
𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
0 �= arccos(ω0 NCP/K )
positive.
Expression
13
must
be
a
positive
𝑃𝑃𝑃𝑃
0
𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃
2
𝑃𝑃𝑃𝑃
0
𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃
0
�
�
�
�
=
−
=
−
𝐶𝐶𝐶𝐶
2
2
2
contender
for
the
simultaneous
solution
of
Equation
11
and
Equation
12.
0𝐵𝐵𝐵𝐵
0𝐵𝐵𝐵𝐵
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0of
cos((Φ
Φ𝑀𝑀𝑀𝑀
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
2 �2
2 +−2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
02 cos
))++(�𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 ( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 + 𝐾𝐾𝐾𝐾 cos( Φ𝑀𝑀𝑀𝑀))
which means
denominator
R
positive.
The
00 )
0D is𝑀𝑀𝑀𝑀
𝐶𝐶𝐶𝐶the
(16)
0=
2 ( 𝐾𝐾𝐾𝐾cos
2 ) be
(
)
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
Φ
−
𝐶𝐶𝐶𝐶
numerator of R0D 𝜔𝜔
is0also
positive,
therefore
R
must
0
𝑃𝑃𝑃𝑃 0D 0
2 (Φ ) 𝑀𝑀𝑀𝑀
2 𝑀𝑀𝑀𝑀)
𝜔𝜔𝜔𝜔0𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1− cos2( Φ
𝐾𝐾𝐾𝐾√1−cos
𝑀𝑀 2( Φ )
𝜔𝜔𝜔𝜔0 𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−
cos
𝐾𝐾𝐾𝐾2 −2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 2 cos( Φ𝑀𝑀𝑀𝑀) + �𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02�
𝑅𝑅𝑅𝑅
=
(15)
𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃
𝑅𝑅b0𝑅𝑅𝑅𝑅22==which
(15)
,
C
solution
set.
This
leaves
negative,
rules
out
the
R
0
2
2
2 cos( Φ ) + �
2
0D
0D
2 −2𝐾𝐾𝐾𝐾
2 2ac)
2 )2
2
2
�
( 𝐶𝐶𝐶𝐶 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 2) 2
=
𝐶𝐶𝐶𝐶
=
−
𝐾𝐾𝐾𝐾
−2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
)+(𝐶𝐶
a
+
c
–
(
cosβ)
(14)
𝑁𝑁𝑁𝑁
cos(Φ
𝑁𝑁𝑁𝑁
𝐾𝐾
𝑃𝑃𝑃𝑃
0
𝑀𝑀𝑀𝑀
0𝐶𝐶𝐶𝐶
0𝐶𝐶𝐶𝐶
𝑃𝑃
0
𝑃𝑃) (0
2 𝑀𝑀
2 2
=K
(𝚽 𝑃𝑃𝑃𝑃)
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 2( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 − 𝐾𝐾𝐾𝐾 cos( Φ𝑀𝑀𝑀𝑀y))
+the
𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
only the R , C𝐾𝐾𝐾𝐾2 −
pair
as𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
a contender
simultaneous
0 cos( Φ𝑀𝑀𝑀𝑀for
0 )
P
COS
M
P
2
0
2
0
COS
0C
𝑀𝑀𝑀𝑀 𝜔𝜔𝜔𝜔0 𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−
𝑃𝑃𝑃𝑃
0
cos ( Φ𝑀𝑀𝑀𝑀)
(16)
𝐶𝐶0 𝑅𝑅𝑅𝑅= = −
�
cos(Φ𝑀𝑀 )−𝐶𝐶
𝑁𝑁𝑁𝑁�0 2 (𝐾𝐾
𝑁𝑁𝑁𝑁0 2 )
0𝐷𝐷𝐷𝐷
𝑃𝑃
22
2−𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−
2
(
))𝑀𝑀𝑀𝑀) + ( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 ) 2
(
cos
Φ
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
cos
Φ
(
𝜔𝜔𝜔𝜔00𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1−
Φ𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃 cos
0
𝑀𝑀𝑀𝑀
𝑅𝑅𝑅𝑅 00 = 22
(15)
Constraints on𝐾𝐾𝐾𝐾 R
C022cos((Φ )) + ((𝐶𝐶𝐶𝐶 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔 22))22
−2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
0 and
2
P
COS
0C
2
2 cos(Φ
2 20 2 )(17)
solution of
11
12.
𝐾𝐾2Equation
−2𝐾𝐾𝐾𝐾
(Φ
) >Equation
𝑃𝑃 𝑁𝑁𝑁𝑁
0 and
𝐾𝐾𝐾𝐾 cos
𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑃𝑃 𝑁𝑁𝑁𝑁
𝐶𝐶𝐶𝐶𝑀𝑀 )+(𝐶𝐶
M
0
M
2
𝐾𝐾𝐾𝐾2 −2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 2 cos( Φ𝑀𝑀𝑀𝑀) + �𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02�
2 (Φ (Φ
2 2
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 2(𝐾𝐾𝐾𝐾𝐶𝐶𝐶𝐶2𝑃𝑃𝑃𝑃−2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02𝑃𝑃𝑃𝑃−𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾 cos
𝑀𝑀𝑀𝑀))𝑀𝑀𝑀𝑀) + �𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 �
0 cos
0
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 ( 𝐾𝐾𝐾𝐾cos( Φ𝑀𝑀𝑀𝑀) − 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 )
𝐶𝐶𝐶𝐶0𝐷𝐷𝐷𝐷 = − �
�
𝐶𝐶𝐶𝐶 =
𝐾𝐾𝐾𝐾 −2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔00 cos Φ𝑀𝑀𝑀𝑀
𝑀𝑀𝑀𝑀 + 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃
𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔00
𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾02
Although Equation
15 and
are contenders
the simultaneous solution of Equation
Φ𝑀𝑀𝑀𝑀_𝑀𝑀𝑀𝑀𝐴𝐴𝐴𝐴𝑀𝑀𝑀𝑀
= Equation
𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 � 16
� radians for
(18)
2) 2 (13)
(𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁
𝐾𝐾𝐾𝐾 2 they
− 2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁0 2valid
𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐(𝐾𝐾𝐾𝐾ifΦthey
11 and Equation 12,
are𝑃𝑃𝑃𝑃only
in 0positive
values for both R0 and C0. Close
𝑀𝑀𝑀𝑀 )2+result
22cos( Φ ) + �𝐶𝐶𝐶𝐶 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔 22� 2
2
2 𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁 2
( Φof
𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾 cos
(17) 𝛚 , 𝚽
> 𝐶𝐶𝐶𝐶
(positive—its
)
�
�
𝐾𝐾𝐾𝐾02−2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
−2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
cos
Φ𝑀𝑀𝑀𝑀
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
+
𝐶𝐶𝐶𝐶
00
𝑃𝑃𝑃𝑃
0
inspection
of
R
shows
it
to
be
numerator
is
positive,
because the
range
(x)
𝑀𝑀𝑀𝑀 )cos
𝑃𝑃𝑃𝑃 is 0
𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃
0
𝐶𝐶𝐶𝐶00 =
(16)
0
M
22((𝐾𝐾𝐾𝐾cos((Φ )) − 𝐶𝐶𝐶𝐶 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔 22))
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
𝐾𝐾𝐾𝐾cos
Φ
−
𝐶𝐶𝐶𝐶
0
𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃
0
0 to 1—and its denominator
is𝐾𝐾𝐾𝐾𝑀𝑀𝑀𝑀the same
0
𝑃𝑃𝑃𝑃
0as Expression 13, which was 0previously shown to be
𝚽M = 𝛑/2
2 = a=
2+ c 2 – (
2ac)
𝜔𝜔𝜔𝜔b0_𝑀𝑀𝑀𝑀𝐴𝐴𝐴𝐴𝑀𝑀𝑀𝑀
radians/s
�
thecosβ)
same(19)
as (14)
Expression 13, so C0 is positive𝚽M_MAX
as long
as(Cits
positive. The numerator
of
C𝐶𝐶𝐶𝐶0 is𝐾𝐾𝐾𝐾 also
= arccos
N𝛚02/K)
P
𝑃𝑃𝑃𝑃
𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾02
Constraints
on Rthe
and
C
denominator
satisfies
following
condition:
1/2�
Φ
=
𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐
� radians
0
0
𝛚
=
[K/(C
N)]
𝑀𝑀𝑀𝑀_𝑀𝑀𝑀𝑀𝐴𝐴𝐴𝐴𝑀𝑀𝑀𝑀
2
O_MAX
P
2
𝐾𝐾𝐾𝐾
) 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃and
𝐾𝐾𝐾𝐾 cos( Φ𝑀𝑀𝑀𝑀
(17)
00
𝑀𝑀𝑀𝑀 >15
𝑃𝑃𝑃𝑃𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁
Although Equation
Equation
16 are contenders for
2
Figure 3. Constraint on C0 denominator.
𝐾𝐾 cos(Φ𝑀𝑀 ) > 𝐶𝐶𝑃𝑃 𝑁𝑁𝑁𝑁0 𝜔𝜔𝜔𝜔 𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾�1− cos2(Φ(17)
)
(16)
(18)
0
the simultaneous
of Equation
11 and 𝑀𝑀𝑀𝑀
Equation 12, (15)
𝑅𝑅𝑅𝑅 0=solution
=– arctan(ω
ΔΦ
R22positive
C2()Φ𝑀𝑀𝑀𝑀(20)
2−2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
0in
)values
( 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
)2
𝐾𝐾𝐾𝐾
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
cos
+
they
are
only
valid
if
they
result
for0 2both
𝑃𝑃𝑃𝑃
0
This is depicted graphically in Figure
sides of Equation
172 and
are C
each
22 3, where the left and rightCompensating
for R
𝐾𝐾𝐾𝐾2 (Third-Order Loop Filter)
𝐶𝐶𝐶𝐶
𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
R0 and C0. Close inspection of
it to be positive—its
𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃 R
𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
00
0 shows
and
φ
.
The
intersection
equated
to
y
(blue
and
green
curves)
with
the
horizontal
axis
sharing
ω
𝜔𝜔𝜔𝜔
=
radians/s
Φ
=
𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐
�
�
radians
(18)
�
0
M
0_𝑀𝑀𝑀𝑀𝐴𝐴𝐴𝐴𝑀𝑀𝑀𝑀
2
𝑀𝑀𝑀𝑀_𝑀𝑀𝑀𝑀𝐴𝐴𝐴𝐴𝑀𝑀𝑀𝑀
𝑀𝑀𝑀𝑀_𝑀𝑀𝑀𝑀𝐴𝐴𝐴𝐴𝑀𝑀𝑀𝑀
In
the
case
of
a
third-order
loop
components(19)
R2 and C2
numerator
is positive, because𝐾𝐾𝐾𝐾
the
range
of
cos
(x)
is
0
to
1—
𝐶𝐶𝐶𝐶
𝐾𝐾𝐾𝐾
𝑃𝑃𝑃𝑃 filter,
𝐾𝐾𝐾𝐾
and
φ
.
The
condition
under
which
of theand
two
curves
marks
the
boundary
condition
for
ω
0
M
2
introduce
additional
phase
shift,
Δϕ,
relative
to
the
secondits denominator
is
the
same
as
Expression
13,
which
was
2
2
2
(21)
ΦM_ MAX𝐾𝐾𝐾𝐾 =−2𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾
ΦM𝑃𝑃𝑃𝑃–𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔
ΔΦ
= (Φ
�𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔0 � 0R2C2)
ΦM
+ arctan(ω
0 cos
𝑀𝑀𝑀𝑀)+
order loopaxis
filter:
Equation
17 is shown
true
as the
red
arc.
The
portion
of
the
horizontal
beneath
the
red
arc
𝐶𝐶𝐶𝐶0appears
=to be positive.
(16)
previously
The
numerator
of
C
is
also
0
𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 ( 𝐾𝐾𝐾𝐾cos( Φ𝑀𝑀𝑀𝑀) − 𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾𝜔𝜔𝜔𝜔02 )
the the
same
as Expression
13,ωso
C0 is ensures
positive as
as its
is positive.
Note the point on the horizontal axis
defines
range
of φM𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾 and
C0long
0 that
ΔΦ = – arctan(ω0R2C2) (20)
denominator
satisfies
the
following
condition:
𝜔𝜔𝜔𝜔
=
radians/s
(19)
�
0_𝑀𝑀𝑀𝑀𝐴𝐴𝐴𝐴𝑀𝑀𝑀𝑀
directly below
the intersection
of the blue and green curves establishes φ
, the maximum
M_MAX R C )
0_𝑀𝑀𝑀𝑀𝐴𝐴𝐴𝐴𝑀𝑀𝑀𝑀ΦM_MAX_NEW
𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝐾𝐾𝐾𝐾
(22)
= ΦM_MAX + ΔΦ = arccos(ω02NCP/K ) – arctan(ω
0 2 2
𝐾𝐾𝐾𝐾
To
deal
with
this excess phase shift, subtract it from the
value of φM to ensure
C
is
positive.
0
2
(
)
𝐾𝐾𝐾𝐾 cos Φ > 𝐶𝐶𝐶𝐶 𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁
(17)
𝑀𝑀𝑀𝑀
𝑃𝑃𝑃𝑃
𝐶𝐶𝑃𝑃 𝑁𝑁𝑁𝑁0 2
desired value of ϕM :
0
(18)
Φ𝑀𝑀_𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 ( 𝐾𝐾 ) radians
ΔΦ = – arctan(ω00R22C22) (20)
𝐶𝐶𝐶𝐶 𝐾𝐾𝐾𝐾𝐾𝐾𝐾𝐾 2
Φ𝑀𝑀𝑀𝑀_𝑀𝑀𝑀𝑀𝐴𝐴𝐴𝐴𝑀𝑀𝑀𝑀 = 𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 � 𝑃𝑃𝑃𝑃 0 � radians (18)
𝐾𝐾𝐾𝐾
ΦM_
M_ MAX
MAX = ΦM
M – ΔΦ = ΦM
M + arctan(ω00R22C22)
𝐾𝐾𝐾𝐾
(21)
ΦM_ MAX = ΦM – ΔΦ = ΦM + arctan(ω0R2C2)
ΦM_MAX_NEW = ΦM_MAX + ΔΦ = arccos(ω02NCP/K
𝜔𝜔𝜔𝜔0_𝑀𝑀𝑀𝑀𝐴𝐴𝐴𝐴𝑀𝑀𝑀𝑀 = �
radians/s (19)
𝐶𝐶𝐶𝐶𝑃𝑃𝑃𝑃 𝐾𝐾𝐾𝐾
2
ΦM_
M_MAX_NEW
MAX_NEW = ΦM_
M_MAX
MAX + ΔΦ = arccos(ω002NCPP/K ) – arctan(ω00R22C22)
Analog Dialogue Volume 49 Number 1
(22)
17
ΔΦ = – arctan(ω0R2C2)
ΔΦ = – arctan(ω0R2C2)
(20)
(20)
ΦM_ MAX = ΦM – ΔΦ = ΦM + arctan(ω0R2C2)
(21)
Applying ϕM_NEW to Φ
Equation
15 and Equation 16 results in different values for R(21)
0 and C0 than for the second-order solution, with
M_ MAX = ΦM – ΔΦ = ΦM + arctan(ω0R2C2)
the new values compensating for the excess phase shift introduced by R2 and C2 . The presence of R2 and C2 also affects ϕM_MAX , the
(22)
= ΦM_MAX
+ of
ΔΦ
maximum allowable value of ϕMΦ
. The
new maximum
value
ϕM=(ϕarccos(ω
is2NCP/K ) – arctan(ω0R2C2)
M_MAX_NEW
M_MAX_NEW ) 0
ΦM_MAX_NEW = ΦM_MAX + ΔΦ = arccos(ω02NCP/K ) – arctan(ω0R2C2)
Conclusion
(22)
This article demonstrates using open-loop unity-gain bandwidth (ω0) and phase margin (ϕM ) as design parameters for secondorder or third-order loop filters when only components R0 and C0 are adjustable. Simulation of a PLL with a second-order loop
filter using R0 and C0 yields an exact match to the theoretical frequency response of HOL and the resulting phase margin, thereby
validating the equations. The parameters ω0 and ϕM have upper bounds for a second-order loop filter per Equation 19 and
Equation 18, respectively.
The procedure for determining R0 and C0 assumed a second-order loop filter, but is extendible to third-order loop filter designs by
adjusting the desired phase margin (ϕM ) to a new value (ϕM_NEW ) per Equation 21, yielding a new upper bound (ϕM_MAX_NEW ) per
Equation 22.
Although simulations using a second-order loop filter validated Equation 15 and Equation 16, validating the equations that
extend the design procedure to third-order loop filter designs requires a redefinition of the loop filter response, HLF (s), to include
R2 and C2 as follows:
𝐻𝐻𝐿𝐿𝐿𝐿 (𝑠𝑠) =
𝑠𝑠(𝑠𝑠 2 𝑅𝑅0 𝑅𝑅2 𝐶𝐶0 𝐶𝐶2 𝐶𝐶𝑃𝑃
𝑠𝑠𝑅𝑅0 𝐶𝐶0 + 1
+ 𝑠𝑠𝑅𝑅2 𝐶𝐶0 𝐶𝐶2 + 𝑠𝑠𝑅𝑅0 𝐶𝐶0 𝐶𝐶𝑃𝑃 + 𝑠𝑠𝑅𝑅2 𝐶𝐶2 𝐶𝐶𝑃𝑃 + 𝑠𝑠𝑅𝑅0 𝐶𝐶0 𝐶𝐶2 + 𝐶𝐶0 + 𝐶𝐶2 + 𝐶𝐶𝑃𝑃 )
𝑦𝑦 CP = 1.5 nF
The incorporation of this form of HLF into the𝑥𝑥HOL and
= 𝜃𝜃2simulations
− 𝜃𝜃1 = 𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎
( ) −loop
𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 ( )
enables
of third-order
HCL equationsΦ
1
1 R2 = 165 kΩ
filter designs using R0 and C0. Such simulations reveal the
calculated values of R0 and C0 deviate from the theoretical
C2 = 337 pF
frequency response and phase margin associated with
2
2
= using
𝑎𝑎2 +a𝑏𝑏third-order
+ 2𝑎𝑎𝑎𝑎 cos(𝜃𝜃)
is the
opposite
D = 30 μA side c)
HOL for a PLL𝑐𝑐when
loop filter.(θ
This
is angle K
predominantly due to the effect of R2 and C2 on HOL in a thirdKV = 3072 (25 ppm/V at 122.88 MHz)
order loop filter.
N = 100
2
2
2 ) +a (√1
Recall that the(𝑥𝑥
formulas
and
C0 𝑥𝑥
assume
second-order
= R(0√
1+
+ 𝑦𝑦 2 ) − 2√1 + 𝑥𝑥 2 √1 + 𝑦𝑦 2 cos Φ
− 𝑦𝑦)2for
Simulation 1 and Simulation 2 use ω0 = 100 Hz, which is near
loop filter, but R2 and C2 do not exist in a second-order filter,
the calculated upper limit of 124.8 Hz (ω0_MAX ). As such,
so including them as part of the loop filter constitutes a source
Simulation 1 and Simulation 2 deviate from the design
of error in spite of adjusting R0 and C0 to compensate for the
parameter
values (ω0 and ϕM ) by nearly 10%. On the other
phase shift introduced by R2 and C2. Even
in the
1+
𝑥𝑥𝑥𝑥 presence of
hand,
Simulation
3 and Simulation 4 use ω0 = 35 Hz, which is
Φ = simulation
𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 (indicates that using the )
this error, however,
2 )(1
approximately ¼ the upper limit. As expected, Simulation 3
+ 𝑦𝑦of2 ω) 0 to a
+ 𝑥𝑥the
adjusted values of R0 and C0, but√(1
limiting
choice
and Simulation 4 hold much closer to the design parameters
maximum of ¼ of the value dictated by Equation 19 yields
(ω
0 and ϕM ), yielding an error of only about 1%.
acceptable results. In fact, the simulated open-loop bandwidth
and phase margin results deviate only slightly from
the design
1 + 𝜔𝜔2 𝑇𝑇1loop
𝑇𝑇2 filter.
parameters (ω0 and ϕM ) for a PLL using a third-order
Φ = 𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 (
Simulation Results
√[1 + (𝜔𝜔𝑇𝑇2 )2 ][1 + (𝜔𝜔𝑇𝑇1 )2 ]
The following is the result of running four simulations of a
PLL with a third-order loop filter. The simulations all have the
following fixed-loop filter components and PLL parameters:
18
Table 1 summarizes the simulation results and also includes
)the calculated values of R0 , C0, ω0_MAX , and ϕM_MAX for the given
design parameters, ω0 and ϕM . Note that for the purpose of
comparison it would be preferable for both Simulation 1 and
Simulation 3 to use ϕM = 80°, but Simulation 1 must satisfy the
constraint imposed by Equation 22 of ϕM < 48° (hence the
choice of 42°).
Analog Dialogue Volume 49 Number 1
Table 1: Simulation Summary
Simulation 1
Parameter
Simulation 2
ϕM
ω0
ω0
Simulation 3
ϕM
ω0
Simulation 4
ϕM
ω0
ϕM
Design
100 Hz
42°
100 Hz
30°
35 Hz
80°
35 Hz
30°
Simulation
93.1 Hz
38.7°
92.5 Hz
27.1°
34.9 Hz
79.0°
34.7 Hz
29.3°
R0
969.6k kΩ
1118 kΩ
240.1 kΩ
139.9 kΩ
C0
14.85 nF
3.670 nF
225.5 nF
21.24 nF
𝛚0_MAX
124.8 Hz
124.8 Hz
124.8 Hz
124.8 Hz
𝛟M_MAX
48.0°
48.0°
84.8°
84.8°
50
80
90
60
80
40
40
70
30
20
60
0
50
−20
40
−40
30
−60
20
−80
10
1
10
100
1k
10k
100k
1M
MAGNITUDE (dB)
20
SIM 2 GAIN
SIM 2 PHASE
SIM 3 GAIN
SIM 3 PHASE
0
−10
−20
0
−30
FREQUENCY (Hz)
SIM 1 GAIN
SIM 1 PHASE
10
PEAKING
50
MAGNITUDE (dB)
−100
0.1
PHASE (DEGREES)
MAGNITUDE (dB)
Figure 4 and Figure 5 show the open- and closed-loop response for each simulation.
45
40
35
0.1
1
−40
SIM 4 GAIN
SIM 4 PHASE
−50
0.1
10
100
FREQUENCY (Hz)
1
10
1k
100
1k
10k
FREQUENCY (Hz)
SIM 1 GAIN
SIM 2 GAIN
SIM 3 GAIN
Figure 5. Closed-loop gain.
Figure 4. Open-loop gain and phase.
SIM 4 GAIN
Figure 5. Closed-loop gain.
Appendix—Converting the discontinuous arctan function to the continuous arccos f
Equation 10 demonstrates that the angle φ is the difference
angles θ2 and θ1, whe
𝑠𝑠𝑅𝑅0between
𝐶𝐶0 + 1 ) and
Equation 10 demonstrates that the angle ϕ𝐻𝐻is the
difference
between angle𝑠𝑠𝑅𝑅
θ2 and
angle
θ1, where θ2 = arctan(ωT
2
𝐶𝐶
+
1
(𝑠𝑠)
=
0
0
)
and
θ
=
arctan(ωT
).
Furthermore,
ωT
is
expressible
as
arctan(ωT
𝐿𝐿𝐿𝐿
2
1
1 as y/1:
𝑠𝑠𝑅𝑅
0 01+
θ1 = arctan(ωT1). Furthermore,
ωT is expressible
as x/1
and 2ωT
(𝑠𝑠)
𝑅𝑅
𝑅𝑅0 𝐶𝐶
𝐶𝐶
𝐶𝐶21𝐶𝐶𝑃𝑃 + 𝑠𝑠𝑅𝑅2 𝐶𝐶0 𝐶𝐶2 +2𝑠𝑠𝑅𝑅0 𝐶𝐶0 𝐶𝐶𝑃𝑃 + 𝑠𝑠𝑅𝑅2 𝐶𝐶2x/1
𝐶𝐶𝑃𝑃 and
+ 𝑠𝑠𝑅𝑅ωT
1 as
0
2y/1:
0 𝐶𝐶0 𝐶𝐶2 + 𝐶𝐶0
𝐻𝐻𝐿𝐿𝐿𝐿 (𝑠𝑠) = 𝐻𝐻𝐿𝐿𝐿𝐿2 = 𝑠𝑠(𝑠𝑠22 𝑅𝑅0 𝑅𝑅2 𝐶𝐶0 𝐶𝐶2 𝐶𝐶𝑃𝑃 + 𝑠𝑠(𝑠𝑠
𝑠𝑠𝑅𝑅2 𝐶𝐶𝐶𝐶
0 𝐶𝐶𝐶𝐶
2 + 𝑠𝑠𝑅𝑅
2
𝑥𝑥 0 𝐶𝐶20𝐶𝐶𝐶𝐶2𝑃𝑃𝐶𝐶𝑃𝑃++𝑠𝑠𝑅𝑅
𝑦𝑦𝐶𝐶2 𝐶𝐶𝑃𝑃 + 𝑠𝑠𝑅𝑅0 𝐶𝐶0 𝐶𝐶2 + 𝐶𝐶0 + 𝐶𝐶2 + 𝐶𝐶𝑃𝑃 )
𝑠𝑠(𝑠𝑠 𝑅𝑅0 𝑅𝑅2 𝐶𝐶0 𝐶𝐶2 𝐶𝐶𝑃𝑃 +Φ𝑠𝑠𝑅𝑅
0 𝑃𝑃 +
=2𝜃𝜃𝐶𝐶20 𝐶𝐶
−2 𝜃𝜃+1 𝑠𝑠𝑅𝑅
= 0arctan
( 𝑠𝑠𝑅𝑅
) − arctan 𝑠𝑠𝑅𝑅
( 0)𝐶𝐶0 𝐶𝐶2 + 𝐶𝐶0 + 𝐶𝐶2 + 𝐶𝐶𝑃𝑃 )
1
1
𝑥𝑥 by the triangles 𝑦𝑦of Figure 6 (b) and (a),
This implies the geometric relationship
shown
in
Figure
6,
with
θ
and
θ
defined
1
2
𝑦𝑦 (shown
This implies
the
in Figure
Φ geometric
= 𝑥𝑥𝜃𝜃
−𝑦𝑦𝜃𝜃1ϕrelationship
=
𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎
)between
− 𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎
( )6, with θ1 and θ2 defined by the t
2show
𝑥𝑥𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎
respectively. Figure 6 (c)
combines
these
two
triangles
to)
as the(difference
θ1 and1θ2 .
Φ
=
𝜃𝜃
−
𝜃𝜃
=
(
−
𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎
)
1
2
1
of
Figure
6
(b)
and
(a),
respectively.
Figure
6
(c)
combines
these two triangles to show φ
Φ = 𝜃𝜃2 − 𝜃𝜃1 = 𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 ( ) − 𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎
1 (1)
1
1
The law of cosines relates an interior
angle (θ)
of a triangle
to the
of the three sides of the triangle (a, b, and c) as follows:
θ2lengths
.
difference
between
θ1 and
Appendix—Converting the Discontinuous Arctan Function to the Continuous Arccos Function
2
𝑐𝑐 2 = 𝑎𝑎relates
+ 𝑏𝑏 2an
+ interior
2𝑎𝑎𝑎𝑎 cos(𝜃𝜃)
angle opposite
side c) of the three sid
The
angle (θ
(θ)isofthe
a triangle
to the lengths
2
2 Law
2 of Cosines
𝑐𝑐
=
𝑎𝑎
+
𝑏𝑏
+
2𝑎𝑎𝑎𝑎
cos(𝜃𝜃)
(θ
is
the
angle
opposite
side
c)
2
2
2
𝑐𝑐 = 𝑎𝑎 + 𝑏𝑏 + the
2𝑎𝑎𝑎𝑎triangle
cos(𝜃𝜃)(a,(θb,isand
the c)
angle
opposite side c)
as follows.
Applying the law of cosines to angle ϕ in 2Figure 26 (c) yields:
2
2 is the angle opposite
2
𝑐𝑐 = 𝑎𝑎 + 𝑏𝑏 + 2𝑎𝑎𝑎𝑎 cos(𝜃𝜃) (θ
side c)
2 𝑦𝑦)2 = (√1 +2 𝑥𝑥 2 ) + (√1 + 𝑦𝑦 2 ) − 2√1 + 𝑥𝑥 2 √1 + 𝑦𝑦 2 cos Φ
(𝑥𝑥
−
2√
2
2
2 √1 + 𝑦𝑦 2 cos Φ
1the
+ law
𝑥𝑥 2+
) of
+√to
𝑦𝑦12angle
)+ 𝑥𝑥−2 √1
2φ√in1+Figure
+𝑦𝑦 2𝑥𝑥cos
Applying
6Φ(c) yields:
√1𝑦𝑦)
(𝑥𝑥 − 𝑦𝑦)2 =(𝑥𝑥(−
+ 𝑥𝑥=2 )( +
(√1
𝑦𝑦+2cosines
)(√1
−2
2
2
(𝑥𝑥 − 𝑦𝑦)2 = (√1 + 𝑥𝑥 2 ) + (√1 + 𝑦𝑦 2 ) − 2√1 + 𝑥𝑥 2 √1 + 𝑦𝑦 2 cos Φ
1 + 𝑥𝑥𝑥𝑥
1+
)
Φ
= 𝑥𝑥𝑥𝑥
𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 (
1
+
𝑥𝑥𝑥𝑥
2 )(1 + 𝑦𝑦 2 )
)
Φ
=
𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎
(
√(1
+
𝑥𝑥
Φ = 𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 (
2)
2
√(1++𝑦𝑦𝑥𝑥
2 ) )(1 + 𝑦𝑦 )
√(1 + 𝑥𝑥 2 )(1
1 + 𝜔𝜔2 𝑇𝑇1 𝑇𝑇2
2
1
+
𝜔𝜔
𝑇𝑇
𝑇𝑇
Φ
=
𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎
(
)
1 2
1(+ 𝜔𝜔 𝑇𝑇1 𝑇𝑇2
2 ][1 + (𝜔𝜔𝑇𝑇 )2 ]
Φ
=
𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎
)
)
(𝜔𝜔𝑇𝑇
√[1
+
2
1
Φ = 𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 (
)
2
2
+ (𝜔𝜔𝑇𝑇
2 ) ][1
)2 ][1
)2 ]+ (𝜔𝜔𝑇𝑇1 ) ]
√[1 + (𝜔𝜔𝑇𝑇√[1
+ (𝜔𝜔𝑇𝑇
2
Analog Dialogue Volume 49 Number 1
2
1
19
2
(1 + y
q2
2
(1
+
x
1 + 𝑥𝑥𝑥𝑥
y
Φ = arccos (
)
√(1 + 𝑥𝑥 2 )(1 + 𝑦𝑦 2 )
q1
But, x/1 = ωT2 and y/1 = ωT1, allowing ϕ to be expressed in
1 T . y/1 = ωT1, allowing φ to be expressed in terms
T1 and
But,terms
x/1 =ofωT
2 and
2
1
½
)
(a)
X
(b)
(1 +
𝛉2
𝛉1
1
2
x
½
)
x− y
q
2 )½ 2
(1 +y
𝛉2
φ
𝛉1
j
y
x
2 )½
y
+
(1
(B)
1
(A)
+
(1
)
q1
2
x
½
)
x–y
References
References
x Paul V. Phase-Locked Loops: Principles and Practice.
Brennan,
Keese,
William
O. An Analysis and Performance Evaluation of a
2 ½
McGraw-Hill,
1996.
)
y
Technique for Charge
Pump Phase-Locked Loops. National Semi
(1 +
Keese,
William
O. AN-1001, National Semiconductor
y
AN-1001,
May 1996
Application Note, An Analysis and Performance Evaluation of
1
(c)
1
y
1 + 𝜔𝜔2 𝑇𝑇1 𝑇𝑇2
Φ = arccos (
)
√[1 + (𝜔𝜔𝑇𝑇2 )2 ][1 + (𝜔𝜔𝑇𝑇1 )2 ]
a Passive
FilterV.,
Design
Technique for Charge
Pump
Phase-Locked
Brennan,
Paul
Phase-Locked
Loops:
Principles
and Practice, M
Loops. May 1996.
MT-086:
Fundamentals
Phase Locked
Loops (PLLs)
MT-086:
Fundamentals of of
Phase-Locked
Loops (PLLs).
VCOs.
PLLsPLLs/PLLs
/ PLLs with
withIntegrated
Integrated
VCOs
of Equation 10.
(C)
Figure 6. of
Geometric
Figure 6. Geometric representation
Equation 10. representation
Solving
Solvingfor
forφ...
ϕ:
Author
Ken Gentile [ken.gentile@analog.com] is a system design engine
Φ = arccos (
)
Greensboro, NC. As a member of the Clock and Signal Synthesis
√(1 + 𝑥𝑥 2 )(1 + 𝑦𝑦 2 )
system level design and analysis of signal synthesis ICs.
But, x/1 = ωT2 and y/1 = ωT1, allowing φ to be expressed in terms of T1 and T2.
1 + 𝑥𝑥𝑥𝑥
1 + joined
𝜔𝜔2 𝑇𝑇1Analog
𝑇𝑇2 Devices in 1998 as a system design
Ken Gentile [ken.gentile@analog.com]
Φ
=
arccos
(
)
engineer with the Clock and Signal Synthesis
product
2 ][1 + (𝜔𝜔𝑇𝑇line
2in]Greensboro, NC, where
(𝜔𝜔𝑇𝑇
)
)
√[1
+
2 analog filter design,
1
he specializes in direct digital synthesis,
and writing GUI-based
engineering tools in MATLAB. Ken holds 10 patents. He has published 14 articles in
References
various industry trade journals and over a dozen ADI application notes, as well as having
at ADI’s
annual
General Technical
Conference (GTC)
in 2001, 2005,of
anda2006.
Keese,presented
William
O. An
Analysis
and Performance
Evaluation
Passive Filter Design
He graduated with honors in 1996 with a B.S.E.E. from North Carolina State University. In
Technique
for
Charge
Pump
Phase-Locked
Loops.
National
Semiconductor
Application
his spare time, Ken enjoys reading, mathematical puzzles, and most anything related to
AN-1001,
May
1996 and “backyard” astronomy.
science,
engineering,
Ken Gentile
Also by this Author:
Reconstruct a DAC
Transfer Function
from Its Harmonic
NoteSpectral Content
Volume 43, Number 1
Brennan, Paul V., Phase-Locked Loops: Principles and Practice, McGraw-Hill, 1996
MT-086: Fundamentals of Phase Locked Loops (PLLs)
PLLs / PLLs with Integrated VCOs
Author
Ken Gentile [ken.gentile@analog.com] is a system design engineer at Analog Devices in
Greensboro, NC. As a member of the Clock and Signal Synthesis product line, he performs
system level design and analysis of signal synthesis ICs.
EVAL-ADF4350EB1Z evaluation board.
20
Analog Dialogue Volume 49 Number 1
Quickly Implement JESD204B on a
Xilinx FPGA
By Haijiao Fan
Introduction
JESD204 is a high-speed serial interface for connecting data
converters (ADCs and DACs) to logic devices. Revision B of
the standard supports serial data rates up to 12.5 Gbps and
ensures repeatable, deterministic latency on the JESD204 link.
As the speed and resolution of converters continues to increase,
the JESD204B interface has become ever more common in
ADI’s high-speed converters and integrated RF transceivers.
In addition, flexible serializer/deserializer (SERDES) designs
in FPGAs and ASICs have naturally started to replace the
traditional parallel LVDS/CMOS interface to converters, and
are used to implement the JESD204B physical layer. This article describes how to quickly set up a project using a Xilinx
FPGA to implement the JESD204B interface, and provides
some application and debug suggestions for FPGA designers.
synchronization, setup, and maintenance, and encodes/
decodes the optionally scrambled octets to/from 10-bit characters. The physical layer is responsible for transmission and
reception of characters at the bit rate.
Tx
APPLICATION
LAYER
Rx
APPLICATION
LAYER
TRANSPORT
LAYER
TRANSPORT
LAYER
SCRAMBLING
LAYER
SCRAMBLING
LAYER
DATA LINK
LAYER
DATA LINK
LAYER
PHYSICAL (PHY)
LAYER
PHYSICAL (PHY)
LAYER
JESD204B Protocol Implementation Overview
HIGH-SPEED SERIAL LANES
The JESD204B specification defines four key layers that implement the protocol data stream, as shown in Figure 1. The
transport layer maps the conversion between samples and
framed, unscrambled octets. The optional scrambling layer
scrambles/descrambles the octets, spreading the spectral
peaks to reduce EMI. The data-link layer handles link
Figure 1. Key layers of JESD204B standard.
Different JESD204B IP vendors may implement the layers
in different ways. Figure 2 and Figure 3 illustrate how the
JESD204B transmit and receive protocols are implemented
by ADI.
TRANSPORT LAYER
PROCESSED
SAMPLES
FROM ADC
SAMPLE
CONSTRUCTION
LINK LAYER
FRAME
CONSTRUCTION
SCRAMBLER
FRAME/LANE
ALIGNMENT
CHARACTER
GENERATION
PHYSICAL LAYER
8B/10B
ENCODER
SERIALIZER
OUTPUT
Figure 2. JESD204B transmitter implementation.
PHYSICAL LAYER
INPUT
DESERIALIZER
LINK LAYER
8B/10B
DECODER
FRAME/LANE
ALIGNMENT
CHARACTER
DETECTION
TRANSPORT LAYER
DESCRAMBLER
DEFRAMER
SAMPLES
TO DAC(s)
Figure 3. JESD204B receiver implementation.
Analog Dialogue Volume 49 Number 1
21
The transport layer implementation depends strongly on the specific converter’s configuration and how it maps between samples
and frames, so most FPGA vendors exclude it from their JESD204 IP. In addition, highly configurable, tightly integrated SERDES
transceivers are integrated in FPGAs. These can be used to support all kinds of serial protocols, including PCIe, SATA, SRIO,
CPRI, and JESD204B. Thus, a logic core that implements the link layer, combined with a configurable SERDES that realizes the
physical layer, forms the basis for a JESD204B link. Figure 4 and Figure 5 show block diagrams of a JESD204B transmitter and
receiver on a Xilinx FPGA. The transmitter/receiver lanes implement the scramble and link layers; the 8B/10B encoder/decoder
and the physical layer are implemented in the GTP/GTX/GTH gigabit transceivers.
Tx LANE(S)
AXI4-STREAM
JESD204
TRANSMITTER CORE
ALIGNMENT
CHARACTER
GENERATOR
SCRAMBLER
GTX/
GTH/
GTP
LANE
ALIGNMENT
SEQUENCE
SYNC/SYSREF
AXI4-LITE
CONTROL
JESD204
SERIAL
DATA
RPAT
GENERATOR
Tx COUNTERS
JSPAT
GENERATOR
AXI4-LITE/IPIF
REGISTERS
Figure 4. JESD204B transmitter implementation using a Xilinx FPGA.
JESD204
RECEIVE CORE
Rx LANE(S)
DESCRAMBLER
GTX/
GTH/
GTP
ALIGNMENT
REPLACE
DATA
AXI4-STREAM
DECODE LANE
ALIGNMENT
SEQUENCE
LINK
ERROR
COUNTER
LMFC AND
STATUS
SYSREF
AXI4-LITE
CONTROL
SYNC
AXI4-LITE/IPIF
REGISTERS
Figure 5. JESD204B receiver implementation using a Xilinx FPGA.
22
Analog Dialogue Volume 49 Number 1
JESD204B Design Example Using a Xilinx FPGA
Symbol Alignment in the Xilinx SERDES Transceiver
The latest Xilinx JESD204 IP core is delivered and encrypted
as a black box via the Vivado® Design Suite. Xilinx also provides a Verilog example design using the Advanced eXtensible
Interface (AXI), but this example project is overdesigned for
most applications. Users typically have their own configuration interfaces and do not need to integrate an extra AXI
for JESD204B logic. Figure 6 shows a simplified JESD204
design, which is intended to help FPGA users understand the
structure of JESD204 and quickly start their own FPGA-based
JESD204 project.
In the SERDES receiver, serial data must be aligned to symbol
boundaries before it can be used as parallel data. To align
the data, the transmitter sends a recognizable sequence,
usually called a comma. The receiver searches for a comma
in the incoming serial data stream and moves it to a symbol
boundary once found. This enables the received parallel
words to match the transmitted parallel words. The comma
is usually a K, which is a special character in 8B/10B table
used for control symbols. For JESD204B applications, the
transmitter will send a stream of K = K28.5 symbols for code
group synchronization (CGS). The FPGA can therefore use
K28.5 as a comma to align symbol boundaries and users can
specify whether a comma match consists of either a comma
plus (running disparity is plus) or a comma minus (running
disparity is minus), or both. The JESD204B default setting for
GTX/GTH comma detection allows either a comma plus or a
comma minus to align the comma.
FPGA TOP
STATUS
MONITOR
JESD204B USER TOP
ENCRYPTED RTL
CONFIGURE
LOGIC
SAMPLE
PROCESSING
F2S
CONTROL
AND STATUS
GTX/
GTH
FOR GTX/GTH
JESD204 DATA
CLOCK/
RESET
Figure 6. JESD204B design example.
The encrypted register-transfer language (RTL) block—the
JESD204 logic IP core generated by Vivado—is equivalent to
the transmitter and receiver modules shown in Figure 4 and
Figure 5. The encrypted interface definition can be found in
the Xilinx example design files. Then the encrypted RTL is
wrapped into the JESD204B user top. Control, configuration,
status, and JESD data interfaces from the encrypted RTL go
through the wrapper to connect with user logic and the
GTX/GTH transceiver data. Symbol alignment configuration
for GTX/GTH is optimized and updated to make the transceivers work more robustly.
Dedicated pads should be used for the GTX/GTH reference
clock to the SERDES transceivers. Careful attention must be
paid to the global clock design for the FPGA logic, including
clocks for the internal PLL, parallel interface, JESD204 logic
core, and user-specific processing logic. In addition, the
master system reference (SYSREF) input for the JESD204B
logic core (Subclass 1) must be captured accurately to
guarantee the deterministic delay of the JESD204 link.
The reset sequence for the GTX/GTH transceivers and the
JESD204 core is crucial for reliable JESD link initialization,
so the JESD204 core should be in reset state until the internal
PLL in the GTX/GTH transceiver is locked and the GTX/GTH
has been reset.
A frame-to-samples (F2S) module is needed to implement the
transport layer of JESD204, which maps samples to or from
frames according to the specific JESD204B configuration. The
samples are then processed by application-specific logic. An
auxiliary module monitors the JESD204 logic and physical
layer (PHY) status for system debug.
Analog Dialogue Volume 49 Number 1
In some applications, the default comma setting may result
in symbol realignment, or alignment to the wrong symbol
boundary. This can cause messy 8B/10B decoding errors and
broken JESD204B links. Combined comma plus and minus is
more robust, forcing the comma align block to search for two
commas in a row, detecting a comma only when the received
data has a comma plus or minus followed by a comma minus
or plus with no extra bits in between. This helps to maintain
symbol boundaries and link stability when the line rate is high
or the system has excessive noise.
Design Consideration for JESD204 Projects on FPGA
A synchronous, active low sync signal from the JESD204
receiver to the transmitter indicates the state of synchronization. Link reinitialization during normal operation will cause
messy samples data, so the link status must be monitored
in real time. In particular, a continuous low on sync means
the receiver cannot identify at least four consecutive K28.5
symbols in the received data stream. If this occurs, check the
transmitter/receiver SERDES configuration or make sure that
the transmitter is sending K28.5. A continuous high on sync
means the link has established and maintained stability. When
sync goes from high to low and back to high, the duration of
the low state should be counted. If it is longer than five frames
plus nine octets, the receiver has detected a large error and
sends a request to reinitialize the JESD204 link. If the duration is equal to two frame clocks, the receiver has detected a
small error, but does not trigger a link reinitialization. This
function can significantly ease system debug and further link
monitoring, so users should include it in their designs.
8B/10B decoding errors can lead to JESD204B link reinitialization, but they are not the only cause, so user designs should
have the ability to count decoding errors of each lane to determine the cause of link resynchronization. Also, the SERDES
link quality can be determined in real time by the 8B/10B
decoding error status.
23
Pseudorandom bit sequences (PRBS) provide a useful resource
for measuring signal quality and jitter tolerance in high-speed
links. The SERDES transceiver in most FPGAs has a built-in
PRBS generator and checker, so no extra FPGA resources are
needed. Thus, do not forget to instantiate this function, which
should be used when the bit-error rate (BER) or eye diagram
is evaluated.
A buffer is always used in SERDES transceivers to change the
internal clock domain. A bad clock design for the transmitter
and receiver or the wrong clock and data recovery (CDR)
setting can cause buffer overflow or underflow. Some link
errors may occur in this case, so monitoring the buffer status
is meaningful. An interrupt record for buffer overflow and
underflow is useful for system debug, so other internal buffers
that are not allowed to underflow or overflow in user logic
should also be monitored.
Conclusion
This article showed how to quickly implement a JESD204
block on a Xilinx FPGA, but the method can be applied to
other FPGAs as well. First, understand the function and
interfaces of the JESD204 logic core and transceiver provided
by the FPGA vendor, then instantiate them and wrap them
into your logic. Second, globally design the FPGA clock tree
and reset sequence for your entire project. Third, carefully
define the interfaces between the JESD204 logic core, user
logic, and transceivers. Finally, add necessary debug resources.
Following these steps will help you to achieve a quick and
successful design for your JESD204 interface.
High-Speed Analog-to-Digital Converters
High-Speed Digital-to-Analog Converters
Integrated Transceivers, Transmitters, and Receivers
Alliances and FPGA Reference Designs
Demystifying the JESD204B High-Speed Data Converter-toFPGA Interface
Beavers, Ian. “Demystifying Deterministic Latency Within
JESD204B Converters.” Electronic Design, 2/25/2014.
Beavers, Ian. “Prototyping Systems: JESD204B Converters and
FPGAs.” Electronic Design, 1/23/2014.
Beavers, Ian and Jeffrey Ugalde. “Designing JESD204B
Converter Systems for Low BER, Part 1.” EDN, 10/22/2014.
Beavers, Ian and Jeffrey Ugalde. “Designing JESD204B
Converter Systems for Low BER, Part 2.” EDN, 10/28/2014.
Harris, Jonathan. “Understanding Layers in the JESD204B
Specification: A High-Speed ADC Perspective, Part 1.” EDN,
9/24/2014.
Harris, Jonathan. “Understanding Layers in the JESD204B
Specification: A High-Speed ADC Perspective, Part 2.” EDN,
10/2/2014.
Jones, Del. “JESD204B Subclasses (Part 1): Intro and
Deterministic Latency.” EDN, 6/18/2014.
Jones, Del. “JESD204B Subclasses (Part 2): Subclass 1 vs. 2,
System Considerations.” EDN, 6/25/2014.
References
JESD204B Survival Guide
JESD204 Serial Interface JEDEC Standard for Data Converters
Haijiao Fan
Haijiao Fan [haijiao.fan@analog.com] is an applications engineer at
Analog Devices in Beijing, China, focusing on JESD204 protocol evaluation
and integrated RF transceivers application and support. He received his
B.S.E.E. in 2003 and M.S.E.E. in 2006 from Northwestern Polytechnical
University, China. Prior to joining ADI in July 2012, Haijiao worked as an
FPGA and system engineer for over six years.
24
Analog Dialogue Volume 49 Number 1
Power Management for Integrated RF ICs
By Qui Luu
As more building blocks are added to a radio-frequency
integrated circuit (RFIC), more sources of noise coupling
arise, making power management increasingly important.
This article describes how power-supply noise can affect
the performance of RFICs. The ADRF6820 quadrature
demodulator with integrated phase-locked loop (PLL) and
voltage-controlled oscillator (VCO) is used as an example,
but the results are broadly applicable to other highperformance RFICs.
level of degradation is determined by the architecture and
layout of the chip. Understanding these power-supply sensitivities allows a more robust power design that optimizes
performance and efficiency.
Quadrature Demodulator Sensitivities
The ADRF6820 uses a double-balanced Gilbert cell active
mixer core, as shown in Figure 2. Double-balanced means
that both the LO and RF ports are driven differentially.
The power-supply noise can degrade linearity by creating
mixing products in the demodulator and degrade phase
noise in the PLL/VCO. A detailed power evaluation is
accompanied by recommended power designs using lowdropout regulators (LDOs) and switching regulators.
With its dual supply and high level of RF integration, the
ADRF6820 provides an ideal vehicle for discussion. It uses
a similar active mixer core as the ADL5380 quadrature
demodulator and the identical PLL/VCO cores as the
ADRF6720, so the information presented can be applied
to those components. In addition, the power-supply design
can be applied to new designs requiring 3.3-V or 5.0-V
supplies with similar power consumption.
CS
SCLK
SDIO
The ADRF6820 quadrature demodulator and synthesizer,
shown in Figure 1, is ideally suited for next-generation
communication systems. The feature-rich device comprises
a high-linearity broadband I/Q demodulator, an integrated
fractional-N PLL, and a low-phase-noise multicore VCO. It
also integrates a 2:1 RF switch, a tunable RF balun, a programmable RF attenuator, and two LDOs. The highly integrated
RFIC is available in a 6-mm × 6-mm LFCSP package.
15
14
13
2
3
8
9
23 25 26 28 38
DC/PHASE
CORRECTION
SERIAL PORT
INTERFACE
4
I+
5
I–
POLYPHASE
FILTER
RFIN0 29
35 LOIN+
34 LOIN–
RFIN1 22
QUAD
DIVIDER
LDO
2.5V
1
19
LDO
VCO
30 36
VPOS_3P3
31
PL L
6 Q–
DC/PHASE
CORRECTION
27
33
40
11
10
DECL1 TO
DECL4
39 REFIN
7
Q+
21
VPOS_5V
Figure 1. ADRF6820 simplified block diagram.
VDD
IF+
IF−
Q1 Q2
Q3 Q4
RF
Figure 2. Gilbert cell double-balanced active mixer.
After a filter rejects the high-order harmonics, the resulting
mixer outputs are the sum and difference of the RF and LO
inputs. The difference term, also called the IF frequency, lies
within the band of interest, and is the desired signal. The sum
term falls out of band and gets filtered.
2V
V(t) = πRF [cos(wRFt – wLOt) + cos(wRFt + wLOt)]
Ideally, only the desired RF and LO signals are presented to
the mixer core, but this is rarely the case. Power-supply noise
can couple into the mixer inputs and manifest itself as mixing
spurs. Depending on the source of the noise coupling, the
relative amplitudes of the mixing spurs may vary. Figure 3
shows a sample mixer output spectrum and where the mixing
products may reside due to power-supply-noise coupling.
In the figure, CW corresponds to a continuous wave or
sinusoidal signal that couples onto the power-supply rail.
The noise may be the clock noise from a 600-kHz or 1.2-MHz
switching regulator, for example. The power-supply noise
can cause two different problems—if the noise couples to the
mixer outputs, the CW tone will appear at the output with
no frequency translation; if the coupling occurs at the mixer
inputs, the CW tone will modulate the RF and LO signals,
producing products at IF ± CW.
The blocks most affected by power-supply noise are the
mixer core and the synthesizer. Noise coupled into the mixer
core creates unwanted products that degrade linearity and
dynamic range. This is especially critical for a quadrature
demodulator because the low-frequency mixing products
fall within the band of interest. Similarly, power-supply noise
can degrade the phase noise of the PLL/VCO. The effect of
unwanted mixing products and degraded phase noise are
common to most mixers and synthesizers, but the exact
Analog Dialogue Volume 49 Number 1
PSRR (dB)
Power-Supply Sensitivities
CW
IF − CW
IF
IF + CW
FREQUENCY
Figure 3. Sample mixer output spectrum with power-supply
noise coupling.
25
These mixing products can be close to the desired IF signal, so
filtering them out becomes difficult, and dynamic range loss is
inevitable. This is especially true for quadrature demodulators
because their baseband is complex and centered around dc.
The demodulation bandwidth of the ADRF6820 spans from
dc to 600 MHz. If a switching regulator with noise at 1.2 MHz
powers the mixer core, undesired mixing products will occur
at IF ± 1.2 MHz.
Frequency Synthesizer Sensitivities
The references provided at the end of the article offer
valuable information on how power-supply noise affects
integrated PLLs and VCOs. The principles apply to other
designs with the same architecture, but nonidentical
designs will need their own power evaluation. For
example, the integrated LDO on the ADRF6820’s VCO
power supply offers more noise immunity than a PLL
power supply that does not use an integrated LDO.
ADRF6820 Power-Supply Domains and Current
Consumption
To design the power-management solution, first examine
the RFIC’s power domains to determine which RF blocks
are powered by which domain, the power consumption of
each domain, the operational modes that affect the power
consumption, and the power-supply rejection of each
domain. Using this information, sensitivity data for the
RFIC can be collected.
The major functional blocks of the ADRF6820 each have their
own power pins. Two domains are powered from the 5-V
supply. VPMX powers the mixer core, and VPRF powers the
RF front-end and input switches. The remaining domains
are powered from the 3.3-V supply. VPOS_DIG powers
an integrated LDO, which outputs 2.5 V to power the SPI
interface, the PLL’s Σ-Δ modulator, and the synthesizer’s
FRAC/INT dividers. VPOS_PLL powers the PLL circuitry,
including the reference input frequency (REFIN), phasefrequency detector (PFD), and the charge pump (CP).
VPOS_LO1 and VPOS_LO2 power the LO path, including
the baseband amplifier and dc bias reference. VPOS_VCO
powers another integrated LDO, which outputs 2.8 V to
power the multicore VCO. This LDO is important for
minimizing the sensitivity to power-supply noise.
The ADRF6820 is configurable in several operational modes.
It consumes less than 1.5 mW in normal operational mode
with a 2850-MHz LO. Decreasing the bias current reduces
both power consumption and performance. Increasing the
mixer bias current makes the mixer core more linear and
improves IIP3, but degrades the noise figure and increases
power consumption. If noise figure is of key importance, the
mixer bias current can be reduced, decreasing the noise within
the mixer core and reducing power consumption. Similarly,
the baseband amplifiers at the output have variable current
drive capabilities for low impedance output loads. Low output
impedance loads require higher current drive and consume
more power. The data sheet provides tables showing power
consumption for each of the operational modes.
Measurement Procedure and Results
Noise coupling on the power rail produces undesired tones
at CW and IF ± CW. To mimic this noise coupling, apply a
CW tone to each power pin and measure the amplitude of
the resulting mixing product relative to the input CW tone.
Record this measurement as the power-supply rejection in
dB. The power-supply rejection varies with frequency, so
sweep the CW frequency from 30 kHz to 1 GHz to capture
the behavior. The power-supply rejection over the band of
interest determines whether filtering is required. The PSRR
is calculated as:
CW PSRR in dB = input CW amplitude (dBm) – measured
CW feedthrough at I/Q output (dBm)
(IF ± CW) PSRR in dB = input CW amplitude (dBm) –
measured IF ± CW feedthrough at I/Q output (dBm)
(IF + CW) in dBm = (IF – CW) dBm, as CW tones modulated
around the carrier have equal amplitudes.
Lab Setup
Figure 4 shows the lab setup. Apply a 3.3-V or 5-V dc source
to the network analyzer to produce a swept continuous sinusoidal signal with a 3.3-V or 5-V offset. Apply this signal to
each of the power rails on the RFIC. Two signal generators
provide the RF and LO input signals. Measure the output on
a spectrum analyzer.
3.3V OR 5V BIAS APPLIED
TO 8753D NETWORK ANALYZER
3.3V OR 5V BIAS
WITH 0dBm CW TONE
I/Q OUTPUT MEASURED
ON SPECTRUM ANALYZER
3.3V OR 5V
RF INPUT
EXTERNAL LO INPUT OR
PLL REFERENCE INPUT
Figure 4. ADRF6820 PSRR measurement setup.
26
Analog Dialogue Volume 49 Number 1
Measurement Procedure
PARALLEL RESONANCE OF 100pF
AND 2nH = 356MHz
–60
AMPLITUDE (CW + IF) (dB)
NO CAPS
2ND HARMONIC
RESONANCE OF 100pF
CAP = 16MHz
RP
L
RS
–100
–110
–120
100pF
RESONANCE OF 0.1𝛍F
CAP = 16MHz
RP
L
RS
0.1𝛍F
–130
0.01
0.1
1
10
CW FREQUENCY (MHz)
100
1k
Figure 5. Effects of decoupling capacitor resonance on IF ± CW.
Results
The amplitudes of the interfering signal (CW) on the powersupply rail and the modulated signals (IF ± CW) were
measured at the baseband outputs. Noise was introduced
to the power rail under test, while the other power supplies
remained clean. Figure 6 shows the amplitude of the (IF ± CW)
tone when a 0-dB sinusoidal signal was injected on the power
pin and swept from 30 kHz to 1 GHz. Figure 7 shows the
feedthrough from the CW tone to the baseband outputs.
20
VPRF
0
VPMX
VPOS_LO1
PSRR (IF ± CW) (dB)
−20
VPOS_LO2
VPOS_PLL
–60
VPOS_LO1
–40
VPOS_LO2
VPOS_VCO
–60
VPOS_PLL
VPOS_DIG
–80
–100
–120
–140
0.01
0.1
1
10
CW FREQUENCY (MHz)
100
1k
Figure 7. PSRR of the CW tone.
Under the same reasoning, it can be argued that the VCO
power-supply is also a critical node. The plots show that
VPOS_VCO has much better rejection than VPOS_PLL. This is
a result of the internal LDO that actually powers the VCO. The
LDO isolates the VCO from noise on the external pin and also
provides it with a fixed-noise spectral density. The PLL power
supply has no LDO, making it the most sensitive power rail.
Thus, isolating it from potential noise coupling is critical for
optimal performance.
The PLL loop filter attenuates high CW frequencies, so the
sensitivity on VPOS_PLL is poor at low frequencies and
slowly improves as the frequency sweeps from 30 kHz to
1 GHz. At higher frequencies the amplitude of the interfering
tone gets attenuated and the power level injected into the
PLL is substantially lower. Thus, VPOS_PLL shows better
high-frequency power-supply rejection than the other power
domains. The loop filter components were configured for
20 kHz, as shown in Figure 8.
The power rails, listed from most sensitive to least sensitive,
are: VPOS_PLL, VPOS_LO2, VPOS_VCO, VPOS_LO1, VPOS_
DIG, VPMX, and VPRF.
VPOS_VCO
–40
VPMX
The plots provide invaluable data on the supply sensitivities
at each power pin. VPOS_PLL has the worst power-supply
rejection and is therefore the most sensitive power node. This
power pin powers the PLL circuitry, including the reference
input frequency, phase-frequency detector, and the charge
pump. These sensitive function blocks determine the accuracy
and phase performance of the LO signal, so any noise coupled
on them propagates directly to the output.
–80
–90
VPRF
−20
Analysis
0.1𝛍F AND 100pF
–70
0
PSRR (CW) (dB)
The amplitude of the undesired mixing products depends on
the chip’s power-supply rejection, and the size and location of
the decoupling capacitors on the evaluation board. Figure 5
shows the amplitude of the (IF + CW) tone at the output given
a 0-dB sinusoidal signal on the power pin. With no decoupling
capacitors, the amplitude of the undesired tone was between
–70 dBc and –80 dBc. The data sheet recommends a 100-pF
capacitor adjacent to the device on top of the board and a
0.1-µF capacitor on the back. The resonance of these external
decoupling capacitors can be seen in the graph. The transition
at 16 MHz is due to the resonance of the 0.1 µF capacitor with
a 1-nH parasitic inductance. The transition at 356 MHz is due
to the resonance of the 100-pF capacitor with 2 nH of parasitic
inductance from both capacitors. The transition at 500 MHz
is due to the resonance of the 100-pF capacitor with a 1-nH
parasitic inductance.
VPOS_DIG
–80
22𝛀
3.3k𝛀
–100
82pF
–120
–140
0.01
1.1k𝛀
680pF
330pF
22nF
0.1
1
10
CW FREQUENCY (MHz)
Figure 6. PSRR of the (IF ± CW) tone.
Analog Dialogue Volume 49 Number 1
100
1k
Figure 8. PLL loop filter configured for a 20-kHz loop bandwidth.
27
attenuate the switching noise. The ADP2370 can deliver up
to 800 mA load current. The ADRF6820’s 5-V rail can be
sourced by either the ADP7104 or the ADP2370. Additional
decoupling and filtering is applied to each power pin.
Power-Supply Design
With a good understanding of the maximum power
consumption of the ADRF6820 in its various modes and
the sensitivity of each power domain, power-management
solutions were designed using both switching regulators and
LDOs to determine the feasibility of both power solutions.
First, a 6-V source was regulated to 5 V and 3.3 V for the
ADRF6820 power rails. Figure 9 shows the power design for
the 5-V power-supply for VPMX and VPRF. The ADP7104
CMOS LDO can deliver up to 500 mA load current. The
ADP2370 low quiescent current step-down (buck) switching
regulator can operate at 1.2 MHz or 600 kHz. Additional
filtering was added to the switching regulator output to
U7
+6V
1
1
+6V
RED
ADP7104
VIN
VOUT
7
PG
SENSE
2
6
GND
GND
3
5
EN
NC
4
2
C74
1𝛍F
JP4
E7
2
VPRF_+5V
120𝛀
3
L1
2
C82
1𝛍F
1
1.2𝛀
1
VPMX_+5V
120𝛀
PAD
R66
P5
E6
1
8
C29
10𝛍F
+6V_TP
Figure 10 shows the 3.3-V power design. The source voltage
is still 6.0 V, but an additional LDO steps the source down to
an intermediate voltage before it further gets regulated down
to 3.3 V. The extra stage is required to reduce power loss, as
a 6-V source regulated directly down to 3.3-V would operate
at 55% maximum efficiency. An intermediate stage is not
necessary for the switching regulator path because its pulsewidth modulation (PWM) architecture minimizes power loss.
C83
1𝛍F
C89
0.1𝛍F
R60
1𝛍H
C75
10𝛍F
C76
10𝛍F
C90
10𝛍F
10k𝛀
U9
EPAD
PAD
PGND
8
FSEL
SW
7
3
EN
PG
6
4
SYNC
FB
5
1
VIN
2
L3
L11
10𝛍H
10𝛍H
C92
22𝛍F
C94
22𝛍F
C96
22𝛍F
C100
0.1𝛍F
C103
22𝛍F
ADP2370
R58
4.02k𝛀
Figure 9. 5-V power design.
ADP7104
+6V
1
1
RED
C29
10𝛍F
2
ADP121
5V, 500mA, LOW NOISE
CMOS LDO
+6V_TP
P5
1
8
VIN
VOUT
1
7
PG
SENSE
2
6
GND
GND
3
5
EN
NC
4
3.3V LOW NOISE
CMOS LDO
C74
1𝛍F
C78
1𝛍F
1
3
IN
EN
1
C98
1𝛍F
NC4
GND
4
PAD
U7
OUT
2
2
1
U8
JP3
3
ADP151
3.3V LOW NOISE
CMOS LDO, 9𝛍V rms
OUTPUT NOISE
C30
1𝛍F
6
4
VIN
EN
VOUT
5
3
1
C65
1𝛍F
PAD
1
ADP7104
C33
1𝛍F
R73
8
VIN
VOUT
1
7
PG
SENSE
2
6
GND
GND
3
5
EN
NC
4
L2
R61
1𝛍H
C32
10𝛍F
C91
10𝛍F
C77
1𝛍F
R22
10k𝛀
PLL_3P3V
R59
0𝛀
C105
100𝛍F
C66
1𝛍F
E4
C80
1𝛍F
LO_3P3V
120𝛀
1
JP6
VCC_+3P3V
2
3
10k𝛀
U10
120𝛀
C104
10𝛍F
3
PAD
1.2𝛀
E1
2
JP5
3.3V, 500mA, LOW NOISE
CMOS LDO, 15𝛍V rms
OUTPUT NOISE
U6
C106
1𝛍F
DIG_3P3V
120𝛀
U4
NC GND
2
E2
2
E5
EPAD
PAD
1
VIN
PGND
8
2
FSEL
SW
7
3
EN
PG
6
4
SYNC
FB
5
L4
L12
6.8𝛍H
6.8𝛍H
C93
22𝛍F
C84
22𝛍F
C95
22𝛍F
C97
22𝛍F
C99
0.1𝛍F
ADP2370
3.3V, 1.2MHz/600kHz,
800mA, LOW QUIESCENT
CURRENT BUCK REGULATOR
C81
1𝛍F
E3
C102
22𝛍F
C79
1𝛍F
LO2_3P3V
120𝛀
120𝛀
VCO_3P3V
C85
0.1𝛍F
R53
4.02k𝛀
Figure 10. 3.3-V power design.
28
Analog Dialogue Volume 49 Number 1
The 3.3-V design allowed for more experimentation. In
addition to sourcing the 3.3-V rail with either an LDO or a
switching regulator, the VPOS_PLL rail has additional LDO
options and the VPOS_DIG rail has an optional isolated LDO.
As the PLL power supply is the most sensitive, three power
solutions were tried, each with different output noise: the
ADP151 3.3-V ultralow-noise CMOS LDO with 9 µV rms
output noise; the ADP7104 3.3-V low-noise CMOS LDO
with 15 µV rms output noise; and the ADP2370 3.3-V buck
regulator. We want to determine the highest level of powersupply noise that will still maintain the required phase-noise
performance. Is the highest performance, lowest noise LDO
an absolute necessity?
The ADP121 3.3-V low-noise CMOS LDO was also tried on
the VPOS_DIG power rail to determine if digital noise would
affect performance. The digital power rail tends to be noisier
than the analog supplies due to switching on the SPI interface.
We want to determine if the digital 3.3-V power supply will
require its own LDO or if it can be coupled directly to the
analog power-supply. The ADP121 was chosen as a low-cost
solution.
Conclusions and Power Design Recommendations
For VPOS_PLL, the most sensitive power-supply rail, the
low-cost ADP151 LDO achieves the same phase noise as the
ADP7104 high-performance, low-noise LDO, as shown in
Figure 11. Performance was degraded when the ADP2370
switching regulator was used, however, as shown in Figure 12.
The noise hump is caused by the switching regulator, and can
be seen on its output, as shown in Figure 13. Thus, VPOS_PLL
can tolerate up to 15 µV rms noise with no degradation in
integrated phase noise, but a switching regulator cannot be
used to power this pin. No benefit is obtained by using a
higher performance, lower noise LDO.
Good phase-noise performance is maintained when either a
switching regulator or an LDO powers the remaining supply
rails, as shown in Figure 14. The 5-V power-supply pins,
VMPX and VPRF, can both be tied together and sourced with
a single supply. The 3.3-V power-supply pins, VPOS_LO1,
VPOS_LO2, and VPOS_VCO, can also be tied together and
sourced by a single supply. VPOS_DIG does not require an
independent LDO and can be tied to the analog 3.3-V power
supply.
REF −56dBm
−40
–60
–70
ADP151
−60
ADP7104
–80
ADP7104
–80
ADP151
–100
–120
AMPLITUDE (dBm)
PHASE NOISE (dBc/Hz)
RBW 100Hz
VBW 300Hz
SWT 12s
ATT 0dB
–140
–90
–100
–110
–120
–130
–140
–160
–180
100
–150
1k
10k
100k
FREQUENCY (Hz)
1M
0
START
10M
Figure 11. Integrated phase noise using the ADP151 and ADP7104.
Figure 13. Output spectrum of the ADP2370.
−40
27
25
–80
PLL_3P3 = SWITCHER
NOISE FIGURE (dB)
PHASE NOISE (dB/Hz)
−60
1/F AND REFERENCE
NOISE FROM SWITCHER
–100
–120
PLL_3P3 = ADP151
–140
23
INTERNAL 2× LO
CASE0
CASE4
CASE1
CASE5
CASE2
CASE6
CASE3
CASE7
21
19
17
–160
–180
100
100k
STOP
10k
FREQUENCY (Hz)
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 12. Integrated phase noise using the ADP151 and ADP2370.
Analog Dialogue Volume 49 Number 1
15
800
EXTERNAL LO,
POLYPHASE
1000 1200 1400 1600 1800 2000 2200 2400 2600 2800
LO FREQUENCY (MHz)
Figure 14. Switcher vs. LDO noise figure.
29
With a 6-V source voltage, the recommended power-supply
design, shown in Figure 15, includes the ADP7104 5.0-V and
the ADP7104 3.3-V LDOs. This solution uses only LDOs
because the source voltage is close to the required supply
voltages. The power efficiency is acceptable, so the added
cost of filtering components and switching regulators is
unnecessary.
References
Circuit Note CN0147. Powering a Fractional-N Voltage-Controlled
Oscillator (VCO) with Low Noise LDO Regulators for Reduced
Phase Noise. Analog Devices, Inc., 2010.
Collins, Ian. Integrated PLLs and VCOs [Part 2]. RadioElectronics.com, Nov 2010.
With a 12-V source, the recommended power-supply design,
shown in Figure 16, includes two switching regulators and
an LDO. The source voltage is much larger than the required
supply voltages, so the switching regulators are used to
improve power efficiency. All of the power pins except for
the sensitive VPOS_PLL supply can be sourced from the
switching regulators. Either the ADP7104 or ADP151 can be
used for VPOS_PLL.
+6V
1
C29
10𝛍F
2
Linear Regulators
Switching Regulators
ADP7104
ADP7104
+6V_TP
RED
1
Modulators/Demodulators
8
VIN
VOUT
1
7
PG
SENSE
2
6
GND
GND
3
NC
4
5
P5
EN
U7
1
C33
1𝛍F
C74
1𝛍F
8
VIN
VOUT
1
7
PG
SENSE
2
6
GND
GND
3
NC
4
EN
5
PAD
VCC_ +3P3V
RED
E1
PAD
U6
PLL_3P3V
120𝛀
C104
10𝛍F
C66
1𝛍F
R59
0𝛀
C105
10𝛍F
E2
2
DIG_3P3V
120𝛀
C106
1𝛍F
VCC_+5V
RED
E4
E6
VPMX_+5V
120𝛀
C81
1𝛍F
C80
1𝛍F
E7
C83
1𝛍F
E5
VPRF_+5V
120𝛀
LO_3P3V
120𝛀
C81
1𝛍F
C89
0.1𝛍F
LO2_3P3V
120𝛀
E1
C79
1𝛍F
VCO_3P3V
120𝛀
C85
0.1𝛍F
Figure 15. Recommended power-supply design for a 6-V source voltage.
R66
+12V
1
2
1.2𝛀
L1
C75 1𝛍H
10𝛍F
R60
C90
10𝛍F
10k𝛀
C76
1𝛍F
P5
1
2
EPAD
PAD
1
VIN
PGND
8
2
FSEL
SW
7
3
EN
PG
6
4
SYNC
FB
5
U9
C92
22𝛍F
C94
22𝛍F
C96
22𝛍F
ADP2370
R66
G
1
1.2𝛀
L1
C32 1𝛍H
10𝛍F
10𝛍H
10𝛍H
C100
0.1𝛍F
VCC_VPMX
RED
VPMX_+5V
E6
C82
1𝛍F
C103
22𝛍F
120𝛀
E7
R58
4.02k
2 S
3
VCC_ +5V
RED
L11
L3
VPRF_+5V
120𝛀
C89
0.1𝛍F
C83
1𝛍F
D
R61
C91
10𝛍F
10k𝛀
C77
1𝛍F
R22
10k𝛀
U10
EPAD
PAD
PGND
8
SW
7
EN
PG
6
SYNC
FB
5
1
VIN
2
FSEL
3
4
ADP2370
ADP151
VCC_+3P3V
L12
L4
6.8𝛍H
C93
22𝛍F
C84
22𝛍F
C95
22𝛍F
C97
22𝛍F
6.8𝛍H
C99
0.1𝛍F
U4
RED
C102
22𝛍F
C30
1𝛍F
6
4
VIN
EN
E2
C106
1𝛍F
PAD
PLL_3P3V
R59
0𝛀
C105
100𝛍F
DIG_3P3V
LO_3P3V
LO2_3P3V
120𝛀
E1
C79
1𝛍F
3
120𝛀
C104
10𝛍F
120𝛀
E5
C81
1𝛍F
C65
1𝛍F
120𝛀
E4
C80
1𝛍F
5
E1
1
NC GND
2
R53
4.02k
VOUT
120𝛀
VCO_3P3V
C85
0.1𝛍F
Figure 16. Recommended power-supply design for a 12-V source voltage.
Qui Luu
Qui Luu [qui.luu@analog.com] is an RF applications engineer at Analog Devices
since June 2000. Qui received her B.S.E.E. from Worcester Polytechnic Institute in Worcester, MA, in 2000 and her M.S.E.E. at Northeastern University in
Boston, MA, in 2005.
Also by this Author:
RF-to-Bits Solution
Offers Precise Phase
and Magnitude Data
for Materal Analysis
Volume 48, Number 4
30
Analog Dialogue Volume 49 Number 1
Design Reliable Digital Interfaces for
Successive-Approximation ADCs
By Steven Xie
Introduction
Successive-approximation analog-to-digital converters, called
SAR ADCs due to their successive-approximation register, are
popular for applications requiring up to 18-bit resolution at up
to 5 MSPS. Their advantages include small size, low power, no
pipeline delay, and ease of use.
A host processor can access or control the ADC via a variety of
serial and parallel interfaces such as SPI, I2C, and LVDS. This
article discusses design techniques for reliable, integrated
digital interfaces, including the digital power-supply level and
sequence, I/O state during turn on, interface timing, signal
quality, and errors caused by digital activity.
Digital I/O Power-Supply Level and Sequence
Most SAR ADCs provide a separate digital I/O power-supply
input, VIO or VDRIVE , which determines the operating voltage
and logic compatibility of the interface. This pin should be at
the same voltage as the host interface (MCU, DSP, or FPGA)
supply. The digital inputs should generally be between
DGND − 0.3 V and VIO + 0.3 V to avoid violating the absolute
maximum ratings. Decoupling capacitors with short traces
should be connected between the VIO pin and DGND.
ADCs that operate with multiple supplies may have welldefined power-up sequences. Application Note AN-932, Power
Supply Sequencing, provides a good reference for designing
supplies for these ADCs. To avoid forward biasing the ESD
diodes and powering up the digital core in an unknown state,
turn on the I/O supply before the interface circuitry. The
analog supplies are usually powered before the I/O supply,
but this is not the case for all ADCs. Read and follow the data
sheet to ensure the proper sequence.
AVCC/DVCC
VDRIVE
CNVST
CH1: 2.00V
CH2: 2.00V
CH3: 2.00V
Figure 1. Bringing CNVST high during power-supply ramp up could
result in an unknown state.
Digital Interface Timing
After a conversion has finished, the host can read the data via
a serial or parallel interface. To read the data correctly, follow
a specific timing strategy, such as which mode to use for the
SPI bus. Do not violate the digital interface timing specifications,
especially the setup and hold times of the ADC and the host.
The maximum bit rate is determined by the whole cycle, not just
the minimum specified clock period. Figure 2 and the following
equations show an example of how to calculate the setup and
hold timing margin. The host sends the clock to the ADC and
reads the data output from the ADC.
tCYCLE
CLOCK @ HOST
Digital I/O State During Turn On
For proper initialization, some SAR ADCs require certain logic
states or sequences for digital functions such as reset, standby,
or power-down. After all power supplies are stable, the specified
pulse or combination is applied to guarantee that the ADC starts
in the intended state. For example, a high pulse on RESET, with
a duration of at least 50 ns, is required to configure the AD7606
for normal operation after power up.
No digital pin should toggle until all the power supplies have
been fully established. For SAR ADCs, the convert start pin,
CNVST, may be sensitive to noise. Figure 1 shows an example
in which the host cPLD brings CNVST high while AVCC , DVCC
and VDRIVE are still ramping. This might put the AD7367 into an
unknown state, so the host should keep CNVST low until the
supplies are all fully established.
Analog Dialogue Volume 49 Number 1
tJITTER
tPROP_CLK
tSETUP
CLOCK @ ADC
tDRV
DATA @ ADC
tPROP_DATA
DATA @ HOST
tMARGIN
Figure 2. Setup and hold timing margin.
31
tCYCLE = tJITTER + tSETUP + tPROP_DATA + tPROP_CLK + tDRV + tMARGIN
tPROP = 180 ps/in × (9 in + 3 in) + 5 ns = 7 ns.
tCYCLE : Clock period = 1/fCLOCK
tJITTER = 1 ns. The host runs SCLK at 30 MHz, so tCYCLE = 33 ns.
tJITTER : Clock jitter
tSETUP_MARGIN = 33 ns − 1 ns – 5 ns – 7 ns – 11 ns – 7 ns = 2 ns
tSETUP : Host setup time
tHOLD_MARGIN = 11 ns + 7 ns + 7 ns – 1 ns – 2 ns = 22 ns
tHOLD : Host hold time
tPROP_DATA : Data propagation delay along the transmit line from
ADC to host
The setup and hold margins are both positive, so the SPI SCLK
can run at 30 MHz.
tPROP_CLK : Clock propagation delay along the transmit line from
host to ADC
tEN = 10ns
tDSDO = 11ns
tDRV : Data output valid time after clock rising/falling edge
tJITTER = 1ns
DSP
SDO
tMARGIN_SETUP = tCYCLE, MIN – tJITTER – tSETUP – tPROP_DATA – tPROP_CLK – tDRV, MAX
The setup time equation defines the minimum clock period
time or maximum frequency in terms of the maximum system
delay terms. It must be ≥ 0 to meet the timing specifications.
Increase the period (reduce the clock frequency) to handle
excessive system delays. For buffers, level shifters, isolators,
or other additional components on the bus, add the extra
delay into tPROP_CLK and tPROP_DATA .
Similarly, the hold margin for the host is
tMARGIN_HOLD = tPROP_DATA + tPROP_CLK + tDRV – tJITTER – tHOLD
Figure 4. Digital interface between DSP and AD7980.
Digital Signal Quality
Digital signal integrity, which includes both timing and signal
quality, ensures that signals: are received at specified voltage
levels; do not interfere with one another; do not damage other
devices; and do not pollute the electromagnetic spectrum.
Signal quality is specified by many terms, as shown in Figure 5.
This section will introduce overshoot, ringing, reflection, and
crosstalk.
OVERSHOOT
The hold time equation defines the minimum system delay
requirements to avoid logic errors due to hold violations. It
has to be ≥ 0 to meet the timing specifications.
Many of ADI’s SAR ADCs with an SPI interface clock the MSB
from the falling edge of CS or CNV, while the remaining data
bits follow the falling edge of SCLK, as shown in Figure 3.
When reading the MSB data, use tEN in the equations instead
of t DRV .
RINGING
DROOP
100% AMPLITUDE
90% AMPLITUDE
50% AMPLITUDE
DROOP
PULSE WIDTH
10% AMPLITUDE
PREPULSE
DISTORTION
–10% AMPLITUDE
FALL TIME
(DECAY TIME)
BACKSWING
RISE TIME
(ATTACK TIME)
POSITIVE PULSE WAVEFORM
SDI = 1
tCYC
Figure 5. Common specifications of signal quality.
tCNVH
Reflection is a result of impedance mismatch. As a signal
travels along a trace, the instantaneous impedance changes
at each interface. Part of the signal will reflect back, and part
will continue down the line. Reflection can produce overshoot,
undershoot, ringing, and nonmonotonic clock edges at the
receiver.
CNV
tCONV
tACQ
ACQUISITION CONVERSION
ACQUISITION
tSCK
tSCKL
SCK
1
tEN
2
tHSDO
D15
D14
3
14
15
16
D1
D0
tSCKH
tDSDO
D13
tDIS
Figure 3. SPI timing of AD7980 3-wire CS mode.
Thus, in addition to the maximum clock rate, the maximum
operating speed of the digital interface also depends on the
setup time, hold time, data output valid time, propagation
delay, and clock jitter.
Figure 4 shows a DSP host accessing the AD7980 in 3-wire CS
mode, with VIO = 3.3 V. The DSP latches the SDO signal on the
falling edge of SCLK. The DSP specifies 5 ns minimum setup
time and 2 ns minimum hold time. For a typical FR-4 PC board,
the propagation delay is about 180 ps/in. The propagation delay
of the buffer is 5 ns. The total propagation delay for CNV, SCLK
and SDO is
32
L = 9 INCHES
AD7980 SCLK
The setup margin for the host is
SDO
L = 3 INCHES
CNV
tMARGIN : Margin time, ≥ 0 means the setup time or hold time is
met; < 0 means the setup time or hold time is not met.
tSETUP = 5ns
tHOLD = 2ns
tPD = 5ns
Overshoot and undershoot can damage the input protection
circuitry or shorten the IC’s life span. Figure 6 shows the
absolute maximum ratings of the AD7606. The digital input
voltage should be between –0.3 V and VDRIVE + 0.3 V. In
addition, ringing above VIL maximum or below VIH minimum
may cause logic errors.
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, UNLESS OTHERWISE NOTED.
PARAMETER
RATING
AVCC TO AGND
–0.3 V TO +7 V
VDRIVE TO AGND
–0.3 V TO AVCC + 0.3 V
ANALOG INPUT VOLTAGE TO AGND
±16.5 V
DIGITAL INPUT VOLTAGE TO DGND
–0.3 V TO VDRIVE + 0.3 V
DIGITAL OUTPUT VOLTAGE TO GND
–0.3 V TO VDRIVE + 0.3 V
REFIN TO AGND
–0.3 V TO AVCC + 0.3 V
INPUT CURRENT TO ANY PIN EXCEPT SUPPLIES
±10 mA
Figure 6. Absolute maximum ratings of AD7606.
Analog Dialogue Volume 49 Number 1
To minimize reflection:
• Eliminate stubs
Crosstalk is the coupling of energy between parallel
transmission lines via mutual capacitance (electric field) or
mutual inductance (magnetic field). The amount of crosstalk
depends on the signal’s rise time, the length of the parallel
lines, and the spacing between them.
• Use an appropriate termination scheme
Some common practices to control the crosstalk are:
• Use solid metal with a small loop area as the return current
reference plane
• Increase the line spacing
• Make the trace as short as possible
• Control the characteristic impedance of the trace
• Use lower drive currents and slew rates
• Keep the traces close to the reference metal planes
Many software tools or webs are available for calculating
the characteristic impedance of a trace, such as the Polar
Instruments Si9000 PCB transmission line field solver. These
make it easy to get the characteristic impedance by selecting
a transmission line model and setting parameters such as
dielectric type and thickness, and trace width, thickness, and
separation.
IBIS is an emerging standard used to describe the analog
behavior of an IC’s digital I/O. ADI provides IBIS models for
SAR ADCs. Prelayout simulation checks clock distribution,
chip package type, board stack-up, net topology, and
termination strategies. It can also check the serial interface
timing constraints to guide placement and layout. Postsimulation verifies that the design meets all guidelines and
constraints, and checks for violations such as reflection,
ringing, and crosstalk.
Figure 7 shows one driver connected to SCLK1 through a
12" microstrip line, and a second driver connected to SCLK2
through a 43-Ω resistor in series with the microstrip.
DRIVER 1
• Minimize parallel runs
MICROSTRIP 50𝛀, 12"
SCLK1 AD7606
• Use an appropriate termination scheme
• Reduce the signal’s slew rate
Performance Degradation Caused by Digital Activity
Digital activity can degrade the SAR ADC’s performance, with
the SNR decreasing due to a noisy digital ground or power
supply, sampling clock jitter, and digital signal interference.
Aperture or sampling clock jitter sets the limit for SNR,
especially for high-frequency input signals. System jitter
comes from two sources: aperture jitter from the on-chip
track-and-hold circuitry (internal jitter) and jitter on
the sampling clock (external jitter). Aperture jitter is the
conversion-to-conversion variation in the sampling time,
and is a function of the ADC. The sampling clock jitter is
usually the dominant source of error, but both sources cause
varying analog input sampling times, as shown in Figure 9.
Their effects are indistinguishable.
The total jitter produces an error voltage, with overall SNR of
the ADC limited by
1
SNR = 20 log10 2 π f tJ
Total jitter = tJ (rms),
DRIVER 2
MICROSTRIP 50𝛀, 12"
43𝛀
Total jitter = √ (ADC aperture jitter)2 + (sampling clock jitter)2
SCLK2 AD7606
where, f is the analog input frequency and tJ is the total
clock jitter.
Figure 7. Drive AD7606 SCLK.
Figure 8 shows a large overshoot on SCLK1 that violates the
–0.3 V to +3.6 V absolute maximum rating. The series resistor
reduces the slew rate on SCLK2, keeping the signal within the
specifications.
For example, with a 10 kHz analog input and 1 ns total jitter,
the SNR is limited to 84 dB.
OVERSHOOT CAUSED BY REFLECTION
6
INPUT
SIGNAL
dv
dt
5
dv
VOLTAGE (V)
4
+3.600V
3
ERROR VOLTAGE
2
1
SWITCH
DRIVER
ENCODE
0
–300.000mV
–1
CHOLD
INPUT
SAMPLING
CLOCK
0
100
200
300
TIME (ns)
AD7606 SCLK1
AD7606 SCLK2
Figure 8. AD7606 IBIS model simulation of overshoot.
Analog Dialogue Volume 49 Number 1
400
dt
SAMPLING CLOCK
Figure 9. Error voltage caused by sampling clock jitter.
Power-supply noise caused by digital outputs switching
should be isolated from the sensitive analog supplies.
33
Separately decouple the analog and digital power supplies,
paying careful attention to ground return current paths.
High-precision SAR ADCs can be sensitive to activity on the
digital interface, even when the power supply is properly
decoupled and isolated. Burst clocks often perform better than
continuous clocks. The data sheet usually shows quiet time
when the interface should not be active. Minimizing digital
activity during these times—typically the sampling instant
and when critical bit decisions occur—can be challenging at
higher throughput rates.
Conclusion
Pay careful attention to digital activity to ensure valid
conversions from SAR ADCs. Digitally induced errors may
take SAR ADCs into an unknown state, cause malfunctions,
or degrade performance. This article should help designers
investigate root causes and provide solutions.
References
Kester, Walt. “Data Converter Support Circuits.” Data
Conversion Handbook, Chapter 7. Analog Devices, Inc., 2004.
Brannon, Brad. AN-756 Application Note. Sampled Systems and
the Effects of Clock Phase Noise and Jitter. Analog Devices, Inc., 2004.
Ritchey, Lee W. Right the First Time: A Practical Handbook on
High-Speed PCB and System Design, Volume 1. Speeding Edge,
2003.
Usach, Miguel. AN-1248 Application Note. SPI Interface.
Analog Devices, Inc., 2013.
Casamayor, Mercedes. AN-715 Application Note. A First
Approach to IBIS Models: What They Are and How They Are
Generated. Analog Devices, Inc., 2004.
Steven Xie [steven.xie@analog.com] has worked as an ADC applications
engineer with the China Design Center in ADI Beijing since March 2011. He
provides technical support for SAR ADC products across China. Prior to
that, he worked as a hardware designer in the Ericsson CDMA team for four
years. In 2007, Steven graduated from Beihang University with a master’s
degree in communications and information systems.
34
Steven Xie
Also by this Author:
Successive-Approximation ADCs: Ensuring
a Valid First Conversion
Volume 47, Number 4
Analog Dialogue Volume 49 Number 1
Notes
Analog Dialogue Volume 49 Number 1
35
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