Reprint from: 8th Int. Mixed-Signal Testing Workshop, Montreux, Switzerland, June 18-21, 2002
A Nullator-Norator-based Analogue Circuit DC-Test Generation Approach
Bernd Straube, Wolfgang Vermeiren
Fraunhofer-Institut für Integrierte Schaltungen,
Branch Lab Design Automation EAS Dresden,
Zeunerstr. 38, 01069 Dresden, Germany
e-mail: < straube | vermeiren >@eas.iis.fhg.de
Abstract
1
Introduction
For analogue circuits the development of automatic test generation techniques is still a subject of
research [1, 2, 5, 6, 7, 9, 10, 12, 13, 14, 15, 16, 17, 18]. In this paper we propose a fault-oriented technique for generating DC-tests for nonlinear analogue circuits. At the time being the circuits to be considered have single inputs and single outputs. An extension to circuits with multiple inputs and outputs
is still under investigation.
The proposed technique is based on a test generation model that makes use of the »singular« network
elements nullator and norator [3, 4]. Nullators and norators are network elements with two terminals.
Both the current and the voltage of a nullator are equal to zero. For a norator, however, its current and
its voltage may have any value. When nullators and norators are used in a network to be simulated by
means of a usual electric simulator then these elements have to be used necessarily in pairs, i. e. as a
two-port (Figure 1). Such a nullator-norator two-port, also referred as to a nullor, can also be described
by an interconnection of controlled sources or, easier, by means of a VHDL-AMS model.
inul
inor
vnul
vnor
nullator
1
0 inul
0
0 inor
+
0
0 vnul
1
0 vnor
=
0
0
norator
Figure 1: Norator-nullator two-port (Nullor)
An analogue circuit is regarded as a two-port. W. l. o. g. we consider voltages as to be the quantities
for test input and test output. In Figure 2 an ideal voltage source is connected to the lhs port, i.e.,
v1 = vin. Since the output load can be considered as a part of the circuit the test output quantity is the
open circuit voltage at port 2, i.e., v2 = vout and i2 = 0.
i1
vin
v1
i2 = 0
network N
(two-port)
v2 = vout
Figure 2: Two-port model of the analogue circuit
The analogue circuit described as a two-port in Figure 2 is connected with a nullator and a norator in
the following way (cf. Figure 3): The voltage source of the input port is substituted by a norator. A
series connection of a nullator with an independent voltage source is connected to the output port.
If the simulated value for voltage v2 in Figure 2 is now taken as the value vout of the voltage source on
the rhs then the voltage over the norator will be v1 = vin.
By applying the substitution theorem of the network theory [19, 20] it can be shown, that each solution
Reprint from: 8th Int. Mixed-Signal Testing Workshop, Montreux, Switzerland, June 18-21, 2002
of an arbitrary, i.e. also nonlinear, network according to the structure of Figure 3 is also a solution of
the network according to the structure of Figure 2.
i1
norator
v1
i2 = 0
nullator
network N
(two-port)
v2
Vout
Figure 3: Interconnection of the circuit of Figure 2 with a norator and a nullator
2
The test generation model
Fault-oriented test signal generation or fault simulation is always based on a network model that consists of a suitable composition of the fault-free network and the faulty one. In our approach to the
fault-oriented test signal generation for nonlinear networks this model is made up of the interconnection of (cf. Figure 4)
• the fault-free network with a nullator in series with a voltage source for the output
voltage vout_good
• the faulty network with a nullator in series with a voltage source for the output
voltage vout_faulty
• a norator at the fault site
• a norator at the input ports of both the networks that are connected in parallel.
The value of output voltage vout_faulty has to be taken in such a way that it is outside the pass band. The
task »generating a test input« involves the numerical computation of the test input voltage vtest for
given vout_good and vout_faulty. In solving this network model the norator voltage vnor_fault and the norator current inor_fault at the fault site is also calculated.
nullator
fault-free
network
vout_good
nullator
vtest
norator
faulty
network
vout_faulty
fault
vnor_fault
inor_fault
vnor_fault – Rfault · inor_fault = 0
norator
at the fault site
Figure 4: Network model for test signal generation
Reprint from: 8th Int. Mixed-Signal Testing Workshop, Montreux, Switzerland, June 18-21, 2002
Since the voltage-current relation of a nullator-norator two-port can be described by an interconnection
of controlled sources or by a VHDL-AMS model a common electric simulator can be applied to calculate
the test input voltage vtest. It is the important advantage of our approach that no dedicated solver of
the proposed test generation model has to be developed and implemented. Therefore
• any electric simulator or VHDL-AMS-simulator can be used,
• all the problems, that arise in solving numerically the system of nonlinear equations, are tackled by
the simulator,
• not only short-faults and open-faults but any models for faults that can be described by an interconnection of network elements, by a functional model, or a description in VHDL-AMS, and parametric
faults can be handled.
3
Illustrating example
The approach is illustrated with the simple circuit depicted in Figure 5.
fault
R2
–
R1 = 1 kΩ
v
+
vin
R2 = 99 kΩ
vout
R1
Op-amp, modelled by a
voltage-controlled voltage source with
an amplification factor of v = 104
Figure 5: Voltage amplifier
A short-fault is across R2. Therefore, the fault-norator is connected in parallel to R2. Let the fault-free
output voltage be vout_good = 2.5 V. The graph of Rfault, calculated by the norator current inor_fault and
the norator voltage vnor_fault versus the output voltage vout_faulty , is shown in Figure 6. Let the ‘pass
band’ be 0.5V. Then, the test input voltage vtest = 25 mV is able to detect any conducting connection,
which is in parallel to the resistor R2, with a resistance up to about 390 kΩ.
700k
Rfault
600k
500k
400k
300k
fault
detected
200k
100k
pass band
0.5
1.0
1.5
2.0
2.5
3.0
vout_fault
Figure 6: Rfault = vnor_fault / inor_fault versus the output voltage vout_faulty
4
Results and future work
The approach has successfully been applied to other circuits such as the c.t.-filter benchmark, a comparator and a sample and hold circuit taken from [6, 11, 13], respectively.
The extension of our DC test generation technique to networks with more than one input and one output ports is under investigation. The generation of transient test signals will be the important task for
the next future.
Reprint from: 8th Int. Mixed-Signal Testing Workshop, Montreux, Switzerland, June 18-21, 2002
5
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