Part III
Lectures 15-18
Field-Effect Transistors
(FETs) and Circuits
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
Field-Effect Transistors (FETs)
Lecture Fifteen - Page 1 of 8
Dr. Ahmed Saadoon Ezzulddin
Field-Effect Transistors (FETs)
Basic Definitions:
The FET is a semiconductor device whose operation consists of controlling the flow of
current through a semiconductor channel by application of an electric field (voltage).
There are two categories of FETs: the junction field-effect transistor (JFET) and
the metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET
category is further broken-down into: depletion and enhancement types.
A Comparison between FET and BJT:
e FET is a unipolar device. It operates as a voltage-controlled device with either
electron current in an n-channel FET or hole current in a p-channel FET.
e BJT made as npn or as pnp is a current-controlled device in which both electron
current and hole current are involved.
e The FET is smaller than a BJT and is thus for more popular in integrated circuits
(ICs).
e FETs exhibit much higher input impedance than BJTs.
e FETs are more temperature stable than BJTs.
e BJTs have large voltage gain than FETs when operated as an amplifier.
e The BJT has a much higher sensitivity to changes in the applied signal (faster
response) than a FET.
Junction Field-Effect Transistor (JFET):
The basic construction of n-channel (p-channel) JFET is shown in Fig. 15-1a (b).
Note that the major part of the structure is n-type (p-type) material that forms the
channel between the embedded layers of p-type (n-type) material. The top of the n-type
(p-type) channel is connected through an ohmic contact to a terminal referred to as the
drain "D", while the lower end of the same material is connected through an ohmic
contact to a terminal referred to as the source "S". The two p-type materials are
connected together and to the gate "G" terminal.
p
D
D
p
G
G
S
Source (S)
n
p-channel
Gate (G)
n-channel
Drain (D)
D
n
S
S
(a)
(b)
Fig. 15-1
G
University of Technology
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Field-Effect Transistors (FETs)
Lecture Fifteen - Page 2 of 8
Dr. Ahmed Saadoon Ezzulddin
Basic Operation of JFET:
e Bias voltages are shown, in Fig. 15-2, applied to an n-channel JFET devise.
e VDD provides a drain-to-source voltage, VDS, (drain is positive relative to source) and
supplies current from drain to source, ID, (electrons move from source to drain).
e VGG sets the reverse-bias voltage between the gate and the source, VGS, (gate is
biased negative relative to the source).
e Input impedance at the gate is very high, thus the gate current IG = 0 A.
e Reverse biasing of the gate-source junction produces a depletion region in the
n-channel and thus increases its resistance.
e The channel width can be controlled by varying the gate voltage, and thereby, ID
can also be controlled.
e The depletion regions are wider toward the drain end of the channel because the
reverse-bias voltage between the gate and the drain is grater than that between the
gate and the source.
ID
Depletion regions
IG = 0 A
G
D
+
p
p
VDS
−
VDD
+
VGS VGG
−
n
S
Electron
flow
Fig. 15-2
JFET Characteristics:
e When VGS = 0 V and VDS < VP (pinch-off voltage)*: ID rises linearly with VDS
(ohmic region, n-channel resistance is constant), as shown in Fig. 15-3.
∗ When VDS is increased to a level where it appears that the two depletion regions
would "touch", a condition referred to as pinch-off will result. The level of VDS
that establishes this condition is referred to as the pinch-off voltage and is
denoted by VP.
University of Technology
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Field-Effect Transistors (FETs)
Lecture Fifteen - Page 3 of 8
Dr. Ahmed Saadoon Ezzulddin
D
I D (mA)
n
G
+
p
p
+
VGS = 0V
_
I DSS
Increasing resistance due
to narrowing channel
VDS < VP
ID
n-channel resistance
_
S
0
VDS (V )
VP
Fig. 15-3
e When VGS = 0 V and VDS ≥ VP : ID remains at its saturation value IDSS beyond VP,
as shown in Fig. 15-4.
D
I D (mA)
n
G
+
VGS = 0V
_
+
p
p
I DSS
Saturation level
I DSS
VGS = 0V
VDS ≥ VP
_
S
0
VP
VDS (V )
Fig. 15-4
e When VGS < 0 and VDS some positive value: The effect of the applied negative-bias
VGS is to establish depletion regions similar to those obtained with VGS = 0 V but at
lower levels of VDS. Therefore, the result of applying a negative bias to the gate is to
reach the saturation level at lower level of VDS, as shown in Fig. 15-5.
Fig. 15-5
University of Technology
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Second Year, Electronics I, 2009 - 2010
Field-Effect Transistors (FETs)
Lecture Fifteen - Page 4 of 8
Dr. Ahmed Saadoon Ezzulddin
Summary:
For n-channel JFET:
1. The maximum current is defined as IDSS and occurs when VGS = 0 V and VDS ≥ VP
as shown in Fig. 15-6a.
2. For gate-to-source voltages VGS less than (more negative than) the pinch-off level,
the drain current is 0 A (ID = 0 A) as appearing in Fig. 15-6b.
3. For all levels of VGS between 0 V and the pinch-off level, the current ID will range
between IDSS and 0 A, respectively, as shown in Fig. 15-6c.
(a)
(b)
(c)
Fig. 15-6
For p-channel JFET a similar list can be developed (see Fig. 15-7).
Fig. 15-7
University of Technology
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Field-Effect Transistors (FETs)
Lecture Fifteen - Page 5 of 8
Dr. Ahmed Saadoon Ezzulddin
Shockley's Equation:
For the BJT the output current IC and input controlling current IB were related by β,
which was considered constant for the analysis to be performed. In equation form:
control variable
↓
IC = β ⋅ I B
↑
constant
In the above equation a linear relationship exists between IC and IB.
Unfortunately, this linear relationship does not exist between the output (ID) and
input (VGS) quantities of a JFET. The relationship between ID and VGS is defined by
Shockley's equation:
control variable
↓
2
⎛ V ⎞
I D = I DSS ⎜⎜1 − GS ⎟⎟
VP ⎠
⎝
↑______↑____
[15.1]
constant
The squared term of the equation will result in a nonlinear relationship between ID and
VGS, producing a curve that grows exponentially with decreasing magnitude of VGS.
Transfer Characteristics:
Transfer characteristics are plots of ID versus VGS for a fixed value of VDS. The transfer
curve can be obtained from the output characteristics as shown in Fig. 15-8, or it can be
sketched to a satisfactory level of accuracy (see Fig. 15-9) simply using Shockley's
equation with the four plot points defined in Table 15-1.
Fig. 15-8
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Field-Effect Transistors (FETs)
Lecture Fifteen - Page 6 of 8
Dr. Ahmed Saadoon Ezzulddin
I D (mA)
Table 15-1
I DSS
⎛ V ⎞
I D = I DSS ⎜⎜1 − GS ⎟⎟
VP ⎠
⎝
VGS (V) ID (mA)
0
IDSS
0.3 VP
IDSS / 2
0.5 VP
IDSS / 4
0
VP
2
I DSS / 2
I DSS / 4
VP
0.5VP
0
VGS (V )
0.3VP
Fig. 15-9
Important Relationships:
A number of important equations and operating characteristics have introduced in the
last few sections that are of particular importance for the analysis to follow for the dc
and ac configurations. In an effort to isolate and emphasize their importance, they are
repeated below next to a corresponding equation for the BJT. The JFET equations
are defined for the configuration of Fig. 15-10a, while the BJT equations relate to
Fig. 15-10b.
(a)
(b)
Fig. 15-10
JFET
⎛ V
I D = I DSS ⎜⎜1 − GS
VP
⎝
ID = IS
IG ≅ 0A
BJT
⎞
⎟⎟
⎠
2
⇔
I C = βI B
⇔
⇔
IC ≅ I E
VBE ≅ 0.7V
University of Technology
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Field-Effect Transistors (FETs)
Lecture Fifteen - Page 7 of 8
Dr. Ahmed Saadoon Ezzulddin
Transconductance Factor:
The change in drain current that will result from a change in gate-to-source voltage can
be determined using the transconductance factor gm in the following manner:
ΔI D = g m ⋅ ΔVGS
The transconductance factor, gm,
(on specification sheets, gm is provided as
yfs) is the slop of the characteristics at the
point of operation, as shown in Fig. 15-11.
That is,
ΔI D
g m = y fs =
ΔVGS V = const .
DS
Fig. 15-11
An equation for gm can be derived as follows:
2
2
⎛ VGS ⎞ ⎤
dI D
d ⎡
d ⎛ VGS ⎞
⎟⎟ ⎥ = I DSS
⎟⎟
⎜⎜1 −
⎢ I DSS ⎜⎜1 −
gm =
=
dVGS Q − pt . dVGS ⎢
V
dV
V
⎥
⎝
P ⎠ ⎦
GS ⎝
P ⎠
⎣
⎡ V ⎤⎡
⎡ V ⎤ d ⎛ VGS ⎞
1⎤
⎟⎟ = 2 I DSS ⎢1 − GS ⎥ ⎢0 − ⎥
⎜⎜1 −
g m = 2 I DSS ⎢1 − GS ⎥
VP ⎠
⎣ VP ⎦ ⎣ VP ⎦
⎣ VP ⎦ dVGS ⎝
gm =
2 I DSS
VP
⎡ VGS ⎤
⎢1 − V ⎥
⎣
P ⎦
[15.2]
and
2 I DSS
VP
where g mo is the value of gm at VGS = 0 V.
Equation [15.2] then becomes:
⎡ V ⎤
g m = g mo ⎢1 − GS ⎥
⎣ VP ⎦
g mo =
[15.3]
[15.4]
JFET Output Impedance:
The output impedance (rd) is defined on the drain (output) characteristics of Fig. 15-12
as the slope of the horizontal characteristic curve at the point of operation.
In equation form:
1 ΔVDS
rd =
=
[15.5]
yos ΔI D V = const .
GS
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Field-Effect Transistors (FETs)
Lecture Fifteen - Page 8 of 8
Dr. Ahmed Saadoon Ezzulddin
where yos is the output admittance, with the units of μS, as appear on JFET specification
sheets.
Fig. 15-12
JFET AC Equivalent Circuit:
The control of Id by Vgs is include as a current source gmVgs connected from drain to
source as shown in Fig. 15-13. The current source has its arrow pointing from drain to
source to establish a 180o phase shift between output and input voltages as will as occur
in actual operation. The input impedance is represented by the open circuit at the input
terminals and the output impedance by the resistor rd from drain to source.
Id
g
+
g mVgs
Vgs
s
_
rd
d
+
Vds
−
s
Fig. 15-13
Exercises:
1. Sketch the transfer curve defined by IDSS = 12 mA and VP = − 6 V.
2. For a JFET with IDSS = 8 mA and VP = − 4 V, determine:
a. the maximum value of gm (that is, g mo ), and
b. the value of gm at the following dc bias points:
VGS = − 0.5 V, VGS = − 1.5 V, and VGS = − 2.5 V.
3. Given yfs = 3.8 mS and yos = 20 μS, sketch the JFET ac equivalent model.
University of Technology
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DC Biasing Circuits of JETs
Lecture Sixteen - Page 1 of 8
Dr. Ahmed Saadoon Ezzulddin
DC Biasing Circuits of JFETs
1. Fixed-Bias Configuration:
For the circuit of Fig. 16-1,
IG ≅ 0A ,
and VRG = I G RG = 0V .
+
V DS
+
VGS
−
−
For the input circuit,
− VGG − VGS = 0 ,
and VGS = −VGG
Fig. 16-1
From Shockley's equation:
⎛ V
I D = I DSS ⎜⎜1 − GS
VP
⎝
⎞
⎟⎟
⎠
2
For the output circuit,
VDD − I D RD − VDS = 0 ,
and VDS = VDD − I D RD
A graphical analysis is shown in Fig. 16-2.
Fig. 16-2
Example 16-1:
For the circuit of Fig. 16-1 with the following parameters: IDSS = 10 mA, VP = − 8 V,
VDD = + 16 V, VGG = 2 V, RG = 1 MΩ, and RD = 2 kΩ, determine the following:
VGSQ, IDQ, VDS, VD, VG, and VS.
Solution:
From Fig. 16-3:
VGSQ = −VGG = −2V , and I DQ = 5.6mA .
VDS = VDD − I D RD
= 16 − (5.6m)(2k ) = 4.8V .
VD = VDS = 4.8V .
VG = VGS = −2V .
VS = 0V .
Fig. 16-3
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DC Biasing Circuits of JETs
Lecture Sixteen - Page 2 of 8
Dr. Ahmed Saadoon Ezzulddin
2. Self-Bias Configuration:
For the circuit of Fig. 16-4,
IG ≅ 0 A,
and VRG = I G RG = 0V .
IS = ID ,
and VRS = I D RS .
For the input circuit,
− VGS − VRS = 0 ,
and
VGS = − I D RS
Fig. 16-4
From Shockley's equation:
⎛ V
I D = I DSS ⎜⎜1 − GS
VP
⎝
⎞
⎟⎟
⎠
2
Self-bias line
For the output circuit,
VDD − VRD − VDS − VRS = 0 ,
and
VDS = VDD − I D ( RD + RS )
A graphical analysis is shown in Fig. 16-5.
Fig. 16-5
Example 16-2:
For the circuit of Fig. 16-4 with the following parameters: IDSS = 8 mA, VP = − 6 V,
VDD = + 20 V, RG = 1 MΩ, RS = 1kΩ, and RD = 3.3 kΩ, determine the following:
VGSQ, IDQ, VDS, VG, VS, and VD.
Solution:
Choosing I D = 4mA , we obtain
VGS = − I D RS = −(4m)(1k ) = −4V .
At the Q-point (see Fig. 16-6):
VGSQ = −2.6V , and I DQ = 2.6mA .
VDS = VDD − I D ( RD + RS )
= 20 − (2.6m)(1k + 3.3k ) = 8.82V .
VG = 0V , and VS = I D RS = (2.6m)(1k ) = 2.6V .
VD = VDD − I D RD = 20 − (2.6m)(3.3k ) = 11.42V ,
or VD = VDS + VS = 8.82 + 2.6 = 11.42V .
Fig. 16-6
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DC Biasing Circuits of JETs
Lecture Sixteen - Page 3 of 8
Dr. Ahmed Saadoon Ezzulddin
Example 16-3 (Common-Gate Configuration):
For the common-gate configuration of Fig. 16-7, determine the following:
VGSQ, IDQ, VD, VG, VS, and VDS.
C2
C1
Fig. 16-7
Solution:
Choosing I D = 6mA , we obtain VGS = − I D RS = −(6m)(680) = −4.08V .
At the Q-point (see Fig. 16-8): VGSQ ≅ −2.6V , and I DQ ≅ 3.8mA .
VD = VDD − I D RD = 12 − (3.8m)(1.5k ) = 6.3V .
VG = 0V .
VS = I D RS = (3.8m)(680) = 2.58V .
VDS = VD − VS = 6.3 − 2.58 = 3.72V .
Fig. 16- 8
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DC Biasing Circuits of JETs
Lecture Sixteen - Page 4 of 8
Dr. Ahmed Saadoon Ezzulddin
Example 16-4 (Design):
For the circuit of Fig. 16-9, the levels of VDQ and IDQ are specified. Determine the
required values of RD and RS.
Fig. 16-9
Solution:
RD =
VRD
I DQ
=
VDD − VDQ
I DQ
=
20 − 12
= 3.2kΩ .
25m
Plotting the transfer curve as shown in
Fig. 16-10 and drawing a horizontal line at
IDQ = 2.5 mA will result in VGSQ = − 1 V,
and applying VGS = − I D RS will establish
the level of RS :
RS =
− VGSQ
I DQ
=
− (−1)
= 0.4kΩ .
2.5m
Fig. 16-10
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DC Biasing Circuits of JETs
Lecture Sixteen - Page 5 of 8
Dr. Ahmed Saadoon Ezzulddin
3. Voltage-Divider Bias Configuration:
For the circuit of Fig. 16-11,
I G ≅ 0 A ⇒ I R1 = I R2 ,
and
VG =
VDD ⋅ R2
.
R1 + R2
For the input circuit,
VG − VGS − VRS = 0 ,
VRS = I S RS = I D RS ,
and
VGS = VG − I D RS
Fig. 16-11
From Shockley's equation:
⎛ V
I D = I DSS ⎜⎜1 − GS
VP
⎝
⎞
⎟⎟
⎠
2
Voltage-divider
bias line
For the output circuit,
VDD − VRD − VDS − VRS = 0 ,
and
VDS = VDD − I D ( RD + RS )
A graphical analysis is shown in Fig. 16-12.
Fig. 16-12
Example 16-5:
For the circuit of Fig. 16-11 with the following parameters: IDSS = 8 mA, VP = − 4 V,
VDD = + 16 V, R1 = 2.1 MΩ, R2 = 270 kΩ, RD = 2.4 kΩ, and RS = 1.5 kΩ, determine
the following: VGSQ, IDQ, VD, VS, VDS, and VDG.
Solution:
VDD ⋅ R2
(16)(270k )
=
= 1.82V .
R1 + R2 2.1M + 270k
VGS = VG − I D RS = 1.82 − I D (1.5k ) ,
when I D = 0mA : VGS = 1.82V , and
1.82
= 1.21mA .
when VGS = 0V : I D =
1.5k
At the Q-point (see Fig. 16-13):
VGSQ = −1.8V , and I DQ = 2.4mA .
VG =
Fig. 16-13
University of Technology
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DC Biasing Circuits of JETs
Lecture Sixteen - Page 6 of 8
Dr. Ahmed Saadoon Ezzulddin
VD = VDD − I D RD = 16 − (2.4m)(2.4k ) = 10.24V .
VS = I D RS = (2.4m)(1.5k ) = 3.6V .
VDS = VDD − I D ( RD + RS ) = 16 − (2.4m)(2.4k + 1.5k ) = 6.64V ,
or VDS = VD − VS = 10.24 − 3.6 = 6.64V .
VDG = VD − VG = 10.24 − 1.82 = 8.42V .
Example 16-6 (Two Supplies):
Determine the following for the circuit of Fig. 16-14;
VGSQ, IDQ, VDS, VD, and VS.
Fig. 16-14
Solution:
For the input circuit of Fig. 16-14,
− VGS − I S RS + VSS = 0 (KVL)
and I G ≅ 0 A ⇒ I D = I S ,
VGS = VSS − I D RS
VGS = 10 − I D (1.5k ) ,
for I D = 0mA ; VGS = 10V , and
10
for VGS = 0V ; I D =
= 6.67 mA .
1.5k
At the Q-point (see Fig. 16-15):
VGSQ = −0.35V , and I DQ = 6.9mA .
For the output circuit of Fig. 16-14,
VDD − I D RD − VDS − I S RS + VSS = 0 ,
VDS = VDD + VSS − I D ( RD + RS )
VDS = 20 + 10 − (6.9m)(1.8k + 1.5k ) = 7.23V .
VD = VDD − I D RD = 20 − (6.9m)(1.8k ) = 7.58V .
VS = VD − VDS = 7.58 − 7.23 = 0.35V .
Fig. 16-15
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DC Biasing Circuits of JETs
Lecture Sixteen - Page 7 of 8
Dr. Ahmed Saadoon Ezzulddin
Example 16-7 (p-channel JFET):
Determine VGSQ, IDQ, and VDS for the p-channel JFET of Fig. 16-16.
Fig. 16-16
Solution:
VDD ⋅ R2 (−20)(20k )
=
= −4.55V .
R1 + R2
20k + 68k
VGS = VG + I D RS = −4.55 + I D (1.8k ) ,
when I D = 0mA : VGS = −4.55V , and
− (−4.55)
= 2.53mA .
when VGS = 0V : I D =
1.8k
At the Q-point (see Fig. 16-17): VGSQ = 1.4V , and I DQ = 3.4mA .
VG =
VDS = −VDD + I D ( RD + RS ) = −20 + (3.4m)(2.7 k + 1.8) = −4.7V .
Fig. 16-17
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DC Biasing Circuits of JETs
Lecture Sixteen - Page 8 of 8
Dr. Ahmed Saadoon Ezzulddin
Exercises:
1. For the common-drain (source-follower) configuration of Fig. 16-18, determine
the following: VGSQ, IDQ, VD, VG, VS, VDG, and VDS.
C1
Vi
RG
VDD + 9V
I DSS = 16mA
VP = −4V
C2
Vo
1MΩ
RS 2.2kΩ
Fig. 16-18
2. For the voltage-divider bias configuration of Fig. 16-19, if VD = 12 V and
VGS = − 2 V, determine the value of RS.
Fig. 16-19
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JFET Small-Signal Analysis
Lecture Seventeen - Page 1 of 7
Dr. Ahmed Saadoon Ezzulddin
JFET Small-Signal Analysis
Common-Source Configuration:
The common-source configuration circuit of Fig. 17-1 includes a source resistor (RS)
that may or may not be bypassed by a source capacitor (CS) in the ac domain.
+ VDD
R D CC
Io
D
CG
Ii
+
Zo
G
Vo
−
Zi
Rsig
+
Vi
+
−
Vs
Z o′
RL
S
RG
RS
−
CS
Fig. 17-1
Bypassed (absence of RS):
For the ac equivalent circuit of Fig. 17-2,
Rsig I i
+
+
Vs
Vi
−
−
Zi
g
Io
d
Zo
+
RG Vgs
g mVgs
−
rd
RD
+
Vo
−
Z o′
RL
s
Fig. 17-2
Input impedance:
Z i = RG
Output impedance:
Approximate (neglecting rd);
Z o = RD
(for rd ≥ 10 RD )
Z o′ = RL RD
Exact (including rd);
Z o = RD rd
Z o′ = RL Z o = RL RD rd
University of Technology
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JFET Small-Signal Analysis
Lecture Seventeen - Page 2 of 7
Dr. Ahmed Saadoon Ezzulddin
Voltage gain:
Approximate (neglecting rd);
Vo = − g mVgs ( RL RD ) ,
Exact (including rd);
Av = − g m ( RL RD rd )
Vgs = Vi ,
Vo
= − g m ( RL RD )
Vi
V
V V
Zi
Avs = o = o ⋅ i = Av ⋅
Vs Vi Vs
Z i + Rsig
Av =
Current gain:
Z
I
Ai = o = − Av ⋅ i
Ii
RL
Phase relationship:
The negative sign in the resulting equation for Av reveals that a 180o phase shift
occurs between the input and output signals.
Unbypassed (include of RS):
For the approximate ac equivalent circuit ( rd ≈ ∞Ω ) of Fig. 17-3,
Ii
Rsig
+
Vs
−
g
+
Zi
−
g mVgs
Vgs
−
+
Vi
Io
d
RG
rd
Zo
+
s
RD Vo
−
RL
RS
Fig. 17-3
Output impedance:
For Vi = 0V , I o + I RD = g mV gs , with V gs = − VRS
Vi = 0V
= −( I o + I RD ) RS ,
so that I o + I RD = − g m ( I o + I RD ) RS , or I o (1 + g m RS ) = − I RD (1 + g m RS ) ,
and I o = − I RD .
Since Vo = − I RD RD , Then Vo = −(− I o ) RD = I o RD , and
V
Z o = o = RD
Io
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JFET Small-Signal Analysis
Lecture Seventeen - Page 3 of 7
Dr. Ahmed Saadoon Ezzulddin
Voltage gain:
Vo = − g mVgs ( RL RD )
Vgs = Vg − Vs = Vi − g mVgs RS => Vi = (1 + g m RS )Vgs
Av =
g (R R )
Vo
=− m L D
Vi
1 + g m RS
Common-Drain (Source-Follower) Configuration:
The common-drain (source-follower) configuration circuit is shown in Fig. 17-4.
+ VDD
D
I i CG
G
CC
Zi
Rsig
S
+
Vi
+
RG
−
Vs
Zo
RS
−
Io
+
Vo
−
RL
Fig. 17-4
For the ac equivalent circuit of Fig. 17-5,
Ii
Rsig
g
+
Zi
Vs
Vi
−
g mVgs
Vgs
−
+
+
d
RG
rd
Io
s
−
RS
Zo
+
Vo
−
RL
Fig. 17-5
Input impedance:
Z i = RG
[high]
Output impedance:
For Vi = 0V , I o + g mV gs = I rd + I RS = Vo rd + Vo RS =>
I o = Vo (1 rd + 1 RS ) − g mV gs , with Vgs = − Vo V =0V => I o = Vo (1 rd + 1 RS + g m ) ,
i
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JFET Small-Signal Analysis
Lecture Seventeen - Page 4 of 7
Dr. Ahmed Saadoon Ezzulddin
and Z o = Vo I o = 1 [1 rd + 1 RS + 1 (1 g m )] =>
Z o = rd RS 1 / g m
Z o = RS 1 / g m =
[low]
RS
1 + g m RS
(for rd ≥ 10 RS )
Voltage gain:
Vo = g mVgs ( RL RS rd ) ,
Vgs = Vg − Vs = Vi − Vo = Vi − g mVgs ( RL RS rd ) => Vi = [1 + g m ( RL RS rd )]Vgs ,
Av =
g m ( RL RS rd )
Vo
=
Vi 1 + g m ( RL RS rd )
[less than 1]
Av =
g m ( R L RS )
1 + g m ( R L RS )
(for rd ≥ 10 RS )
Phase Relationship:
Vo and Vi are in-phase.
Common-Gate Configuration:
The common-gate configuration circuit is shown in Fig. 17-6.
I i CS
Rsig
+
+
Vi
S
Zi
RS
−
Vs
CC
D
G
RD Z o
VDD
−
Io
+
Vo
RL
−
Fig. 17-6
For the approximate ac equivalent circuit ( rd ≈ ∞Ω ) of Fig. 17-7,
rd
Rsig I i
+
+
Vs
Vi
−
−
Zi
g mVgs
s
−
RS
Io
Zo +
RD Vo
Vgs
+
d
g
Fig. 17-7
−
RL
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JFET Small-Signal Analysis
Lecture Seventeen - Page 5 of 7
Dr. Ahmed Saadoon Ezzulddin
Input impedance:
Z i = RS 1 / g m =
RS
1 + g m RS
[low]
(Derive)
Output impedance:
Z o = RD
Voltage gain:
Vo = − g mVgs ( RL RD ) , and Vgs = −Vi =>
Av =
Vo
= g m ( RL RD )
Vi
Phase Relationship:
Vo and Vi are in-phase.
Example 17-1 (Analysis):
For the JFET amplifier circuit of Fig. 17-8 with parameter gm = 2.2 mS, determine:
Zi, Zo, Z o′ , Av = Vo/Vi, Ai = Io/Ii, Avs = Vo / Vs and Vo . Assume rd > 10 RD .
VDD
R1
2.1MΩ
RD 2.4kΩ C
C
Z o 20 μF
CG I i
Rsig
+
Vs
−
10μF Z i
1kΩ
200mV
+ 16V
R2
Io
RL
Z o′
4.7 kΩ
RS1 0.3kΩ
270kΩ
RS 2 1.2kΩ C S
20 μF
Fig. 17-8
Solution:
Z i = R1 R2 = 2.1M 0.27 M = 239kΩ .
Z o = RD = 2.4kΩ , Z o′ = RL RD = 4.7 k 2.4k = 1.59kΩ .
g (R R )
(2.2m)(1.59k )
Av = − m L D = −
= −2.11 .
1 + g m RS 1
1 + (2.2m)(0.3k )
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JFET Small-Signal Analysis
Lecture Seventeen - Page 6 of 7
Dr. Ahmed Saadoon Ezzulddin
Zi
(−2.11)(239k )
=−
= 107 .
RL
4.7 k
Zi
(−2.11)(239k )
Avs = Av
=
= −2.10 ≈ Av .
239k + 1k
Z i + Rsig
Ai = − Av
Vo = Avs Vs = −2.10(200m) = 420mV .
Example 17-2 (Design):
Complete the design of the JFET amplifier circuit shown in Fig. 17-9 to have a voltage
gain magnitude of 17.5 dB, using a relatively high level of gm for this device defined
at VGSQ = VP/4. Assume rd > 10 RD .
VDD + 20V
RD
0.1μF
R
I DSS = 10mA L
VP = −4V
CG
Rsig 1kΩ
0.1μF
+
Vs
−
100mV
CC
RG 10MΩ
RS C S
40 μF
Fig. 17-9
Solution:
VGSQ = VP / 4 = −4 / 4 = −1V ,
⎛ VGS
⎜⎜1 −
VP
⎝
G (dB ) = 20 log10 Av
gm =
2 I DSS
VP
⎞ 2(10m) ⎛
−1 ⎞
⎟⎟ =
⎜1 −
⎟ = 3.75mS ,
4
−
4
⎝
⎠
⎠
⇒ 17.5 = 20 log10 Av ⇒ Av = 7.5 ,
Av = g m ( RL RD ) ⇒ 7.5 = 3.75m(6k RD ) ⇒ RD = 3kΩ .
2
2
⎛ VGSQ ⎞
−1 ⎞
⎟⎟ = 10m⎛⎜1 −
I DQ = I DSS ⎜⎜1 −
⎟ = 5.625mA ,
V
4
−
⎝
⎠
P ⎠
⎝
VGSQ = − I DQ RS ⇒ −1 = −5.625m( RS ) ⇒ RS = 178Ω .
6kΩ
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JFET Small-Signal Analysis
Lecture Seventeen - Page 7 of 7
Dr. Ahmed Saadoon Ezzulddin
Exercises:
1. For each one of the circuits shown in Fig. 17-10, determine:
(b) Zi, and Zo.
(c) Av = Vo / Vi , and Ai = I o / I i .
(a) VGS, and gm.
VDD
RD 3.3kΩ
CC I o
I DSS = 5mA
5.6 μF +
VP = −4V
V R 4.7kΩ
Z o −o L
C
Ii S
VDD + 12V
I DSS = 6mA
VP = −6V
CC
Io
I i CG
8.2 μF
Rsig 0.5kΩ +
Vi RG 2 MΩ 8.2 μF +
+
−
Vs
RS 3.3kΩ Vo RL 2.2kΩ
−
Zi
Zo
−
+ 18V
5.6 μF +
Rsig 1kΩ
Vi RS 1.2kΩ
−
+
Zi
Vs
−
(a)
(b)
Fig. 17-10
2. Choose the values of RD, RS, and RL for the JFET amplifier circuit of Fig. 17-11
that will result in a gain of 18.062 dB. Assume that IDSS = 8 mA, VP = −4 V,
rd ≈ ∞ Ω, VDQ/VDD = 0.375, and IDQ/IDSS = 0.25. Calculate Avs = Vo / Vs , and
sketch Vo.
VDD + 16V
RD
CC
1μF
−
CS
10 μF +
Rsig 1kΩ
Vi
+
Vs
−
+
Vo RL
RS
−
VSS − 1V
50Sin(2π × 103 )t mV
Fig. 17-11
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Frequency Response of JFET Amplifiers
Lecture Eighteen - Page 1 of 5
Dr. Ahmed Saadoon Ezzulddin
Frequency Response of JFET Amplifiers
Low-Frequency Response of JFET Amplifiers:
The Capacitors CG, CC, and CS will determine the lower-cutoff frequency (fL) of the
common-source JFET amplifier shown in Fig. 18-1, but the results can be applied to
any JFET amplifier.
+ VDD
For the cutoff-frequency of CG,
Rsig + Ri = X CG =>
f LG =
RD CC
D
1
2π ( Rsig + Ri )CG
where Ri = RG .
CG
Rsig
+
For the cutoff-frequency of CC,
RL + Ro = X CC =>
f LC =
1
2π ( RL + Ro )CC
where Ro = RD .
For the cutoff-frequency of CS,
Req = X CS =>
f LS =
1
2πReq C S
where Req = RS 1 / g m .
The lower-cutoff frequency,
f L = Max.[ f LG , f LC , f LS ]
Vs
Ro
G
−
Ri
+
Vi
−
+
Vo
S
RG
−
RS
Req
Fig. 18-1
CS
RL
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
Frequency Response of JFET Amplifiers
Lecture Eighteen - Page 2 of 5
Dr. Ahmed Saadoon Ezzulddin
High-Frequency Response of JFET Amplifiers:
The analysis of the high-frequency response of the JFET amplifier is similar to that
encountered for the BJT amplifier. As shown in Fig. 18-2, there are interelectrode and
wiring capacitances that will determine the high-frequency characteristics of the
amplifier. The capacitors Cgs and Cgd typically vary from 1 to 10 pF, while the
capacitance Cds is usually quite a bit smaller, ranging from 0.1 to 1 pF.
+ VDD
RD
CC
C gd
CG
D
G
Rsig
Cds
C gs
RG
+
Vs
RL
CWo
S
CWi
−
RS
CS
Fig. 18-2
Since the circuit of Fig. 18-2 is an inverting amplifier, a Miller effect capacitance
will appear in the high-frequency ac equivalent circuit appearing in Fig. 18-3. The
cutoff frequencies defined by the input and output circuits can be obtained by first
finding the Thevenin equivalent circuits for each section as shown in Fig. 18-3.
Rsig
Vo
+
+
Vs
Vgs
Ri Ci
RThi
−
−
Ci = CWi + C gs + C M i
RThi
−
Ro
RL
RTho
Co
Co = CWo + Cds + C M o
RTho
+
+
EThi
g mVgs
Ci
ETho
−
Fig. 18-3
Co
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Frequency Response of JFET Amplifiers
Lecture Eighteen - Page 3 of 5
Dr. Ahmed Saadoon Ezzulddin
For the input circuit,
f Hi =
and
1
2πRThi Ci
RThi = Rsig RG .
with Ci = CWi + C gs + C M i = CWi + C gs + (1 − Av )C gd .
For the output circuit,
f Ho =
and
1
2πRTho Co
RTho = RL RD .
with Co = CWo + C ds + C M o = CWo + C ds + (1 − 1 / Av )C gd .
The higher-cutoff frequency,
f H = Min.[ f H i , f H o ]
Example 18-1:
For the JFET amplifier circuit shown in Fig. 18-4, with the following parameters:
IDSS = 8 mA, VP = −4 V, rd > 10RD, Cgd = 2 pF, Cgs = 4 pF, Cds = 0.5 pF,
CWi = 5 pF, and CWo = 6 pF.
a. Determine fL, fH, and BW.
b. Sketch the frequency response.
VDD + 20V
RD 4.7 kΩ
D
CG
G
CC
0.5μF
Rsig 10kΩ 0.01μF
+
S
Vi RG 1MΩ
+
−
Vs
RS 1kΩ C S
−
Fig. 18-4
+
Vo RL
−
2μF
2.2kΩ
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Frequency Response of JFET Amplifiers
Lecture Eighteen - Page 4 of 5
Dr. Ahmed Saadoon Ezzulddin
Solution:
I D (mA)
From dc analysis (see Fig. 18-5):
VGSQ = −2V , and I DQ = 2mA ,
gm =
2 I DSS
VP
8
Self-bias line
VGS = −(1k ) I D
⎛ VGSQ ⎞ 2(8m) ⎛ − 2 ⎞
⎜⎜1 −
⎟⎟ =
⎜1 −
⎟ = 2mS ,
4
−
4
V
⎠
⎝
P ⎠
⎝
( I DSS )
6
4
Q-point
I DQ = 2mA
2
Av = − g m ( RL RD ) = −2m(2.2k 4.7 k ) = −3 .
-4 -3 -2 -1
(VP )
f LG =
1
1
=
≈ 16 Hz ,
2π ( Rsig + RG )CG 2π (10k + 1M )(0.01μ )
Fig. 18-5
1
1
=
≈ 46 Hz ,
2π ( RL + RD )CC 2π (2.2k + 4.7 k )(0.5μ )
Req = RS 1 / g m = 1k 0.5k = 333.3Ω ,
1
1
=
≈ 239 Hz ,
2πReq C S 2π (333.3)(2 μ )
The lower-cutoff frequency, f L = Max.[ f LG , f LC , f LS ]
= Max.[16,46,239] = 239 Hz .
RThi = Rsig RG = 10k 1M ≈ 9.9kΩ ,
Ci = CWi + C gs + (1 − Av )C gd = 5 p + 4 p + (1 + 3)(2 p ) = 17 pF ,
f Hi =
1
1
=
≈ 945.66kHz ,
2πRThi Ci 2π (9.9k )(17 p )
RTho = RL RD = 2.2k 4.7 k = 1.5kΩ ,
Co = CWo + C ds + (1 − 1 / Av )C gd = 6 p + 0.5 p + (1 + 1 / 3)(2 p ) = 9.17 pF ,
f Ho =
1
1
=
≈ 11.57 MHz ,
2πRTho Co 2π (1.5k )(9.17 p )
The higher-cutoff frequency, f H = Min.[ f H i , f H o ]
= Min.[945.66k ,11.57 M ] = 945.66kHz .
The bandwidth, BW = f H − f L = 945.66k − 239 ≈ 945.42kHz .
VGS (V )
VGSQ = −2V
f LC =
f LS =
0
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Frequency Response of JFET Amplifiers
Lecture Eighteen - Page 5 of 5
Dr. Ahmed Saadoon Ezzulddin
The frequency response for the low- and high-frequency regions and bandwidth are
shown in Fig. 18-6.
Av
Avmid
dB
f LC
1
10
f LS
100
1k
10k
100k
1M
10M 100M
0
- 3 dB
-5
f (log scale)
f LG
fL
fH
f Hi
f Ho
BW
- 10
- 15
Fig. 18-6
Exercise:
For the JFET amplifier circuit of Fig. 18-7, determine the lower- and higher-cutoff
frequencies and sketch the frequency response.
CWi = 3 pF
CWo = 5 pF
VDD
C dg = 4 pF
RD
C gs = 6 pF R
1 220 kΩ
C ds = 1 pF
CG
Rsig 1.5kΩ
+
Vs
−
1μF
R2 68kΩ
RS
+ 20V
3.9kΩ C
C
6.8μF
I DSS = 10mA RL
VP = −6V
2.2kΩ C S
Fig. 18-7
10 μF
5.6kΩ