JFET BIASING
4 types of biasing circuit will be studied in this course:
(i).
(ii).
(iii).
(iv).
Fixed biasing
Self biasing
Mid-point biasing
Voltage division biasing
Before analyzing the respective biasing circuitries, Q
point and load line need to be known.
1. Load line and Q-point
A load line connects 2 points on the drain
characteristic. One point is on the ID axis and the
other is on the VDS axis. For a known VGS, the
intercept point between the load line and the drain
curve can determine the operating/quiescent (Q) point
and consequently, the IDQ and VDSQ.
ID
Load line (determined
from the circuit)
IDSS
VGS =0
-1V
IDQ
Q-point
VDS(sat) = Vp VDSQ
25
-2 V( VGSQ )
-3 V
-4 V
VDS VGS(off)
2.
Fixed biasing
RD
ID
RG
VDD
VDS
VGG
ID
To determine the Q-point (IDQ and VDSQ), the
relationship between the ID and VDS needs to be
known.
Looking at the
characteristic):
output
loop
(Loop
1
-
drain
-VDD +IDRD +VDS =0
ID = VDD - VDS =- 1 VDS + VDD
RD
RD
RD
This expression is in the form of y = mx + c.
Slope is - 1 and c = VDD .
RD
RD
If ID = 0, VDS = VDD. Hence, the load line intersects the
ID axis at VDD and the VDS axis at VDD.
RD
26
Slope is - 1 and c = VDD . At ID = 0, VDS = VDD.
RD
RD
Hence, the load line intersects the ID axis at VDD and
RD
the VDS axis at VDD. Once VGSQ is known, IDQ and VDSQ
can be determined.
ID
VDD
RD
Load line with
a slope of - 1
RD
IDSS
IDQ
VGS =0
Q-point
Vp VDSQ VDD
3.
VGS1
VGSQ
VGS2
VGS3
VDS VGS(off)
Self-biasing
In order to operate in the saturation region (hence, as
an amplifier), G-S of the JFET needs to be reverse
biased. To obtain this condition, the VGS has to be
negative for the n-channel JFET and positive for the
p-channel JFET. The following topologies will enable
the mentioned condition to be achieved without the
need of an external voltage to be connected to the G.
Due to this capability, this topology is called selfbiasing circuit.
27
RD
ID
RD
ID
VDD
RG
VDD
VSD
VDS
ID
RG
RS
ID
RS
In Cct. A:
-VDD + IDRD + VDS + IDRS = 0.
IDRD + VDS + IDRS = VDD.
VS = IDRS is positive.
Since IG ≈ 0, then VRG ≈ 0. Hence, VG = 0.
Since VG = 0 and VS is positive, VGS=VG-VS= negative.
So, the n-channel is properly biased as an amplifier.
VGS= -VS = - IDRS.
RS = VS / ID.
In Cct. B:
IDRS + VSD + IDRD - VDD = 0.
IDRS + VSD + IDRD = VDD.
Since IDRS is positive and 0 - VS = IDRS , VS = - IDRS.
Therefore, VS is negative.
Since IG ≈ 0, then VRG ≈ 0. Hence, VG = 0.
Since VG = 0 and VS is negative, VGS=VG-VS= positive.
So, the p-channel is properly biased as an amplifier.
VGS= -VS = IDRS.
RS = VGS / ID.
For both n- and p-channel JFET, RS = |VGS| / ID.
28
RD
ID
RD
ID
VDD
ID
RG
VDD
VSD
VDS
ID
RG
RS
RS
In the JFET, majority carriers are moving from S to D.
In the n-channel JFET, VDD is positive to attract the
electrons to move from S to D. Conventional current
flow is opposite to the flow of electron. Hence, the
direction of current is from D to S.
In the p-channel JFET, VDD is negative to attract the
holes to move from S to D. Conventional current flow
is the same as the flow of holes. Hence, the direction
of current is from S to D.
Determining the operational point of the self-biasing
JFET
2 ways:
1.
2.
graphical method, i.e. from the transfer and drain
characteristic


DSS 

from calculation, i.e. using ID =I
29

1- VGS 
VGS(off) 
2
Example 1
Determine the RS that is needed to self bias an nchannel JFET that has the transfer characteristic
curve as shown below at VGS = -5 V.
ID (mA)
RD
IDSS
ID
VDS
RG
ID
RS
-VGS(V)
VGS(off)
Solution
From the graph, at VGS = -5 V, ID = 6.25 mA.
RS = |VGS | / ID = 5 / 6.25 m = 800 Ω
30
VDD
Example 2
Determine VDS and VGS. Given ID = 5 mA.
10 V
RD =1kΩ
RG
D ID
G
+V
- DS
S ID
RS =500 Ω
Solution:
VG = 0 V (criteria of the self-biased circuit).
VS = IDRS = 5m x 500 = 2.5 V
VGS = - VS
VGS = -2.5 V
VDD = IDRD + VDS + IDRS
VRD = IDRD = 5m x 1k = 5 V
VRS = IDRS = VS = 2.5 V
VDS = 10 – 5 – 2.5 = 2.5 V
31
4.
Mid-point biasing
The JFET is typically biased near the mid-point of the
drain characteristic curve to achieve maximum signal
swing at the input. The purpose is to obtain maximum
undistorted ouput signal.
ID
IDSS
VGS =0
-1V
IDQ
VGSQ
-4 V
Vp VDSQ
VDS
Steps to obtain the Q-point
1.
Mid-point biasing enables maximum drain current
swing between IDSS and 0. Hence, IDQ = IDSS .
2


DSS 

ID =I

V
GSQ

1VGS(off) 
2
From
3.
VGS(off)
.
3.4
To set the drain voltage at mid-point, VD = VDD .
2
Choose large RG to prevent loading effect.
RG = 1 M Ω
VGSQ ≈
4.
32
and
when
IDQ = IDSS ,
2
2.
Example 3
Determine the resistors to be implemented in the
following circuit for mid-point biasing. The parameters
for the JFET are: IDSS = 15 mA and VGS(off) = -8 V.
12 V
RD
RG
D ID
G
+V
- DS
S ID
RS
Solution
IDQ = IDSS =7.5 mA
2
V
VGSQ = GS(off) = -8 =-2.35 V
3.4 3.4
VDQ = VDD = 12 =6 V
2
2
RG = 1 M Ω
VGSQ = - VS
VSQ = 2.35 V = IDQRS
RS = VSQ / IDQ = 2.35 /7.5 m = 313 Ω
RD = VDD - VDQ / IDQ = 12 - 6 /7.5 m = 800 Ω
33
5.
Voltage division biasing
VDD
RD
R1
R2
D ID
G
+V
- DS
S ID
RS
VS has to be more positive than VG to maintain the
requirement of a reverse biased G-S.
VS = IDRS


VG =  R 2  VDD
 R1 + R 2 
34
Example 4
Determine ID and VGS for the following voltage division
biased JFET. Given VDD = 12 V, VD = 7 V, RD = 3.3
kΩ, RS = 1.8 kΩ, R1 = 6.8 MΩ and R2 = 1 MΩ.
VDD
RD
R1
ID
VDS
ID
RS
R2
Solution:

 

ID =  VDD - VD  =  12 -7  =1.52 mA
RD   3.3 k 





1M
12 =1.54 V
VG =  R 2  VDD = 

R
+
R
6.8
M
+
1M


 1
2
VS = IDRS = 1.52 m x 1.8 k = 2.74 V
VGS = VG – VS = 1.54 – 2.74 = -1.2 V
35