Multi-TSV Crosstalk Compensation Based On
Digital MIMO Channel Equalization
Tobias Seifert and Gerhard Fettweis
Vodafone Chair Mobile Communications Systems
Technische Universität Dresden
Dresden, Germany
Email: {tobias.seifert, fettweis}@ifn.et.tu-dresden.de
Abstract—Signal transmission in 3D integrated circuits (ICs) over
through-silicon via (TSV) links inherently creates coupling interference on
signal TSVs. This interference might be a crucial factor for the functional
correctness of 3D ICs and therefore needs to be tackled.
In this paper we propose a novel multi-TSV channel equalization
method deployed in the digital domain, allowing almost perfect compensation of the crosstalk by inverting the impact of the individual
coupling channels. The proposed equalization technique is carried out
for a TSV-to-TSV scenario with realistic I/O termination and the
corresponding performance is analyzed under consideration of analogto-digital converter (ADC) impairments. The results show, that even in
the presence of significant ADC clock jitter and tight ADC quantization
restrictions, remarkable crosstalk mitigation can be accomplished.
wireless communications, we regard the multi-TSV channel as a
MIMO channel to which equalization as well as channel estimation
techniques can directly be applied. We also analyze the robustness of
this approach against analog-to-digital converter (ADC) impairments,
namely ADC quantization noise and ADC clock jitter.
The remainder of the paper is organized as follows: Section II
describes the multi-TSV system as well as the general channel equalization concept. Section III deals with a basic TSV-to-TSV lumped
circuit model and its crosstalk channel frequency response, while
section IV shows simulation results of the equalization performance.
Section V concludes the paper.
I. I NTRODUCTION
II. C ONCEPT OF C ROSSTALK C OMPENSATION BASED ON MIMO
C HANNEL E QUALIZATION
3D chip-stacks have added a new dimension to circuit design.
Those designs can benefit from reduced length of global interconnects, resulting in decreased power consumption and increased area
efficiency [1]. The signal transfer between two integrated circuit (IC)
layers is usually realized by through-silicon via (TSV) links. Since the
TSVs are directly placed in the substrate and respectively surrounded
by a thin insulator, electrical coupling interference (crosstalk) can
occur in neighboring TSVs.
In order to preserve most chip area for active circuits and to
provide high vertical bandwidth, it is desirable to arrange multiple signal TSVs in a highly dense TSV cluster, exacerbating the
problem of TSV-to-TSV coupling. Additionally, many applications
demand for high energy efficiency, which requires capacitively driven
transceivers with low voltage swings to limit the dynamic power
consumptions [2]. Thus, even low coupling interference between
signal TSVs can cause critical signal distortion that affects the
functional correctness of the whole 3D IC system.
Crosstalk mitigation techniques have therefore been studied intensively, mostly concentrating on conventional signal shielding by
adding ground TSVs [3] or using grounded guard rings and coaxial
TSVs [4], [5]. In [6] and [7], lossy passive contacts are used to
compensate the capacitive effect of TSV interconnects and perform a
partial equalization of the TSV frequency response. However, these
approaches usually lack acceptable area efficiency or do not adapt
well to arbitrary TSV coupling channels. Furthermore, the introduced
shielding capacitances reduce the achievable TSV bandwidth.
In this paper a novel crosstalk compensation approach is presented
that uses digital signal processing to equalize the TSV voltage
signals. This approach is directly inspired by the field of mobile
communications, where signals are spatially-multiplexed, transmitted
over a time-dispersive multiple-input multiple-output (MIMO) radio
channel and finally equalized at the receiver [8]. In analogy to
This work has been supported by the European Social Fund in the
framework of the Young Investigators Group “3D Chip-Stack Intraconnects”.
We consider two ICs which are vertically connected by N TSV
signal links, resulting in a 3D chip-stack. Note that the TSV array is
not restricted to be arranged on a regular grid structure.
From a communications perspective it is possible to regard the
upper IC layer as a transmitter, the N -TSV array as a MIMO channel
and the lower IC layer as a receiver. Thus, for each TSV the upper
chip transmits a voltage signal xi (t) and the lower chip receives a
corresponding voltage signal yj (t) with i, j = 1, ..., N . Their inputoutput relation is given by the channel impulse response hij (t). Since
the signal yj (t) might be interferred by transmit signals of other TSV
signal links i ̸= j, it has to be described as the superposition of all
input signals, respectively convolved by individual channel impulse
responses, leading to
yj (t) =
N
∑
(hij ∗ xi )(t).
(1)
i=1
Stacking up all N output signals and transforming them to frequencydomain results in the compact matrix description

 


Y1 (f )
H11 (f ) · · · H1N (f )
X1 (f )
 ..  
  .. 
..
..
..
(2)
 . =
 . .
.
.
.
YN (f )
HN 1 (f ) · · · HN N (f )
XN (f )
| {z } |
{z
} | {z }
Y
H
X
Note that the channel matrix H(f ) is assumed to be symmetric
due to channel reciprocity. Each frequency response Hii (f ) on the
main diagonal represents the direct channel of TSV i, while each
off-diagonal function Hij (f ) corresponds to the coupling channel
between input port of TSV i and output port TSV j, causing crosstalk
voltage at the output port of TSV j. In this paper we show how
the crosstalk interference can be significantly reduced by jointly
equalizing the received signal vector y(t).
Channel equalization is a well-known technique in digital communications [8], [9], deployed to tackle intersymbol interference (ISI)
Zout,2
and to improve the reliability of the estimated transmit symbols.
For this purpose, Y(f ) is filtered by the inverse channel matrix,
approximated by a filter
Cox
Cox
GSi
TSV 2
(3)
the so-called zero-forcing (ZF) equalizer [9]. Ĥ denotes the approximation or estimate of H. Since the TSV channel does not change over
time, the estimation of the channel as well as ZF-filter determination
can be carried out as an initial calibration procedure.
CSi
X̂(f ) = G(f )Y(f ).
(4)
Zin,2
B. Channel EQ: Discrete-Time View
In communications, the equalization is usually carried out by a
digital filter, assuming that a discrete-time signal yj [k] is received at
the output port of TSV j. Similarly, the TSV channel is given by
M + 1 channel coefficients hij [m] with m = 0, ..., M . Note that
M = 0 refers to a memoryless channel. Taking these changes into
account, (1) turns into a discrete convolution, explicitly expressed by
i=1
M ∑
N
∑
Parameter
Value
TSV height l
TSV radius r
Insulator Si02 thickness t
TSV center-to-center distance d
75 µm
2.5 µm
0.5 µm
10 µm
Supply voltage VDD
I/O input capacitance Cin
I/O output resistance Rout
1.0 V
48 fF
1 kΩ
TABLE I: TSV dimensions and I/O cell characteristic used in this paper.
A. Lumped circuit model
(hij [m]xi [k − m]),
m=1 i=1
|
{z
(5)
}
yjIF [k]
where yjIF [k] denotes the crosstalk interference caused by previously
transmitted signal values xi [k − m], with m ≥ 1. This interference
can be subtracted in advance from the received signal by approximating the transmit signal xi [k − m] = x̂i [k − m] and the channel
coefficients hij [m] = ĥij [m]. Subsequently, the interference-reduced
received signals yj′ [k] are jointly equalized by means of the linear ZFN ×N
filter G0 = Ĥ−1
is composed of the estimated
0 , where Ĥ0 ∈ R
fundamental channel coefficients ĥij [0]. The matrix description for
the equalized signal vector in time-domain is
x̂k = G0 yk′ ,
Zin,1
Fig. 1: Lumped circuit model of two parallel TSVs, coupled by the impedance
ZC and terminated by input and output impedances Zin and Zout of an I/O
cell.
When Ĥ = H, the equalized received signals are identical to the
original transmit signals (X̂ = X) and the crosstalk is completely
compensated.
(hij [0]xi [k]) +
RTSV
ZC
Assuming that G is a matrix of analog filter functions Gij (f ), the
resulting received and equalized signal vector in frequency-domain
is
N
∑
Cox
Cox
A. Channel EQ: Continuous-Time View
yj [k] =
LTSV
TSV 1
G = Ĥ−1 ,
Zout,1
with yk′ = yk −
∑
Two adjacent TSVs can be modeled by lumped elements, as shown
in Fig. 1. The capacitance Cox of the silicon dioxide insulator,
the substrate capacitance Csi and substrate conductance Gsi are
derived from material properties and TSV dimensions. Since the TSV
impedance is very low in comparison with the coupling impedance,
the components RTSV and LTSV are neglected [10]. For the sake of
simplicity, we therefore assume that the direct channel frequency
response is ideally constant, i.e. HD (f ) = 1.
The remaining circuit components are calculated by
Cox =
Csi =
(6)
m=1
where ML ≤ M is the channel memory length considered for
equalization.
III. TSV- TO -TSV CROSSTALK COUPLING
In the following we set N = 2 and focus on TSV-to-TSV coupling,
determined by the crosstalk channel frequency response Hc (f ). The
direct channel frequency response is given by HD (f ), leading to the
frequency-domain TSV channel matrix
[
]
HD (f ) Hc (f )
H=
.
(7)
Hc (f ) HD (f )
(
d
2(r+t)
ln
σ
Gsi =
Csi .
ϵ0 ϵsi
ML
Ĥm x̂k−m
πϵ0 ϵox l
)
(
ln r+t
r
(8)
πϵ0 ϵsi l
√
)
d2
+ 4(r+t)
2 − 1
(9)
(10)
Throughout this paper, the values for the TSV length l, the TSV
radius r, insulator thickness t and TSV center-to-center distance d
are set as stated in Table I.
B. I/O termination analysis
Both TSVs are connected to I/O cells whose input impedance Zin
and output impedance Zout have to be taken into account when the
total transmission behaviour is analyzed. If we assume that the ports
of each TSV are terminated by identical I/O cells, we obtain the
crosstalk channel frequency response
Hc (f ) =
2
Zout
Zc
Zout Zin 2
,
+ Zout Zin (3 + 2Zc ) + Zin2 (2Zout + Zc )
(11)
x2(t)
x1(t)
ZF-Equalization
(digital domain)
ADC
−20
|Hc (f)| [dB ]
Zout
−40
y2(t)
−60
−80
h21(t)
1/TS
Sampler
Zout
1/TS
Sampler
n-bit
Quantizer
y2[k]
-
Zin
G0
50 Ω termination
−100
7
10
y1[k]
ADC
y1(t)
ZC
Zin
I/O cell termination
n-bit
Quantizer
Delay
H1
-1
8
9
10
10
Frequ en cy / H z
z
10
10
z-1
x2[k] x1[k]
where the coupling impedance is given by
(
)
GSi
ωCSi
1
.
Zc = 2
−j
+
ωCox
GSi + (ωCSi )2
G2Si + (ωCSi )2
(12)
Often S-parameters are used to describe the transfer behaviour in
the frequency domain. For this purpose, the input and output ports
of the TSVs are terminated by 50 Ω. However, in a real 3D IC,
TSVs are connected to I/O cells which typically represent a much
higher impedance. Hence, the termination condition of the model is
changed to input impedance Zin = −j(1/Cin ) and output impedance
Zout = Rout (see Table I) of a possible 65 nm I/O cell.
Fig. 2 depicts the magnitude of Hc (f ) for both cases. The curves
show that the high impedance of a realistic I/O termination exposes
a significant larger coupling level (more than 30 dB for f ≤ 2 GHz)
compared to the case of 50 Ω termination.
Throughout the rest of the paper, I/O cell termination is used as
desribed.
IV. TSV- TO -TSV CROSSTALK CHANNEL EQUALIZATION
The simplified lumped circuit leads to the transmission system
model shown in Fig. 3. The received signals y1 (t) and y2 (t) are
sampled and quantized by an ADC and subsequently equalized in the
digital domain. Note that Zin represents now the input impedance of
the ADC.
A. Continuous-Time View
Applying a 1 GHz signal of magnitude 1.0 V to the input x1 (t)
leads to a crosstalk voltage signal at the output y2 (t), as depicted in
Fig. 4. A peak voltage of 180 mV is observed.
In order to illustrate the equalization principle as described in II-A,
the ADC sampling rate is assumed to be ideally high enough to
resolve all frequencies of an arbitrary input signal, hence we are
regarding continuous time signals. However, a limited number of
ADC quantization stages is considered, resulting in quantized output
signals ỹ1,2 (t). It is assumed that the crosstalk channel Hc (f ) is
perfectly known to the equalizer.
By using (3) and (4), equalization results in
(
)
1
X̂2 (f ) =
HD (f ) Ỹ2 (f ) − Hc (f ) Ỹ1 (f )
(13)
det (H)
in frequency-domain. Figure 4 depicts the equalized time signal
x̂2 (t), depending on various ADC quantization. It can be seen that
Fig. 3: Transmission system model of the two parallel TSV links, including
ADCs and the equalization unit according to (6). The considered memory
length of the depicted equalizer is ML = 1
Equ alized S ign al x̂2 (t) / V
Fig. 2: Termination analysis for the TSV-to-TSV coupling channel. In the
50 Ω case, the input and output impedances are Zin = Zout = 50 Ω. For the
I/O cell case Cin = 48 fF and Rout = 1 kΩ.
0.2
0.1
0
−0.1
−0.2
w/o EQ, y (t)
EQ (6 bit)
EQ (4 bit)
EQ (8 bit)
2
−0.3
0
0.5
1
1.5
2
Time / n s
2.5
3
Fig. 4: Illustration of the crosstalk signal and the equalized signal observed at
TSV 2 when a 1 GHz signal is applied to TSV 1. The equalization is carried
out for the ADC output signal ỹ2 (t), uniformly quantized within the range
[−0.2 V, 1.2 V].
the larger the error due to bit width limitation, the more flickering is
exhibited in the equalized signal. However, even for 4 bit resolution
the observed quantization noise is always much lower than the peak
voltage in the non-equalized case. For 6 bit the flickering is already
negligible.
B. Discrete-Time View
When TSVs are used as network-on-chip links, yj (t) represents
a digital signal. One or multiple comparators (each adjusted to the
respective threshold level) are usually deployed at the output ports
of the TSVs to decide for the correct binary sequence. However,
the induced crosstalk interference may lead to wrong decisions,
depending on the magnitude and decay time of the interference signal
and the threshold level distances. In this regard, capacitively driven
transceivers are especially susceptible to interference and noise [2].
In order to show the potential of equalization for the system
depicted in Fig. 3, we assume no 1-bit comparator but a configurable
ADC. The ADC samples the TSV signal yj (t) at half the symbol
period TS but its clock is impaired by (jitter, )modeled as a gaussian
random variable n with distribution N 0, σ 2 . Hence, we obtain the
EQ (M =1)
EQ (M =0)
EQ (M =2)
80
L
L
70
L
60
RMSD / mV
RMSD / mV
70
w/o EQ
50
40
30
w/o EQ
EQ (M =1)
EQ (M =0)
EQ (M =2)
80
L
L
70
L
60
RMSD / mV
80
50
40
30
10
10
0
0.06
0.08
Clock Jitter σ / ns
(a) 4-bit ADC
L
30
10
0.04
L
40
20
0.02
EQ (M =2)
L
50
20
0
EQ (M =1)
EQ (M =0)
60
20
0
w/o EQ
0
0
0.02
0.04
0.06
Clock Jitter σ / ns
(b) 6-bit ADC
0.08
0
0.02
0.04
0.06
0.08
Clock Jitter σ / ns
(c) 8-bit ADC
Fig. 5: Illustration of the RMSD for the equalized (EQ) x̂1/2 [k] and non-equalized (w/o EQ) ỹ1/2 [k] received signal, plotted over the ADC clock jitter
standard derivation σ. A (a) 4-bit, (b) 6-bit and (b) 8-bit uniform quantizer with the range [−0.2 V, 1.2 V] is used. Additionally, the impact of different channel
memory lengths ML is also investigated.
discrete output sequence
ỹj [k] = ⌊yj (t = tk )⌉,
with tk =
(14)
(
)
1
k+
TS + n, k ∈ N.
2
⌊·⌉ denotes the quantization operation. The ADC output is equalized
as shown in (6). To quantify the equalization performance, the rootmean-square derivation (RMSD) for a single TSV, defined by
√
(
)
E∥x̂k − xk ∥2
RMSD x̂i [k] =
(15)
N
is used, where xk is the reference transmit vector with
xi [k] ∈ {0 V, 1 V}. Note that the channel coefficients hij [k] are
perfectly known to the equalizer.
The performance analysis has been carried out for the TSV-to-TSV
scenario with N = 2 and a symbol period of TS = 0.5 ns. The mean
square derivation was determined by averaging over 3 · 105 symbol
transmissions and jitter realizations. The plots in Fig. 5 depict the
equalization performance depending on the ADC clock jitter. We see
that at least two channel coefficients (ML ≥ 1) have to be considered
to benefit from equalization. An small performance increase for
ML = 2 can only be observed if the clock jitter and quantization
noise are low enough. Otherwise, the ADC impairments dominate the
overall performance. For 4 bit resolution and jitter σ < 0.08 ns, the
crosstalk interference is reduced by more than 50 %. By increasing
the signal resolution up to 8 bit, the quantization noise decreases and
the jitter noise becomes dominant, as shown in Fig. 5(c). If no jitter
noise is present, the remaining derivation is less than 2 mV and the
crosstalk interference is almost perfectly compensated.
V. C ONCLUSION
This work presents a novel approach to perfectly compensate
crosstalk effects in TSV arrays by means of digital equalization of the
multi-TSV channel. The main advantage of this approach is its ability
to adapt to arbitrary coupling channels, taking even mismatch into
account. Moreover, since crosstalk is not avoided in advance, TSVs
can be arranged very compactly, leading to high area efficiency.
To prove the described concept, the equalization performance was
evaluated for a TSV-to-TSV scenario based on a lumped circuit
model. Although both ADC clock jitter and ADC quantization noise
limits the performance, remarkable crosstalk reduction could be
observed even for e.g. 4-bit quantization. Moreover, the performance
can be further optimized using a non-uniform quantizer, making this
approach feasible with low additional circuit complexity.
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