Submission Number: 435
1
A Combined Dynamic and Static Frequency
Divider for 40GHz PLL in 80nm CMOS
George von Büren1, Christian Kromer1, Frank Ellinger1, Alex Huber2, Martin Schmatz3, Heinz
Jäckel1
1
Electronics Laboratory, ETH Zürich, 8092 Zürich, Switzerland
2
ZMA, Zentrum für Mikroelektronik Aargau, 5210 Windisch, Switzerland
3
IBM Research, Zurich Research Laboratory, 8803 Rüschlikon, Switzerland
Abstract:
A divide-by-four circuit divides frequencies from 31GHz to 41GHz at input signal
amplitudes ≤0.5Vpp. The implemented circuit consists of a dynamic followed by a static
frequency divider. The dynamic and static frequency dividers consume 2mA and 1mA,
respectively, from a 1.1V supply.
Paper:
Future high-density chip-to-chip links require data rates of up to 40Gb/s per channel to
meet the Tb/s aggregate bandwidth demand. Transmitter and receiver incorporate D-flip-flops
(DFF), consisting of two latches (TFF) to retime the data, ideally at full-rate speed. The clock
driving the DFFs is generated by a PLL, which therefore requires a full-rate frequency divider in
the CMU. The prescaler typically is the speed-limiting block. In addition, due to the limited
system power budget, all circuits need to be optimized for low power consumption.
Consequently, the design of low-power and high-speed frequency dividers is a challenging task.
The implemented circuit shown in Fig. 1 consists of a dynamic and a static frequency
divider followed by a 50Ω buffer for test and measurement equipment. Conventional static
frequency dividers (SFD) use a DFF, which allows broadband operation from DC to a maximum
division frequency. As long as the slew rate of the input signal is high enough, the maximum
division frequency of a static frequency divider is approximately 1/(2tpd), where tpd denotes the
latch propagation delay. Higher operating frequencies can be achieved by dynamic frequency
dividers (DFD) based on Miller’s work in 1939 on regenerative modulation because the loop
Submission Number: 435
2
contains only one tpd instead of two. Therefore, a DFD is chosen for the first divider stage. The
limited operating range does not pose a problem for most applications where the divider operates
in a narrow frequency range only. Fig. 1 shows the block diagram for a regenerative frequency
divider consisting of a mixer, a filter and an amplifier. Assuming an input signal fin and a
feedback signal fout, the mixer output signal has the frequency components fin±fout. Only the
component fin-fout can pass the filter and consequently stable operation exists if fout=fin–fout=fin/2.
The operating bandwidth is limited by the band pass frequency response of the open loop. The
maximum operating frequency limit is reached when the open loop gain is 1 at fin/2. The lower
limit for frequency division is obtained when the filter no longer suppresses the frequency
components 3fin/2 or when the open loop gain falls below 1 at fin/2.
Most Miller dividers incorporate a double balanced Gilbert cell mixer realized as a RFport feedback [1] or LO-port feedback [2]. In contrast to a SFD where the load impedance
generates a logic swing, the role of the load of the DFD is to convert the desired current
component mixed by the Gilbert cell to a voltage. Bipolar implementations introduce source
followers in the feedback loop to provide level shifting, sufficient broadband gain around the loop
for fin/2 and suppression of higher order odd-harmonic components at 3fin/2, 5fin/2… due to the
inherent low pass characteristic of the mixer. Operating frequencies over one octave can be
achieved [1]. The design challenge of a CMOS broadband regenerative divider is the design of a
feedback network featuring a low output impedance, a voltage gain > 1 and minimum delay. A
recent work [2] implemented a DFD operating from 17 to 27GHz in 0.13µm CMOS. The
feedback consists of a differential amplifier stage responsible to filter out 3fin/2 followed by an
inductive peaked differential stage to amplify fin/2. Employing a BPF in the Miller divider
increases the operating frequency. A 38 to 41GHz DFD with a LC-tank load with a quality factor
(Q) of 8 at 20GHz and a feedback coupling capacitance has been reported in 0.18µm CMOS. [3].
Fig. 2 illustrates the circuit schematic of the proposed DFD. The input is fed to the LOport (M1 to M4), where the mixer output is connected to the RF-port via the feedback network
consisting of a combination of a common source and source follower [4]. M7 and M8 are lowthreshold-voltage (LVT) FETs to diminish their overdrive voltages. M9 and M10 are highthreshold-voltage (HVT) FETs to extend the saturation region of the transistors for large signal
operation. The transistors M7 to M10 perform level shifting, isolate the high-impedance node at
the mixer output and drive the RF-port and the following frequency divider. The advantage of the
proposed feedback topology is that the voltage gain can be set to >1, compared to a source-
Submission Number: 435
3
follower, of which the voltage gain is always <1. Furthermore, the frequency dependent phase
shift is lowered towards higher frequencies due to the lowered output impedance of the source
follower. Because of the large loop gain the Q of the band pass load can be decreased to broaden
the operating range. The load consists of a resistor of 140Ω and a spiral inductor having a series
inductance and resistance of 3nH and 88Ω, respectively. The inductor occupies four metal layers
on an area of 15µm × 15µm and can handle a maximum DC current of 0.8mA. The simulated
open loop band pass frequency response of the DFD showing the operating region at fin/2 is
depicted in Fig. 3.
The TFFs of the SFD (Fig. 4) are optimized for low power consumption and minimum
input amplitude at 20GHz. To decrease the rise and fall time of the SFD peaking inductors of a
series inductance and resistance of 2nH and 75Ω, respectively, have been added in series to the
1kΩ load resistance.
All measurements of the divide-by-four and SFD circuits are performed on wafer. In
contrast to the DFD the SFD self-oscillates if no input power is applied. The measured selfoscillation frequency of the SFD is 11GHz. The measured and simulated minimum single-ended
input amplitude curves for correct division for the SDF and the divide-by-four circuits are
illustrated in Fig. 5. The operating range of the divide-by-four circuit is from 31 to 41GHz. The
measured output spectrum of the divide-by-four circuit with a 40GHz input amplitude of 0.4Vpp
is shown in Fig. 6 and exhibits a phase noise of -105dBc/Hz at 500kHz offset. The current
consumption of the DFD is 2mA where the Gilbert cell and the feedback network consume 1mA
each. The SFD consumes 1mA and the output buffer 26mA. The circuits operate with 1.1V
supply.
Figure 7 shows the implemented divide-by-four frequency divider including the output
buffer fabricated in IBM’s standard CU-08 8M CMOS process with a nominal transistor gate
length of 80nm. The DFD and SFD occupy a chip area of 20µm x 60µm and 20µm x 30µm,
respectively.
ACKNOWLEDGMENT
The authors thank D. Barras, L. Rodoni, G. Sialm, M. Kossel, C. Menolfi, T. Morf, T. Toifl and J.
Weiss for fruitful discussions and the IBM foundry team in Fishkill/NY for manufacturing the
CMOS chips. This work was supported by the Swiss Federal Office for Professional Education
and Technology, contract/grant number: KTI 6726.1.
Submission Number: 435
4
REFERENCES
[1] H. Knapp, et al., “A 79GHz Dynamic Frequency Divider in SiGe Bipolar Technology”,
IEEE ISSCC Dig. Tech Papers, pp. 208-209, Feb. 2000.
[2] U. Singh, and M. M. Green, “High-Frequency CML Clock Divider in 0.13µm CMOS
Operating Up to 38GHz”, IEEE JSSC, Vol. 40, No. 8, pp. 1658-1661, Aug. 2005.
[3] J. Lee, and B. Razavi, “A 40GHz Frequency Divider in 0.18µm CMOS Technology”, IEEE
JSSC, Vol. 39, No. 4, pp. 594-601, Apr. 2004
[4] C. Kromer, et al., “A 100mW 4×10Gb/s Transceiver in 80nm CMOS for High-density
Optical Interconnects”, accepted for publication in the IEEE JSSC, Dec. 2005.
Dynamic divider
Static divider
Buffer
L=3nH
R=230Ω
f 3f
, ,...
2 2
DP
FILTER
f
QP
DP
TFF 1
DM
f
2
XM
QP
QM
DM
XP
f/4
TFF 2
CIP
QM
M1
M3
M4
(4µm/80nm)
(LVT)
M7
M8
M2
(4µm/80nm)
(4µm/80nm)
CIM
COP
M5
COM
M6
(4µm/80nm) (4µm/80nm)
VBIAS
Fig. 1. Block diagram of the complete designed divide-by-four circuit.
Gain [dB]
2
(1µm/80nm)
(32µm /80nm)
Fig. 2. Circuit schematic of the proposed regenerative frequency divider
6
4
(HVT)
M9
M10
M3A
operating region:
14GHz < fin/2 < 22GHz
LA=2nH
LB=2nH
RA=1.1kΩ
RB=1.1kΩ
QP
QM
0
DP
22GHz
14GHz
(2µm/80nm)
M1A
(2µm/80nm)
M1C
M1D
M1B
DM
-2
CP
-4
(2µm/80nm)
M2A
M2B
CM
-6
M3
VBIAS
10
10
(24µm /80nm)
Frequency [Hz]
Fig. 3. Simulated open loop band pass frequency response of the DFD showing the operating
region for the divided-by-two input frequency.
0 dBm
0.3
Input Amplitude [V]
Fig. 4. Circuit schematic of the CML-type TFF.
RBW:
100 kHz
10 dB
0.25
VBW:
100 kHz
1 MHz
0.2
0.15
0.1
Divide-by-four Divider(meas.)
Divide-by-four Divider(sim.)
Static Divider(meas.)
Static Divider(sim.)
0.05
0
10
20
30
Input Frequency [GHz]
40
Fig. 5. Measured and simulated minimum input amplitude curves of the divide-by-four and the
static divider.
10 GHz
Fig. 6. Measured output spectrum of the divide-by-four circuit with an input signal of 40 GHz.
1
fref
Dynamic
Divider
Static
Divider
PD
CP
LF
Output buffer
1
20µm
0.2
5
0.15
0
0.1
Input Power [dBm]
Differential Output Amplitude [V]
N
Fig. 8. Block diagram of a typical CMU.
Fig. 7. Chip micrograph of the divide-by-four circuit and the output buffer.
0.05
0
-0.05
-5
-10
-15
-20
-0.1
-25
-0.15
-0.2
2.28
fout
2.285
2.29
time [s]
2.295
-8
GND
Divide-by-four Divider
Static Divider
10
15
20
25
30
Input Frequency [GHz]
x 10
Fig. 9. Measured differential output signal of the divide-by-four circuit with a 40 GHz amplitude
of 0.4Vpp.
ibias_d
-30
2.3
Vdd
vim
Divide-by-four
circuit
vip
GND
fin,min
[GHz]
fin,max - fin,max fin,max − fin,m in Vdd
fcenter
Pdiv *)
[mW]
Technology Ref.
79GHz
26.6GHz
52.8GHz
0.99%
7.5V
532m
W
SiGe
[1]
27GHz
17.4GHz
9.6GHz
43%
1.8V
12mW
CMOS
L=0.13µm
[2]
38GHz
34.5GHz
3.5GHz
9.5%
1.8V
12mW
CMOS
L=0.13µm
[2]**)
40.6GHz
38.3GHz
2.3GHz
5.8%
2.5V
42mW
CMOS
L=0.18µm
[3]
41GHz
31GHz
10GHz
27%
1.2V
2.4mW
CMOS
L=80nm
This
Work
vom
CM
GND
ibias
Fig. 11. Full chip photo including pads of the divide-by-four circuit.
40
fin,max
[GHz]
vop
GND
35
Fig. 10. Measured input power sensitivity curves of the divide-by-four and the static divider.
*) Buffer not included;
**) Injection-locked ring oscillator
Fig. 12. Comparison of state-of-the-art regenerative frequency dividers.
2