Fully Parallel 6T-2MTJ Nonvolatile
TCAM with Single-Transistor-Based
Self Match-Line Discharge Control
Shoun Matsunaga1,2, Akira Katsumata2, Masanori Natsui1,2,
Shunsuke Fukami1,3, Tetsuo Endoh1,2,4, Hideo Ohno1,2,
and Takahiro Hanyu1,2
1
Center for Spintronics Integrated Systems, Tohoku University
2 Research Institute of Electrical Communication, Tohoku University
3 NEC Corporation
4 Center for Interdisciplinary Research, Tohoku University
Acknowledgment:
This research is supported by the Japan Society for the Promotion of
Science (JSPS) through its "Funding Program for World-Leading Innovative
R&D on Science and Technology (FIRST Program)."
Symposia on VLSI Technology and Circuits
June 17, 2011.
Outline
• Background & Purpose
• 6T-2MTJ-Based NV-TCAM Cell and Test Chip
Fabrication
• Design Example of Low-Power NV-TCAM
Using Three-Level Segmented Match-Line
Scheme
• Conclusions
Slide 1
Background
TCAM (Ternary Content-Addressable Memory)
Fully Parallel equality-search
High-speed pattern matching
Applications: Database, virus checker, network router, etc.
Demands: Large capacity, Low-power consumption
TCAM cell structure
Search word
1
1
0
0
0
X
SA
Miss
0
0
1
SA
Miss
0
X
X
SA
Miss
1
0
X
SA
Miss
1
1
0
SA
Hit
1
1
X
SA
Hit
Parallel Input
&Output
2-bit
volatile
storage
Comp.
Logic
Leakage
current
Problems:
Many device counts of TCAM cell
Large cell area
Increasing leakage current
High standby power
Purpose : Realize a compact and low-power TCAM
Slide 2
Merits of MTJ-Based Nonvolatile Logic-in-Memory
MTJ device
Hardware structure
Function
Storage
Logic
MTJ layer
CMOS layer
 Nonvolatile storage
 Perfectly cut off the
power supply.
 Low standby power
 3D-stacking structure  CMOS/MTJ-hybrid logic
 Greatly reduce area
 Merge storage and
overhead of storage.
logic functions.
 Compact
 More compact
Nonvolatile Logic-in-Memory structure is suitable
for a compact and low-standby-power TCAM.
Slide 3
Approaches for a Compact and Low-Power TCAM
 For Large Capacity (Small Cell Size)
 Utilize nonvolatile logic-in-memory
- 3D-stacking structure
Compact
- CMOS/MTJ-hybrid logic
( & Nonvolatile)
NV-TCAM cell
 For Low Power (with maintaining search speed)
 Eliminate wasted cell activation
 Power OFF at standby state using nonvolatility
Low active power
Low standby power
Match-line (ML)
SA
Large capacitive load
100% of activity  High Power
SA
Small load
(Fast)
Disabled
(Standby)
Decreased activity  Low Power
Miss
SA
Miss
Medium load
(Medium speed)
Total load is the same  Comparable speed
Slide 4
Outline
• Background & Purpose
• 6T-2MTJ-Based NV-TCAM Cell and Test Chip
Fabrication
• Design Example of Low-Power NV-TCAM
Using Three-Level Segmented Match-Line
Scheme
• Conclusions
Slide 5
Conventional TCAM Cell
Cell circuit
S
Truth table
S
Stored data
ML
Match
Line
Comparison
circuit
Mem.
Mem.
(b1)
(b2)
B
(b1, b2)
0
(0, 1)
1
GND
2-bit Volatile Mem. (SRAM cells)
Large cell size (16Tr. or 12Tr.)
High leakage
(1, 0)
X
Don’t
care
(0, 0)
Input
Matched
result
S
ML
0
1 (Hit)
1
0 (Miss)
0
0 (Miss)
1
1 (Hit)
0
1 (Hit)
Masked
1
ML = b1.S + b2.S
It is desirable to realize a compact and nonvolatile TCAM cell.
Slide 6
Proposed NV-TCAM Cell
6T-2MTJ NV-TCAM cell
WL1 SL(S)
ML
VDD
BIAS
Measured I-V char.
VCELL_H (Hit)
VCELL_L (Miss)
SL(S) WL2
ML voltage
Keeper
(Diode switch)
ICELL [µA]
120
“Miss”
100
Load
“Hit”
80
b 1 .S + b 2 .S
b1
∆VCELL
60
b2
(0.35V)
40
20
BL
BL
PMOS load
Nonvolatile storage
0
Comparison circuit
VCELL-H
VCELL-L
0
0.2
0.4
0.6
0.8
1.0
1.2
VCELL [V]
Slide 7
Mechanism of ML voltage keeper
Minimum voltage detection
VML
Match-line (ML)
ML
voltage
keeper
ML
voltage
keeper
VCELL
Comp.
Circuit
Comp.
Circuit
Comp.
Circuit
SA
OUT
VML is almost
the same as
minimum
voltage of
each VCELL.
VCELL_H (Hit)
1-bit cell
If Full-bit Hit  VML : H
If Miss
 VML : L
VCELL =
VCELL_L (Miss)
Easy to sense
Slide 8
Self Match-Line Discharge Control in Word Circuit
Full-bit Hit
VML > VCELL_H
H
H
ML is
precharged
to VDD.
ML
H
Miss
VML > VCELL_H
H
H
ML
M
GND
VML = VCELL_H
GND
VML = VCELL_H
ML
ML
M
GND
GND
VML
VDD
VCELL_H
VCELL_L
“Hit”
Slight
degradation ML voltage swing
“Miss”
VML
. V
. CELL_L
ML
GND
Time
Slide 9
Match-Line Voltage Swing
1-bit miss detection (worst case)
Hit
Hit
Reversed
current
VCELL-H VCELL-H
IDiode
Word
length
Hit
VCELL-H
Current into a
miss cell
(exponential scale)
Reversed current
from hit cells
(linear scale)
VML
VML
VCELL-L
Miss
logarithmic
scale
VML-H
ML voltage keeper
(Weak inversion)
VCELL-H
VML-L
VCELL-L
∆VML
Sufficient ML voltage swing can be obtained even in longer word circuit.
Slide 10
Fabricated NV-TCAM Test Chip
3.36 µm
2-kb
TCAM
cell array
174 µm
3.08 µm
Sense Amp.
Row Dec.
226 µm
Column Dec.
Fabricated
TCAM cell
Process
90 nm 1P5M
CMOS/MTJ
Cell structure
6T-2MTJ
MTJ size
100 nm x 200 nm
Cell size
10.35 µm2
Array
configuration
32bits x 64words
Match delay
0.29 ns
Supply voltage
1.2 V
Slide 11
Match-line voltage swing [V]
Match-Line Voltage Swings (Simulated and Measured)
0.5
Logarithmically
degraded
MRR=400%
MRR=250%
0.4
MRR=172%
Easy
to
detect
(Typical)
MRR=172%
0.3
(10%∆Vth, 10%∆MRR)
MRR=100%
0.2
Measured ∆VML : 0.23V@32bits
0.1
Criterion for sufficient
voltage swing
Estimated ∆VML : 0.19V@144bits
0
1
2
4
8
16
32
64
128
256
Word length [bit]
Sufficient match-line voltage swing is obtained.
Slide 12
Chip Measurements
RAP – RP
MRR =
x 100
RP
RMTJ [kΩ]
P : Precharge
E : Evaluate
Voltages
CLK
3.5
RAP = 3.0 kΩ
3
2.5
2
P
E
P
1.2V
= 172%
E
100ns
SL
Input
key
1
0
OUT
Hit
Miss
1.5
1
RP = 1.1 kΩ
0.5
-400
-200
0
IMTJ [µA]
200
400
Time
Basic behaviors of the fabricated MTJ device and NV-TCAM
have been successfully confirmed.
Slide 13
Measured Waveforms of Instant-ON/OFF
VDD
Power
OFF
Power
OFF
Power
OFF
Power
OFF
1.2V
Voltages
Power
OFF
1µs
CLK
SL
The same
output
1
1
0
The same
output
0
Input
key
OUT
Hit
Hit
Miss
Miss
Time
Instant ON/OFF of the fabricated chip has been successfully confirmed.
Slide 14
Outline
• Background & Purpose
• 6T-2MTJ-Based NV-TCAM Cell and Test Chip
Fabrication
• Design Example of Low-Power NV-TCAM
Using Three-Level Segmented Match-Line
Scheme
• Conclusions
Slide 15
Approach for Low-Power NV-TCAM
Three-Level Segmented Match-Line Scheme
1st segment
2nd segment
SA
SA
SA
SA
SA
DisabledSA
Miss cell
3rd segment
SA
Hit
Disabled
SA
Miss
Disabled
SA
Miss
Hit cell
If current segment is “Miss,” then next segment is disabled.
Decreased activity rate
Low-Power
Slide 16
Image of Cell Array Activity
(1 - pi)m
Miss
(Active)
Disabled
(Inactive)
pi m
m-word x n-bit cell array
i bits
j bits
n - i - j bits
Hit
(Active)
Miss (Active)
Hit (Active)
Most words are “Miss”
Hit probability of cell (p):
2/3 (using masked bit)
1/2 (not using masked bit)
Disabled
(Inactive)
Miss
Enabled (Active)
Hit
Ultra Low Activity
Slide 17
Cell Activity Rate
Minimum activity rate
@ 1st 3-bit / 2nd 7-bit
segmentation
Activity rate
of cells [%]
9
8
7
6
5
4
3
2
10
8
6
2.8%
4
1
2
W
2n ord
d
se len
gm gth
en of
t[
bit
]
3
2
4
5
0
8
6
7
6
5
4
3
2
f 1st segment
[bit]
Word length o
7
1
8
Slide 18
Performance Evaluations
Array structure
144-bit x 256-word
Cell activity [%]
2.8
1.04
Search energy [fJ/bit/search]
Standby power
[W]
(Comparable to CMOS-based TCAM
within a few fJ/bit/search)
Sleep mode
0 (@Power-OFF)
Search mode
Negligible (@2.8% activity)
HSPICE simulation under a 90nm CMOS technology @1.2V
Low-standby-power nonvolatile TCAM is successfully realized
under comparable search energy with CMOS-based one.
Slide 19
Outline
• Background & Purpose
• 6T-2MTJ-Based NV-TCAM Cell and Test Chip
Fabrication
• Design Example of Low-Power NV-TCAM
Using Three-Level Segmented Match-Line
Scheme
• Conclusions
Slide 20
Conclusions
We have proposed and demonstrated 6T-2MTJ-based
fully-parallel NV-TCAM.
Cell Circuit Techniques:
- Fewest transistor counts with nonvolatility
- Bit-parallel equality-search capability in a long word
based on 1-transistor ML voltage keeper array
Word Circuit Techniques:
- Eliminate wasted cell activation based on three-level
segmented match-line scheme
 Negligible standby power under comparable search
energy with CMOS-based TCAM
Slide 21