THICK-GATE-OXIDE MOS STRUCTURES
WITH SUB-DESIGN-RULE CHANNEL LENGTHS
FOR DIGITAL AND RADIO FREQUENCY CIRCUIT APPLICATIONS
By
HAIFENG XU
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
2007
1
 2007 Haifeng Xu
2
To my parents and my wife
3
ACKNOWLEDGMENTS
I want to express my deep gratitude and appreciation to my advisor, Professor Kenneth K.
O, for his patient, constant encouragement and devotion. He guided me through the transition
from a student to an electrical engineer. Under his supervision, I had opportunities to work in
microelectronics, which eventually became a joy for me. Also much appreciation goes to Professor Rizwan Bashirullah, Professor Huikai Xie and Professor Oscar D. Crisalle for their helpful
suggestions to my research. I would like to thank them for their interests in this work and serving
on my Ph.D. supervisory committee.
I would like to thank all the former and current colleagues in the SiMICS research group
for their helpful discussions, advice and friendship. Some names are listed here: Chikuang Yu,
Xiaoling Guo, Brian Floyd, Chih-Ming Hung, Feng-Jung Huang, Kihong Kim, Yochuol Ho,
Namkyu Park, Xi Li, Zhenbiao Li, Seong-Mo Yim, Dong-Jun Yang, Narasimhan Trichy Rajagopal, Ran Li, Tod Dickson, Jason Branch, James Caserta, Wayne Bomstad, Jose Bohorquez,
Aravind Sugavanam, Jie Chen, Jau-Jr Lin, Li Gao, Changhua Cao, Yanping Ding, Yu Su,
Eun-Young Seok, Kwang-Chun Jung, Swaminathan Sankaran, Hsin-ta Wu, Chuying Mao, Ning
Zhang, Seon-Ho Hwang, Nallani Shashank Kiron, Myoung Hwan Hwang, Zhe Wang, Wuttichai
Lerdsitsomboon, Dongha Shim, and Kyujin Oh.
Finally, I am grateful to my parents, my sister and her family. At last, but not least, I want
to thank my wife for her love, patience, encouragement and tolerance. She has been beside me
every single day, bright or dark. I can not imagine walking through all these days without her
companionship.
4
TABLE OF CONTENTS
page
ACKNOWLEDGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CHAPTER
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.1 CMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.1.1 History of CMOS Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.1.2 From Digital to Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.2 Transistor Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.2.1 Transistor Scaling Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.2.2 Issues for Transistor Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3 Thick-Gate-Oxide MOS Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.5 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.6 Overview of the Dissertation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2 HIGH-TO-LOW LEVEL SHIFTER APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2 Sub-Design-Rule (SDR) MOS Transistor Structure . . . . . . . . . . . . . . . . . . . . . . . 32
2.3 DC Characteristics of SDR MOS Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.3.1 Current Drive Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.3.2 Voltage Handling Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3.3 Optimization of MOS Transistors for Level Shifter Application . . . . . . . . 38
2.4 Capacitance Property of SDR-26 MOS Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.5 High-to-low Level Shifter Speed Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3 LOW-TO-HIGH LEVEL SHIFTER APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.2 Composite MOS Transistor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3 Composite MOS Transistors in a 0.18-µm Process . . . . . . . . . . . . . . . . . . . . . . . . 53
3.3.1 Current and Breakdown Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.3.2 Subthreshold Current Leakage Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.4 Composite MOS Transistors in a 0.13-µm Process . . . . . . . . . . . . . . . . . . . . . . . . 60
5
3.5
3.6
3.7
3.8
4
3.4.1 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.4.2 Voltage Handling Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Composite MOS Transistor Capacitance Property . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Composite-22 MOS Transistors for Level Shifter Application . . . . . . . . . . . . . . . . . . 68
Low-to-high Level Shifter Speed Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
RADIO FREQUENCY POWER AMPLIFIER APPLICATION . . . . . . . . . . . . . . . . . . . . . 76
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.1.1 CMOS RF Power Amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.1.2 Classification of CMOS RF Power Amplifiers . . . . . . . . . . . . . . . . . . . . . . 77
4.1.3 Thick-Gate-Oxide MOS Transistors in Linear Power Amplifiers. . . . . . . . 78
4.2 AC Characteristics of Composite-22 MOS Transistor . . . . . . . . . . . . . . . . . . . . . . . . 79
4.2.1 fT and fmax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.2.2 Measurements for fT and fmax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5 TRANSMIT/RECEIVE SWITCH APPLICATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.1.1 CMOS Transmit/Receive Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.1.2 Techniques to Improve Power Handling Capability . . . . . . . . . . . . . . . . . . 90
5.2 CMOS T/R Switches Using Sub-Design-Rule Transistors . . . . . . . . . . . . . . . . . . . . . 91
5.2.1 Design of SDR T/R Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.2.2 900-MHz SDR T/R Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.2.3 2.4-GHz SDR T/R Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6 HIGH-Q MOS VARACTOR APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.1.1 CMOS Voltage-Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.1.2 MOS Varactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.1.3 Sub-Design-Rule MOS Varactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.2 High Frequency Characteristics of SDR MOS Varactors . . . . . . . . . . . . . . . . . . . . . 117
6.2.1 Device Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.2.2 Measurements and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
7
SUMMARY AND SUGGESTION FOR FUTURE WORK . . . . . . . . . . . . . . . . . . . . . . . . 123
7.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.2 Suggestion for Future Work. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.2.1 Application in high power T/R switches . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.2.2 Application in high-Q varactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6
APPENDIX
MODEL FILE FOR SDR-26 MOS TRANSISTORS . . . . . . . . . . . . . . . . . . . . 129
LIST OF REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
BIOGRAPHICAL SKETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7
LIST OF TABLES
Table
page
1-1
Scaling strategies for CMOS transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1-2
Two types of transistors available in a standard CMOS technology . . . . . . . . . . . . . . . . . 25
2-1
Breakdown voltages of sub-design-rule MOS transistors . . . . . . . . . . . . . . . . . . . . . . . . . 37
2-2
Speed performance of level shifters using the SDR-26 and conventional 3.3-V MOS
transistors as the drive transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3-1
Breakdown voltages and threshold voltages for the composite-18, and the conventional
3.3-V and 1.8-V MOS transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3-2
Measured threshold voltages of the composite transistors, and the conventional 1.2-V,
3.3-V transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3-3
Breakdown voltages for the composite transistors, and the conventional 3.3-V and 1.2-V
transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3-4
Speed performance comparison of level shifters using the composite-22 and conventional 3.3-V MOS transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5-1
Performance summary of CMOS T/R switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8
LIST OF FIGURES
Figure
page
1-1
First MOSFET structure proposed in 1928 from Lilienfeld’s US patent application.. . . . 16
1-2
Illustration of MOSFET scaling proposed in Dennard’s paper. . . . . . . . . . . . . . . . . . . . . 17
1-3
Typical floorplan for the mixed-signal system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1-4
Scaling parameters in CMOS transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2-1
Low-to-high and high-to-low level shifters (LS) used as the interface circuits along the
paths between the circuits with different signaling levels. . . . . . . . . . . . . . . . . . . . . . . . . 30
2-2
Typical high-to-low level shifter, using 3.3-V drive transistors at the interface between
3.3-V and 1.8-V circuitries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2-3
Cross-section of the sub-design-rule (SDR) MOS structure.. . . . . . . . . . . . . . . . . . . . . . . 33
2-4
Test structure layout of a set of SDR MOS transistors for DC measurements. . . . . . . . . . 34
2-5
Normalized ID-VGS for different SDR MOS transistors at VDS = 1.8 V. . . . . . . . . . . . . . 35
2-6
Measured threshold voltages of SDR MOS transistors with different channel lengths. . . 36
2-7
Comparison of normalized ID-VDS between SDR-26 and conventional 3.3-V MOS
transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2-8
Comparison of normalize ID-VGS between SDR-26 and conventional 3.3-V MOS
transistors in both linear and logarithm scales, when VDS = 1.8 and 0.05 V. . . . . . . . . . . 40
2-9
Simulated gate capacitance of longer channel 3.3-V MOS transistors, and extrapolated
gate capacitance of SDR-26 MOS transistors.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2-10 Simulated ID-VDS and ID-VGS curves of the SDR-26 and 3.3-V MOS transistors. The
simulations also match the measured currents for both types of transistors. . . . . . . . . . . . 43
2-11 Schematics of level shifter circuits in simulation. Version A uses conventional MOS
transistors as drive transistors, while Version B uses SDR-26 MOS transistors. . . . . . . . 44
2-12 Comparison of the SDR-26 and conventional 3.3-V MOS transistors used as the drive
transistors in 3.3-to-1.8-V level shifters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3-1
Typical low-to-high level shifter, using thick-gate-oxide drive transistors at the interface
between low-VDD and high-VDD circuitries.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9
3-2
Layout of the composite MOS transistor. Only 2 cells are shown here. . . . . . . . . . . . . . . 51
3-3
Cross-section of the composite MOS transistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3-4
Equivalent schematics of the composite MOS transistor. . . . . . . . . . . . . . . . . . . . . . . . . . 53
3-5
Test structure layout of the composite-18, conventional 3.3-V thick-oxide and
conventional 1.8-V thin-oxide MOS transistors for DC measurements. . . . . . . . . . . . . . . 54
3-6
Normalized ID-VDS of the composite-18, conventional 3.3-V thick-oxide and
conventional 1.8-V thin-oxide MOS transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3-7
ID-VGS curves in a logarithm scale for the composite-18, conventional 3.3-V and 1.8-V
MOS transistors with VDS = 0.05 V and VDD (1.8/3.3 V). . . . . . . . . . . . . . . . . . . . . . . . . 56
3-8
Illustration of source current matching between (A) the composite-18 transistors and (B)
the conventional 1.8-V MOS transistors.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3-9
Calculation of the voltage at the shared diffusion region (VM(a)) by using source current
matching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3-10 Test structure layout of a group of the composite MOS transistors for DC measurements. 61
3-11 Normalized ID-VGS plots for the composite and the conventional 3.3-V transistors with
VDS = 3.3 V, and the conventional 1.2-V transistor with VDS =1.2 V.. . . . . . . . . . . . . . . 62
3-12 Layout of the AC test structures for the composite MOS transistor and the open
structure.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3-13 Measured gate capacitance of the composite transistors with different lengths of SDR
sub-transistors, compared to those of the conventional 1.2-V and 3.3-V transistors. . . . . 67
3-14 ID-VDS characteristics of the composite-22, conventional 3.3-V and 1.2-V MOS
transistors when gate capacitances (Cgg) are the same. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3-15 Comparison of ID-VGS curves for the composite-22 and conventional 3.3-V MOS
transistors in linear and logarithm scales at fixed gate capacitance. . . . . . . . . . . . . . . . . . 70
3-16 Schematics of level shifter circuits in simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3-17 Comparison of the composite-22 and conventional 3.3-V MOS transistors used in 3.3to-1.8-V level shifters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4-1
Simplified block diagram of a typical RF transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4-2
Small-signal lumped microwave network model of a MOSFET. . . . . . . . . . . . . . . . . . . . 79
10
4-3
Measured current gain (h21), maximum available gain (MAG) and unilateral power gain
(Gmax) for the composite-22 and conventional 3.3-V thick-gate-oxide transistors.a . . . . 83
4-4
fT and fmax for the composite-22 MOS transistor and conventional 3.3-V thick-gateoxide transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4-5
gm, output resistance (ro) and intrinsic gain of the composite-22 and conventional 3.3V/1.2-V transistors when the overdrives (VGS-VT) are around 0.25 V. . . . . . . . . . . . . . . 85
5-1
T/R switch in a typical TDD RF transceiver.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5-2
Simplified schematic of the T/R switch with 3-stack sub-design-rule (SDR) length
transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5-3
Cross-section of the 3-stack transistors in the SDR T/R switch. . . . . . . . . . . . . . . . . . . . . 93
5-4
Detailed schematic of the 3-stack transistors (M1-M3) including the parasitic shunt
paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5-5
Voltage distributions for the 3-stack SDR switches with and without the feed-forward
capacitors, when the input power is 30 dBm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5-6
Impact of feed-forward capacitance (0X, 1X, 2X and 3X) on the peak voltages across
transistors M1-M3 (VDG1p~VDG3p, VSG1p~VSG3p). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5-7
Die photo of the 3-stack SDR T/R switch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5-8
Measured insertion loss of the SDR switch using 3 stack SDR transistors, compared to
that of the switch using 2 stack 0.34-mm length transistors. . . . . . . . . . . . . . . . . . . . . . . 100
5-9
Measured isolation and return loss for the SDR T/R switch using 3 stack SDR channel
length transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5-10 Linearity measurement results of the 3-stack SDR switch with source/drain biased at 3
and 0 V, and with (1X) and without the feed-forward capacitors.. . . . . . . . . . . . . . . . . . 101
5-11 Simplified schematic of the T/R switch for 2.4-GHz applications using 2-stack SDR
transistors without feed-forward capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5-12 Die photo of the T/R switch for 2.4-GHz applications using 2-stack SDR transistors
without feed-forward capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5-13 Measured insertion loss and isolation of the 2-stack SDR switch for 2.4-GHz
applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5-14 IP1dB measurement of the 2-stack SDR switch working at 2.4 GHz. . . . . . . . . . . . . . . . 104
11
5-15 Detail of linearity measurement results around 1-dB compression point for the 3-stack
SDR switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5-16 Measured DC current through the n-p-n-p sandwich structure from source/drain,
through body to p-substrate.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5-17 Measured breakdown characteristics of a single SDR transistor. . . . . . . . . . . . . . . . . . . 108
6-1
Schematic of a typical differential CMOS voltage-controlled oscillator. . . . . . . . . . . . . 112
6-2
Cross-section of MOS varactor structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6-3
Layout and equivalent circuit model of a MOS varactor. . . . . . . . . . . . . . . . . . . . . . . . . 117
6-4
C-V and Q-V characteristics of the thick-gate-oxide (TK) and thin-gate-oxide (TN)
varactors with L = 0.24 µm.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6-5
Measurement data of Qmin and γ vs channel length for thick-gate-oxide (TK) and thingate-oxide (TN) varactors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6-6
Varactor design space formed by Qmin and tuning range γ. . . . . . . . . . . . . . . . . . . . . . . 121
7-1
Additional nodes to connect feedforward capacitors in a 4-transistor stack of SDR T/R
switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7-2
Spacing between poly gate and diffusion connections in MOS varactor structures. . . . . 128
12
Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy
THICK-GATE-OXIDE MOS STRUCTURES
WITH SUB-DESIGN-RULE CHANNEL LENGTHS
FOR DIGITAL AND RADIO FREQUENCY CIRCUIT APPLICATIONS
By
Haifeng Xu
August 2007
Chair: Kenneth K. O
Major: Electrical and Computer Engineering
The potential digital and radio frequency (RF) applications and advantages of
thick-gate-oxide metal-oxide-semiconductor (MOS) structures with sub-design-rule (SDR) channel lengths in standard complementary MOS (CMOS) technologies are investigated. This is a
low-cost solution for scaling down thick-gate-oxide transistors, which does not require any modifications to the existing foundry technologies. This concept provides a new perspective to the
down-scaling of thick-gate-oxide transistors.
The maximum drain voltage for the drive transistors with a thick-gate oxide of
3.3-to-1.8-V level shift circuits in 0.18-µm CMOS processes is 1.8 V. The drain current is
increased by reducing the gate length to 0.26 from 0.35 µm. Measurements show the SDR MOS
transistor has sufficient drain-to-source breakdown voltage for 1.8-V operation. At the same gate
capacitance, the SDR transistor delivers more than 1.6 times the drain current of the conventional
thick-gate-oxide transistor. Simulations indicate the propagation delay of 3.3-to-1.8-V level shift
circuits can be reduced by 20% without process modifications. Then, for the first time, we proposed a composite MOS transistor structure by combining a 0.12-µm long thin-gate-oxide transistor with a 0.22-µm long thick-gate-oxide (SDR) transistor in a 0.13-µm CMOS process. The
composite transistor has more than 2 times the drain current of the conventional thick-oxide transistor, while having the same breakdown voltage. 3.3-V I/O transistors with better combination of
drive current, threshold voltage and breakdown voltage are realized in conventional CMOS technologies without process modifications. Simulations suggest that 40% reduction in the propagation delay for a 1.2-to-3.3-V level shifter is expected.
The concept of SDR transistors can also be used to improve the performance of RF/analog
circuits. Measurements show that the composite MOS transistor has higher fT and fmax than the
3.3-V transistor when VGS is below 1.2 V. If the VGS-VT is set to ~ 0.25 V in a practical bias condition for linear power amplifiers, fT of the composite transistor is 15 GHz and 20% higher than
that of the 3.3-V transistor. This characteristics can potentially improve RF power amplifier gain
and power efficiency.
Using 3-stack thick-gate-oxide transistors with a 0.26-µm SDR channel length, a
31.3-dBm 900-MHz bulk CMOS transmit/receive (T/R) switch with insertion losses of 0.5 and
1.0 dB in transmit (TX) and receive (RX) modes has been successfully demonstrated. The effects
of feedforward capacitance in the switch are analyzed. Through another 28-dBm T/R switch operating at 2.4 GHz with IL of 0.8/1.2 dB in TX/RX modes, it is demonstrated that 2-stack configuration can be used to trade-off IP1dB for better loss performance. It is suggested that integration of
a bulk CMOS T/R switch for cellular applications is a realizable goal by using thick-gate-oxide
SDR MOS transistors. Lastly, the use of the SDR MOS structures as varactors in VCO circuits is
investigated. This study shows that Qmin of SDR varactors at 24 GHz is 5 times that of
thin-gate-oxide structures. The varactor tuning range (γ) is decreased from ~ 65% to ~ 40%. Its
application for 50-GHz narrow tuning range VCOs with better power consumption and phase
noise performance is projected.
14
CHAPTER 1
INTRODUCTION
Thick-gate-oxide metal-oxide-semiconductor (MOS) transistors in addition to
thin-gate-oxide high performance MOS transistors are commonly used in standard complementary MOS (CMOS) processes. Their high breakdown voltage and low off-current are preferred in
many applications. This study is interested in further scaling down the thick-gate-oxide MOS
transistors and exploiting this further scaled devices in both digital and analog circuit designs.
Since this study is related to scaling, the evolution and development trend of CMOS technology is an excellent place to start with.
1.1 CMOS Technology
1.1.1 History of CMOS Transistors
The concept of MOSFETs (metal-oxide-semiconductor field-effect transistors) was first
proposed as early as 1928 by Julius Edgar Lilienfeld in his US patent (Figure 1-1) [Lil28]. The
conductivity between the S node (source) and D node (drain) can be modulated by the transverse
electric field applied through the G (gate). Unfortunately, this idea did not become practical until
1958 when the thermally grown oxide were developed by Atalla to reduce the surface state density and solve the electrical instability of the MOS transistors [Ata59].
Building on these and others, Kahng and Atalla successfully developed the first modern
MOSFET in 1960. Their structure was very similar to that of modern MOS transistors, and consisted of a thermally grown gate-oxide layer over an n-type inversion channel between two n+/p
junctions on a p-type silicon substrate [Kah60, Kah76]. About the same time, Kilby and Noyce
separately invented the monolithic integrated circuit (IC) concept [Kil76, Noy61]. This technol-
15
Cu2S
S
D
Al2O3
Al
G
S
D
G
Figure 1-1.
First MOSFET structure proposed in 1928 from Lilienfeld’s US patent
application.
ogy laid the foundation for the development of ICs, initially using BJTs (bipolar junction transistors), then using MOSFETs [Sah88].
A major breakthrough in IC technology occurred when a CMOS (complementary
metal-oxide-semiconductor) inverter circuit was invented by Frank Wanlass and Chih-Tang Sah
in 1963 [Wanl63]. In CMOS technology, both n-type and p-type MOSFETs are fabricated in the
same silicon chip, and the circuits using CMOS logic has almost zero static power consumption.
CMOS integrated circuits became successful in many then-advanced electronic products because
of low overall power consumption and prolonged battery life time. In 1968, Noyce and Moore
started a MOS integrated circuit manufacturing company (Intel), leading to volume production in
1970. A new era of CMOS integrated circuit production has been opened.
Probably one of the most influential techniques on MOSFET design was proposed by
Dennard and co-researchers around 1973 [Den74]. They presented the way to reduce the transis-
16
L’ = L/k
tox’ = tox/k
Vds’= Vds/k
NA’ = kNA
k =5
A
Figure 1-2.
B
Illustration of MOSFET scaling proposed in Dennard’s paper. (A)
State-of-the-art MOSFET structure. (B) Down-scaled MOSFET structure
following the scaling law.
tor dimensions without compromising the current-voltage characteristics. This has been known as
the scaling law of MOSFETs (illustrated in Figure 1-2). Compared to bipolar devices, CMOS
transistors are relatively easy to fabricate. The ability to scale makes CMOS technology even
more attractive. Engineers and researchers have been able to scale down the feature size and push
CMOS technology forward. The channel length of MOSFETs has decreased from several micron
meters in Dennard’s time, to submicron, and to nano-meters nowadays.
Since its first use in commercial products, CMOS technology has been growing very fast.
Just tracing back to year 1982, for example, integrated circuits manufactured using CMOS processes were only 12% of the market including BJT, BiCMOS, NMOS, PMOS, TTL and other
technologies. However, this percentage almost reversed by the year 2003. The share of CMOS
technology jumped to 82% [Vee03]. Considering the fact that the whole IC market had increased
from $10.2B to $175B during the same period, the growth of CMOS technologies is indeed amazing.
17
1.1.2 From Digital to Analog
Scaling is one remarkable feature of CMOS technology. When the dimensions are
reduced, MOS transistors can achieve higher speed performance due to lower capacitance, lower
supply voltage and higher drive current. By reducing the transistor size, more functions can be
integrated in the same chip area, and the cost of the same functionality is decreased. Additionally,
CMOS gates have low power consumption. Power is dissipated only during switching of the circuit. This allows hundreds of millions of CMOS transistors to be integrated on a single silicon
chip before the heat management becomes problematic. CMOS technology is the dominant one in
VLSI production today, and its advance will remain the primary driving force for the IC industry.
RF (radio frequency) and analog circuits were traditionally fabricated using bipolar transistors due to its higher transconductance, better matching, lower noise and higher speed. Meanwhile MOS transistors have been steadily scaled down and this has improved the speed of MOS
transistors. As a matter of fact, the intrinsic speed of MOS transistors has been increased by more
than three orders of magnitude in the past 30 years and becomes comparable to that of bipolar
counterparts. This has enabled use of CMOS technology for RF applications. With the modest
transistor performance, CMOS technology has the advantage that both analog and complex digital
circuits can be inexpensively integrated into the same silicon chip. Analog/mixed signal CMOS
circuit design is under rapid development, including RF applications [HuaQ98, Abi04]. It is the
clear trend today to use CMOS digital circuits combined with CMOS analog circuits whenever
possible because of the higher level of integration and low cost, thus providing highly reliable
SoC (system-on-chip) solutions, as illustrated in Figure 1-3 [Sin99].
18
Low amplitude
analogue circuits
Medium amplitude
analogue circuits
High amplitude
analogue circuits
p+ Guard Ring
Low speed
digital circuits
High speed
digital circuits
Digital output
buffers
Figure 1-3.
Typical floorplan for the mixed-signal system design.
1.2 Transistor Scaling
1.2.1 Transistor Scaling Guidelines
CMOS technology evolution has followed the path of scaling down for pursuing higher
speed, higher integration, lower power consumption and lower cost. However, the progress of
scaling is not arbitrary even if allowed by the lithography. The short channel effect (SCE) which
leads to the decrease of the threshold voltage is an undesirable aspect of scaling and should be
controlled with the help of advancement in device design and process technology. Therefore, certain design guidelines are always followed. There are two methods often mentioned:
✦ constant-field scaling
✦ constant-voltage scaling
In the first scaling scenario, both horizontal and vertical dimensions in Figure 1-4, such as
channel length L, width W, gate thickness tox, junction depth Xj, etc., are proportionally scaled
down by a factor of k. At the same time, it is required to decrease the applied voltage (VDD) and
19
VDD
Gate
n+ source
tox
Wdm
n+ drain
xj
WD
L
p-substrate, NA
Figure 1-4.
Scaling parameters in CMOS transistors.
increase the doping concentration (NA or ND) by the same factor. The maximum drain depletion
width (WD in Figure 1-4), given by
WD =
2ε si ( ψ bi + V DD )
2ε si V DD
V DD 1
---------------------------------------- ≈ -------------------- ∝ ---------- ∝ --- ,
k
qN A
qN A
NA
(1-1)
is also scaled down approximately by k. The key point in this scenario is that the electric field (E)
remains unchanged by the scaling, so that the reliability of scaled CMOS transistors is no worse
than that of the original device. This concept is illustrated in Figure 1-2 and the scaling rules for
device and circuit parameters are specified in Table 1-1.
For the constant-field scaling, the drift current (ID) decreases by a factor k. Interestingly,
the circuit delay (τ ∼ CVDD/ID) is still improved by k because the capacitance (C ~ WL/tox) and
the voltage are scaled down by a factor of k2 in total. Moreover the power density (~ P/WL) is
kept the same. This means that, by following the constant-field scaling, the circuits can speed up
by the same factor while maintaining the power density of the silicon chip.
20
Table 1-1. Scaling strategies for CMOS transistors
Parameters
constant-E
scaling factor
(k>1)
constant-V
scaling factor
(k>1)
generalized
scaling factor
(1<α<k)
Dimension (L,W, tox, Xj, etc.)
1/k
1/k
1/k
Doping concentration (NA, ND)
k
k2
αk
Voltage (VDD)
1/k
1
α/k
E-field (~ VDD/tox)
1
k
α
Depletion-layer width (Wd)
1/k
1/k
1/k
Capacitance (C ~ WL/tox)
1/k
1/k
1/k
Drift current (ID ~ WVDD2/Ltox)
1/k
k
α2/k
Drift current per width (~ ID/W)
1
k2
α2
Channel resistance (Ron ~ VDD/ID)
1
1/k
1/α
Circuit delay (τ ~ CVDD/ID)
1/k
1/k2
1/αk
Power per circuit (P ~ VDDID)
1/k2
k
α3/k2
Circuit density (~ 1/WL)
k2
k2
k2
Power density (~ P/WL)
1
k3
α3
Under the second scaling scheme (constant-voltage scaling), the MOS transistor’s horizontal and vertical dimensions again are scaled down by k. Different from the last scenario, the
applied voltage in this case remains the same, thus the electric field has to be increased by k. The
maximum channel depletion width (Wdm in Figure 1-4) is expressed as
W dm =
4ε si kT ln ( N a ⁄ n i )
4ε si kT ( const )
1 ∝ 1--- .
------------------------------------------ ≈ ----------------------------------- ∝ ------2
2
NA k
q NA
q NA
(1-2)
To assure that the maximum channel depletion width (Wdm) and the maximum drain depletion
width (WD) in Equation 1-1 are scaled down by factor of k, the doping concentration (NA or ND)
21
should be increased by k2. The constant-voltage scaling rules for device and circuit parameters are
also listed in Table 1-1.
Under the constant-voltage strategy, the drift current is increased by k. Consequently, the
circuit delay is improved even faster (by k2). However, the benefit is countered by the drastic
increase of power density by a factor of k3. Even worse, scaling up electric field may cause
hot-carrier and oxide reliability problems in the scaled MOS transistors.
The constant-field scaling is a clear and simple approach to the design of scaled MOS
transistors. However, the requirement of reducing the voltage by the same factor as the device
physical dimension is too conservative. Because of certain non-scalable effects and reluctance to
depart from the standardized voltage levels of the previous generations, the supply voltage is seldom scaled in proportion to the channel length. Actually, the electric field has been gradually rising over the generations rather than staying constant [Cha01]. On the other hand, the
constant-voltage scaling scheme puts a very loose constraint on the electric field and allows it to
increase by the same factor as the dimensions are scaled down. The performance can be improved
fast. However, the MOS transistor is no longer reliable and the circuit heating becomes unmanageable.
In reality, CMOS technology development has followed the steps between the constant-field scaling and the constant-voltage scaling. This mixed scaling method is expressed as the
generalized scaling in Table 1-1. When the device dimensions are reduced by k, the electric field
is allowed to scale up by a smaller factor α (1<α<k) rather than k. The applied voltage and the
power density are scaled to α/k (< 1) and α3 (< k3), respectively. The generalized scaling can
relieve the reliability problems and alleviate the severeness of the package heat removal problem.
22
1.2.2 Issues for Transistor Scaling
Even though the CMOS scaling guidelines discussed above have served the industry well,
there are some non-scalable effects that are not taken into account and make the scaling guidelines
impractical sometimes.
To keep improving the speed performance of MOS transistors, an important assumption
implicitly used is that the threshold voltage (VT) can be always scaled down together with the
supply voltage (VDD) so that sufficient VDD/VT ratio is maintained. However, the off current (Ioff)
will exponentially increase when the threshold voltage VT is scale down, as given by
W
kT 2 –( qVT ) ⁄ ( mkT )
I off = u o C ox ----- ( m – 1 )  ------- e
,
 q
L
(1-3)
3t ox
where m is 1 + ----------, representing the efficiency that the gate controls the inversion layer. FundaW dm
kT
mentally, the thermal voltage ------- is non-scalable with the process parameters. The off current
q
(Ioff), therefore, will increase beyond the reasonable limit if there is no compromise in VDD/VT
ratio, i.e., slowing down the scaling of threshold voltage.
The off current directly contributes to the static power consumption of the chip. Even
though the latter is only a small fraction of the total power dissipation nowadays, it is expected to
become more problematic for future technologies when the CMOS technology is further scaled
down and the number of transistors per chip is increased.
Over the last decade, many techniques have been reported to reduce the static power dissipation in VLSI. Among those, the multi-threshold CMOS transistor and variable threshold CMOS
transistor are promising techniques to reduce the static power while maintaining high performance in active mode [McP00, YamT00]. The basic idea is to use lower-VT MOS transistors
along the critical signal paths for high speed and higher-VT MOS transistor in the non-critical por-
23
tion of the same chip without affecting the high performance portion. For one CMOS process,
these types of transistors with different threshold voltages can be achieved in several ways
[Ani03].
✦ Body effect (VSB): Change the threshold voltage by applying different biases at the
body of MOS transistors. Control signals at the body nodes are required. Changing VT
is less efficient because VT is proportional to the square root of VSB.
✦ Ion implantation (Na): Extra process steps are needed. Both process complexity and
cost are increased. It is an efficient way to adjust VT and already widely used in existing CMOS processes [Wei00].
✦ Different channel lengths (L): Scale down the MOS transistor further and intentionally introduce more short channel effect to lower the VT. Scaling should be carefully
designed and controlled.
✦ Multiple oxide thicknesses (tox): Transistors with different gate-oxide thicknesses can
be fabricated in the same wafer. This technique complicates the process, but the
higher gate-oxide thickness for high-VT MOS transistor can reduce the gate capacitance and suppress both the dynamic and static power dissipation [Che95, O95,
Ima00, Tho01].
1.3 Thick-Gate-Oxide MOS Transistor
As to the multiple oxide thickness technique, dual-gate-thickness CMOS processes are the
most commonly used approach. Two different thicknesses of gate-oxide-layers can be fabricated
in the same process. The thin-gate-oxide MOS transistors are optimized to take full advantage of
the process parameters (physical dimension, doping profile, etc.) and operate at the highest possible speed. Due to smaller dimensions, the voltage swings they can tolerate at the gate and drain
nodes are lower. On the contrary, the thick-gate-oxide MOS transistors also have larger horizontal
dimension in addition to the thicker gate-oxide-layer. Its speed performance is not as good as that
of the thin-gate-oxide transistors due to the longer channel length, while they have much lower
leakage current and are able to handle higher voltage swings at the gate and drain.
24
Table 1-2. Two types of transistors available in a standard CMOS technology
Parameters
Thin-oxide
transistor
Thick-oxide
transistor
Gate thickness (nm)
4.5
6.8
Minimum channel length
specified in design rule (µm)
0.18
0.35
Gate voltage (V)
1.8
3.3
Drain voltage (V)
1.8
3.3
With the continuous scaling of thin-oxide MOS transistors, the thick-oxide MOS transistors became part of the standard offering from the CMOS foundries. In a 0.18-µm CMOS foundry
technology, for instance, both the thin-oxide transistor and the thick-oxide transistor are available.
Compared in Table 1-2 are the dimensions and applied voltages of the two types of transistors.
Including the thick-gate-oxide MOS transistor as the standard offering of CMOS technology, of course, increases the process complexity, and in turn the cost of chip fabrication. However,
several reasons make the efforts worthwhile in modern CMOS technologies.
The first one among them, as discussed in Section 1.2.2, is that the thick-gate-oxide transistors can be used as the sleep transistors to disable the core circuits, therefore providing a technique to effectively control the circuit leakage current and significantly reduce the standby power
consumption. Second, the dual-gate-thickness processes give the option that the core circuits use
more advanced CMOS transistors to operate at higher frequencies, while the I/O interface blocks
using the thick-gate-oxide MOS transistors can bridge the core circuits with those implemented in
the older generations of technologies, or the peripheral circuits which usually employ higher voltages and operate at lower speed. Third, the thick-gate-oxide transistor is also beneficial for RF
25
and analog circuit design. While the higher transistor fT is certainly welcomed as the technology
advances, the lower supply voltage of thin-gate-oxide transistors causes some serious problems. It
can impair the ability to handle large signals. This limits the power handling capability of amplifiers, reduces the dynamic range, and worsens the phase noise of local oscillators. These can be
bypassed by realizing critical analog circuits with the thick-gate-oxide MOS transistors [Abi04].
1.4 Motivation
In present CMOS technologies, the polysilicon gates on the thin-gate-oxide and the
thick-gate-oxide transistors are formed at the same time. The thin-gate-oxide transistor has a
shorter feature length than that for thick-gate-oxide transistor. Therefore, the thick-gate-oxide
MOS transistor could have the same length as the thin-gate-oxide transistor, and the lithography
limitation is not a barrier to further shorten the thick-gate-oxide MOS transistor. Technically, it is
feasible to shrink the length of the thick-gate-oxide transistor to less than the minimum specified
in the design rule, and down to that for the thin-gate-oxide transistor.
With the steady scaling of thin-gate-oxide transistors, they can operate faster and tolerate
smaller voltage swings. On the other hand, the performance of 3.3-V thick-gate-oxide transistors
has remained standstill. Essentially, they are the devices belonging to an older generation. The
gap between the device characteristics of these two types of MOS transistors, such as supply voltage and current drive capability and so on, are becoming greater. Thick-gate-oxide transistors
with a certain degree of scaling with a better combination of current and voltage characteristics
can bridge this gap. To improve the performance of thick-gate-oxide MOS transistor for certain
applications as will be discussed, it is possible to scale down the horizontal dimensions of
thick-gate-oxide transistors to keep up with the scaling trend.
26
A goal of this research is to explore low cost solutions for scaling down the
thick-gate-oxide MOS transistor without modifying the existing foundry technologies. More specifically, the thick-gate-oxide transistors with a channel length less than the design rule specification is the focus of this study. They are named the SDR (sub-design-rule) MOS transistors.
The device characteristics of SDR transistors will be different from that of the normal
transistors, and in turn they may not be used in the conventional ways. To exploit this opportunity,
possible applications in both digital and RF circuits for the SDR MOS transistors are explored.
Careful design and good control of the SDR MOS transistor’s length are of importance.
1.5 Methodology
The SDR MOS transistors are structures that have channel lengths shorter than the minimum length required by the design rule. Their characterization data and models are not at hand.
Study and optimization of the SDR MOS transistors, or structures consisting of the SDR MOS
transistors, can typically be done in two ways:
The first one is to use the simulation techniques to predict the performance and to optimize structures at the same time. This method requires detailed process information provided by
the foundries. Even with that, the final characteristics still strongly depend on the accuracy of the
available fabrication parameters [McS02]. This information is proprietary in nature and is not
readily available. This method is a difficult option for university research.
The second method is to implement a variety of structures in a systematic manner and to
find out the optimal layout. Usually, multiple layout parameters should be varied, and a large
array of test structures should be tested. More intensive measurements are the drawback of this
method, but it can directly provide the final performance results. The second method is a practical
way for this work.
27
For each potential applications of the SDR MOS structures detailed in the following chapters (including both digital and RF circuits), a series of test structures are designed based on scientific insight and experience, then fabricated in foundry processes and evaluated for optimization.
1.6 Overview of the Dissertation
This dissertation starts with the applications of SDR MOS structures in digital interface
circuits. In Chapter 2, a conventional high-to-low level shifter circuit and the typical problems are
discussed. In this particular situation, the current drive capability and voltage tolerance can be
traded-off. Thick-gate-oxide MOS transistors with different sub-design-rule channel lengths are
measured and analyzed. It is shown that such MOS transistors can improve the current drive capability without over-stress. A high-to-low level shift circuit using such SDR MOS transistors will
also be discussed. In Chapter 3, the application in the low-to-high level shifter circuitthe counterpart in the reverse direction of I/O paths, is also studied. A composite MOS transistor consisting of a SDR MOS transistor and a conventional thin-gate-oxide transistor is proposed. It will be
shown that the composite MOS transistors, when properly designed, can provide higher current
drive capability without compromising the voltage tolerance. The speed performance of a
low-to-high level shifter using the composite MOS transistors as the drive transistors are compared to the case using the conventional transistors.
Then, building on the concept and characteristics of the SDR structures discussed in digital circuits, the potential for RF applications of the SDR MOS structures is evaluated. In Chapter
4, the potential application of the composite MOS transistors in RF power amplifiers is examined.
A T/R switch with power handling capability above 31 dBm is presented in Chapter 5. SDR MOS
transistors, along with other circuit techniques, are used to achieve this performance. The
trade-off between power handling capability and switch loss is also discuss. In Chapter 6, the high
28
frequency performance of SDR MOS structures used as varactors is presented. The higher quality
factor (Q) makes the SDR MOS varactors suitable for millimeter-wave low power and lower
phase noise voltage-controlled oscillator (VCO) applications.
Lastly, the dissertation is summarized and some future work is suggested in Chapter 7.
29
CHAPTER 2
HIGH-TO-LOW LEVEL SHIFTER APPLICATION
2.1 Introduction
As MOS transistors have scaled down along with the operating voltage [SIA05], the high
voltage input/output (I/O) transistors have become part of a standard technology offering to provide the option to maintain compatibility to the systems using circuits fabricated in the preceding
generations of technologies or other peripheral circuits [O95]. For instance, in 1.8-V 0.18-µm
CMOS processes, 3.3-V 0.35-µm I/O transistors with a thicker gate oxide layer are available.
Unlike the 1.8-V thin-oxide transistor, the 3.3-V thick-oxide transistor requires a longer channel
to support the 3.3-V drain voltage, which in turn limits its drain current.
As shown in Figure 2-1, digital circuits with different signaling levels will employ different voltages, for example, 1.8 V and 3.3 V, etc. These different voltages represent the same logic
high-VDD older generation circuits
or peripheral circuits
high-VDD I/O circuit
low/high
LS
low/high
LS
high/low
LS
high/low
LS
low-VDD core circuit
Figure 2-1.
Low-to-high and high-to-low level shifters (LS) used as the interface
circuits along the paths between the circuits with different signaling
levels.
30
level and they should be translated in both directions by the interface circuits. Therefore, both the
high-to-low and low-to-high level shifters are often used in the I/O circuits along the signal paths.
In this chapter, we will look into the high-to-low level shifter circuit and investigate the
potential application of the thick-oxide MOS transistors with channels shorter than the minimum
length specified in the design rule to improve the current drive capability.
Figure 2-2 shows a typical 3.3-to-1.8-V level shifter circuit [Wang01]. The 3.3-V
thick-oxide transistors (M5/M6) have to be used here as the drive transistors, because the 3.3-V
signal swings at the gates. However, the drain-to-source voltage (VDS) of the drive transistors in
this case only switches between 0 and 1.8 V. Because of this, the channel length chosen to handle
3.3-V Transistors
1.8-V Transistors
3.3 V
1.8 V
M2
M4
M6
In
M8
Out
M5
M3
M1
M7
3.3-V Drive Transistor
Level Shifter
Figure 2-2.
Typical high-to-low level shifter, using 3.3-V drive transistors at the
interface between 3.3-V and 1.8-V circuitries.
31
3.3 V is excessive, and unnecessarily limits the drain current of M5/M6. The drain current (ID) of
MOS transistors in the saturation region is given by following [Gra04]:
1
W
I D = --- µC ox  ----- ( V GS – V T ) 2 ,
2
L
(2-1)
and in the linear region,
W
1
I D = µC ox  -----  V GS – V T – --- V DS V DS ,
 L

2
(2-2)
where, µ is carrier mobility, Cox is unit capacitance of gate oxide, W is channel width, L is channel length, VGS is gate-source voltage, and VT is threshold voltage which is also dependent on L.
When the gate length L of the thick-oxide layer is scaled further the drain current will proportionally increase. Additionally, the shorter gate length will introduce more significant short
channel effect (SCE). Threshold voltage VT could be lowered, and the drain current will increase
even more. We refer to this type of further scaled thick-oxide MOS transistor as the
sub-design-rule transistor (SDR transistor).
In general, circuit designers can not violate the design rules of a process to reduce the
channel length arbitrarily. However, in this particular application  the high-to-low level shifter,
as will be discussed, there is some design space to improve the device and circuit performance.
We will push the process limit while not applying excessive stress to devices.
2.2 Sub-Design-Rule (SDR) MOS Transistor Structure
In this chapter, the thick-gate-oxide sub-design-rule (SDR) MOS structures fabricated in a
conventional 0.18-µm foundry digital CMOS technology without any process modification are
under investigation. In this technology, the minimum channel length for the conventional 3.3-V
thick-gate-oxide nMOS transistors is 0.35 µm. On the other hand, the minimum channel length
32
Thick Oxide
POLY
Gate
Source
Drain
n+
n+
LDRC = 0.35 µm
p-substrate
Substrate
Figure 2-3.
Cross-section of the sub-design-rule (SDR) MOS structure.
for 1.8-V thin-gate-oxide nMOS transistors is 0.18 µm. To further push forward the drive current
performance of the thick-gate-oxide device, channel length for SDR MOS transistors can be
between 0.18 and 0.35 µm. Figure 2-3 shows the cross-section of this type of devices. SDR MOS
transistors have the same structure as the conventional 3.3-V thick-gate-oxide MOS transistors,
except that the channel lengths are scaled to less than 0.35 µm, the minimum specification in the
design rule.
These SDR MOS transistors with channel lengths of 0.30, 0.28, 0.26, 0.24 and 0.22 µm
(SDR-30, -28, -26, -24, -22 MOS transistor) will be examined and compared to the characteristics
of conventional 0.35-µm long 3.3-V thick-gate-oxide MOS transistors in Sections 2.3 and 2.4.
These lengths are about 86%, 80%, 74%, 68% and 63% of that of the conventional 3.3-V transistor, respectively.
33
2.3 DC Characteristics of SDR MOS Transistors
To exam the DC characteristics, a series of DC test structures of SDR MOS transistors
with the same width (4.65 µm) are fabricated. Figure 2-4 shows the layout of a group of the test
structures. An HP4155A (semiconductor parameter analyzer) and a DC probe station are
employed for the measurements.
SDR Transistors
G
D
G
D
G
D
S
B
S
B
S
B
Figure 2-4.
Test structure layout of a set of SDR MOS transistors for DC
measurements.
2.3.1 Current Drive Capability
ID-VGS curves of these SDR MOS transistors at VDS = 1.8 V are shown on the right side
of Figure 2-5. Drain currents in the plot are normalized to unit channel width. By scaling the
thick-gate-oxide transistor from 0.30 to 0.22 µm, current drive capability is significantly
increased.
As shown from Equation 2-1 and 2-2, there are two main factors leading to the drain current increases.
(a)
W
Increase of  ----- ratio, or effectively decrease of L.
 L
34
10-4
0.8
ID / width (A/µm)
10
0.6
0.26µm
0.28µm
0.30µm
10-8
0.4
10-10
0.2
10-12
10-140.0
Figure 2-5.
(b)
ID / width (mA/µm)
0.22µm
0.24µm
-6
1.0
2.0
VGS (V)
3.0
0.0
Normalized ID-VGS for different SDR MOS transistors at VDS = 1.8 V.
1
Increase of ( V GS – V T ) and  V GS – V T – --- V DS , due to
2
decrease of VT.
Comparing the SDR-22 to the SDR-30 MOS transistor, for example, the current ratio at
VGS = 3.3 V and VDS = 1.8 V is about 1.4. Now the SDR MOS transistors are biased in the linear
W
region. This current difference is largely due to the increase of  ----- ratio, or the decrease of L.
 L
1
The  V GS – V T – --- V DS = ( 3.3 – V T – 0.9 ) term gives a relatively smaller improvement fac

2
tor for different SDR MOS transistors with lowered threshold voltages.
The high-VDS data in Figure 2-5 clearly show that the down-ward shift of threshold voltage (VT) occurs when SDR MOS transistor is scaled from 0.30 to 0.22 µm. The exact dependence
of threshold voltage on channel length can be extracted from the low-VDS measurement results,
which is plotted in Figure 2-6. When biased at low over-drive condition (VGS ~ 1.0 V), these SDR
35
1.0
VT (V)
0.8
0.6
0.4
0.2
0.0
0.0
0.2
0.4
0.3
0.5
0.6
L (µm)
Figure 2-6.
Measured threshold voltages of SDR MOS transistors with different
channel lengths.
MOS transistors are in saturation region and the drain current improvement in percentage is even
more dramatic than high over-drive case (VGS ~ 3.0 V). This is because, when VGS approaches
threshold voltages (VT), the term ( V GS – V T ) 2 is a stronger function of VT, and gives a more significant current increase in percentage.
As shown in Figure 2-6, the threshold voltages of SDR MOS transistors abruptly drops
when the channel length is shorter than 0.35 µm, the minimum design rule specification. It is
expected that at certain point, the threshold voltage can be negative, which means this SDR MOS
structure will be always on and is no longer a normal transistor. This threshold voltage change sets
the lower limit for the channel length of a functional SDR MOS transistor. An SDR MOS transistor can not be much lower than 0.22 µm in this particular CMOS process.
Once again in Figure 2-5, the logarithm scale plots on the left side reveal the subthreshold
characteristics of these SDR MOS transistors. Unless the channel length reaches 0.22 µm, all
36
SDR MOS transistors have almost same subthreshold slope and normal subthreshold behaviors.
Higher subthreshold currents are as expected for the SDR MOS transistors because the threshold
voltage is lowered. However, the drain leakage current at VGS = 0 V is still well below 1 nA/µm
and considered within the controllable scope [SIA05]. Within a certain range of channel lengths,
we do have some opportunities for optimization of SDR MOS transistors.
2.3.2 Voltage Handling Capability
The breakdown voltage (VBK) sets the maximum voltage that can be applied either across
the drain and source, or across the gate and drain. When VDS approaches the breakdown voltage,
the drain current of device rapidly increases, even abruptly jumps which should be always
avoided. Therefore, a sufficient voltage margin should be reserved between the transistor’s operational voltages and its breakdown voltages. When breakdown occurs, ID - VDS curves will bend
the most. We can expect the greatest curvature around the breakdown voltage along the curves.
For consistency and ease of comparison, breakdown voltages for these MOS transistors are measured at the drain-to-source voltage (VDS) when the second derivatives of ID to VDS reach the
maximum.
The lowering of breakdown voltages in SDR MOS transistors is one of the most important
effects resulting from further scaling down of the channel length. Listed in Table 2-1 are the mea-
Table 2-1. Breakdown voltages of sub-design-rule MOS transistors
0.22
0.24
0.26
(SDR-26)
0.28
0.30
0.35
(3.3-V)
VGS=1.0/
1.4
~ 4.7
~ 4.8
~ 5.0
~ 5.1
~ 5.3
~ 6.4
VGS=0
-
-
~ 8.4
~8.4
~8.4
~ 8.6
L (µm)
VBK (V)
37
sured breakdown voltages of SDR MOS transistors, together with that of the conventional 3.3-V
MOS transistor.
At VGS = 1.0 / 1.4 V, the breakdown voltages of these SDR MOS transistors drop from
that of the 3.3-V transistor by 1.1 ~ 1.7 V. The reason is that the punch-through between the drain
and source occurs more easily when the channel becomes shorter. This effect limits the maximum
voltage that can be applied to the drain node of SDR transistors. We need to sacrifice some voltage handling capability to obtain the current advantage of these SDR transistors. In Section 2.3.3,
there will be more discussions on the proper selection of channel length of SDR MOS transistors
particularly for the 3.3-to-1.8-V level shifter application.
The off-state breakdown voltages measured at VGS = 0 V show no obvious degradation
due to the scaling of the SDR MOS transistors down to 0.26 µm. The gate oxide of SDR transistors is shorter than the conventional 3.3-V transistor, while the thickness is the same as that of the
conventional transistor. The gate dielectric layer should sustain similar voltage across it, either
between the drain and gate, or between the gate and source. This means that these SDR MOS
transistors can tolerate as much gate-to-drain voltage (VGD) as the conventional 3.3-V MOS transistor. Therefore, the gates of SDR MOS transistors can be biased up to 3.3 V without excessively
stressing the MOS structures.
2.3.3 Optimization of MOS Transistors for Level Shifter Application
The 3.3-to-1.8-V level shifter circuit is an excellent example of digital application for
SDR MOS transistors. The conventional 3.3-V MOS transistors (M5/M6 in Figure 2-2) can easily
be replaced by the SDR MOS transistors for drive current enhancement.
Because the gate oxide layer of SDR MOS transistors is sufficient to handle the 3.3-V
swing from the preceding circuitry, there is no undermining of voltage tolerance at its gate node.
38
On the drain side, the SDR transistors replacing M5/M6 only need to sustain 1.8-V, instead of
3.3-V swing. The breakdown voltage necessary for the 1.8-V operation could be lower. The voltage margin (VBK-VDD) reserved for the conventional 3.3-V MOS transistors with 3.3-V supply
voltage is about 3.1 V (6.4V-3.3V). The measurement results in Table 2-1 indicate that the
0.26-µm long SDR transistor (SDR-26) has high enough breakdown voltage (~ 5.0V), so that an
adequate margin (5.0V-1.8V=3.2V) is kept for its operation with 1.8-V supply. Furthermore, in
this level shifter application, the gates of drive transistors (M5/M6) are swept quickly from 0 V to
3.3 V, with drain biased no higher than 1.8 V. The drive transistors enter linear region almost
instantaneously, and for only a small portion of time the transistors stay in saturation region.
Because of these, the level shifters using the SDR-26 transistors should be resistant to the hot-carrier related performance degradation [Tak95].
1.0
SDR-26
ID /width (mA/µm)
0.8
VGS=
3.3V
0 ~ 1.8V
2.8V
0.6
2.3V
0.4
1.8V
1.3V
0.2
0.8V
0.0
0.0
Figure 2-7.
1.0
2.0
VDS (V)
3.3-V
3.3V
2.8V
2.3V
1.8V
1.3V
0.8V
3.0
Comparison of normalized ID-VDS between SDR-26 and conventional
3.3-V MOS transistors.
39
The SDR-26 MOS transistor is 26% shorter than the conventional 3.3-V transistor. Its
threshold voltage is 0.66 V, which is 0.18 V lower than that of the 3.3-V transistor. When M5/M6
in Figure 2-2 are replaced by SDR-26 MOS transistors, the gate overdrive (VGS-VT = 3.3-VT) is
increased by about 7%.
The ID per unit width (µm) versus VDS curves of SDR-26 and 3.3-V MOS transistors are
shown in Figure 2-7. Biased at the same gate-to-source voltage (VGS), the SDR-26 MOS transistor delivers more than 1.28 times the current of the 3.3-V transistor. In Figure 2-8, the ID-VGS
curves of SDR-26 and 3.3-V transistors are also compared. The linear scale plots once again show
that the drain current of the SDR-26 transistor is at least 1.28 times that of the 3.3-V transistor,
and this current enhancement is even more substantial for low VGS (~ 1 V). The shaded area in
Figure 2-8 clearly illustrates the current increase.
0.8
10-4
0.6
10-8
0.4
10-10
10-12
10-14
0.0
Figure 2-8.
1.0
2.0
VGS (V)
ID / width (mA/µm)
ID / width (A/µm)
10-6
SDR-26, VDS=1.8V 0.2
3.3-V, VDS=1.8V
SDR-26, VDS=0.05V
3.3-V, VDS=0.05V
0.0
3.0
Comparison of normalize ID-V GS between SDR-26 and conventional
3.3-V MOS transistors in both linear and logarithm scales, when VDS =
1.8 and 0.05 V.
40
Normal subthreshold behaviors can be observed by the logarithm scale plots in Figure 2-8.
SDR-26 and 3.3-V MOS transistors have same subthreshold slopes at both low and high VDS,
indicating the short channel effects are still well controlled in SDR-26 MOS transistors. The leakage current of SDR-26 transistors at high VDS is increased to 10-12 from 10-14 A/µm, which is
still lower than the specification for low voltage transistors in more advanced CMOS processes
[SIA05]. Additionally, since the number of I/O drive transistors used in an integrated circuit is
limited, this increased leakage is tolerable.
2.4 Capacitance Property of SDR-26 MOS Transistor
Speed performance in digital circuits usually can be evaluated by the propagation delay
(τd), as well as the rise time (τr) and the fall time (τf). From Equation 2-3, we can see both the current drive capability ( I o ) of preceding stage and gate capacitance (Cload) as the load to preceding
stage strongly affect the speed performance.
Cload ⋅ ∆V
τ d = --------------------Io
(2-3)
All data compared above, however, are measured at the same channel width (W) for
SDR-26 and 3.3-V MOS transistors. Compared to the 3.3-V transistors with unit width, the
SDR-26 transistors have the same gate-oxide thickness but shorter length, therefore less gate
capacitance. For a fairer comparison, the drain current should be normalized to the same gate
capacitance. Therefore, it is necessary to study the dependence of gate capacitance on the channel
length of SDR MOS transistors.
Approximately, the gate capacitance (CGS) of MOS structures has the linear relation with
length L as shown below:
41
C GS = C GSO ⋅ W + γ ⋅ C ox ⋅ W ⋅ L ,
(2-4)
where, γ represents the constant for saturation region or linear region. Simulation data of
longer-channel 3.3-V thick-oxide MOS transistors between 0.35 and 1.0 µm long are plotted in
Figure 2-9. The unit gate capacitance of 0.35-µm long 3.3-V MOS transistors is 1.67 fF/µm as
simulated. The linear fitting line is drawn in Figure 2-9, and it can be used to extrapolate the gate
capacitance (CGS) of SDR MOS transistors. The SDR-26 MOS transistor of interest is expected to
have unit gate capacitance of 1.33 fF/µm, which is only 79.6% of that of the minimum length
3.3-V MOS transistors. Compared at the same gate capacitance which acts as the load to preceding stage, a SDR-26 transistor is 25.6% wider and this increases its drive current to about 60%
higher than that of the conventional 3.3-V MOS transistor.
Gate capacitance / width (fF/µm)
5.0
Longer Channel 3.3-V
Extrapolation
4.0
3.0
(0.26µm, 1.33fF/µm)
2.0
1.0
0.0
(0.35µm, 1.67fF/µm)
SDR region
0.0
0.2
0.4
0.6
0.8
1.0
Channel Length (µm)
Figure 2-9.
Simulated gate capacitance of longer channel 3.3-V MOS transistors, and
extrapolated gate capacitance of SDR-26 MOS transistors.
42
2.5 High-to-low Level Shifter Speed Performance
Between SDR-26 and 0.35-µm long conventional 3.3-V MOS transistors, the increases of
drain current in both fixed channel width and fixed gate capacitance cases are described in the
previous sections. To interpret such improvements to the speed performance in a level shifter circuit, Cadence Spectre simulator is used to estimate the difference.
At first, modeling of SDR-26 MOS transistors is necessary. Based on the conventional
3.3-V transistor’s model file, we built a model to approximately describe the behavior of the
SDR-26 transistor by modifying a few parameters, such as gate oxide thickness (tox), threshold
voltage (vth0), mobility (u0) and saturation velocity (vsat) (see APPENDIX). Shown in
Figure 2-10 are the simulated ID-VDS and ID-VGS for both the SDR-26 and 3.3-V MOS transistors, with the same channel width. The plots match the measurement results. This simulation con1.0
simulated
measured
ID / width (A/µm)
0.8
ID-VDS of SDR-26
ID-VDS of 3.3-V
0.6
VGS = 3.3 V
0.4
ID-VGS of SDR-26
VDS = 1.8 V
0.2
ID-VGS of 3.3-V
0.0
0.0
Figure 2-10.
1.0
2.0
VDS / VGS (V)
3.0
Simulated ID-V DS and I D-VGS curves of the SDR-26 and 3.3-V MOS
transistors. The simulations also match the measured currents for both
types of transistors.
43
firm that the “created” model file gives 1.28 times the drain current of the conventional 3.3-V
transistors. The SDR-26 and 3.3-V MOS transistors have gate capacitance of 6.23 and 7.85 fF,
respectively, so that the capacitance ratio is 0.79. These changes reflect the measured improvement of current drive capability discussed in Section 2.3.3 and gate capacitance change discussed
in Section 2.4.
Secondly, the same 3.3-to-1.8-V level shifter structure shown in Figure 2-2 is used in simulation. Two versions of level shifters under comparison are shown in Figure 2-11. Version A rep-
3.3-V inverter
1.8-V inverter
level shifter A
1.8V
conventional 3.3-V
A1
A2
A3
A4
M2A
A5
A6
A7
M1A
outputA
Version A
Version B
input
level shifter B
1.8V
outputB
B1
B2
B3
B4
M2B
B5
B6
B7
M1B
SDR-26
3.3-V circuitry
Figure 2-11.
1.8-V circuitry
Schematics of level shifter circuits in simulation. Version A uses
conventional MOS transistors as drive transistors, while Version B uses
SDR-26 MOS transistors.
44
resents the conventional implementation, and the conventional 3.3-V MOS transistors are used as
the drive transistors (M1A/M2A) in the level shifter. The 3-stage 3.3-V inverter chain (A1 through
A3) preceding the level shifter generates an input signal whose shape is approximately independent of the number of propagation stages. Similarly, the 3-stage conventional 1.8-V inverter chain
(A5 through A7) is also used following the level shifter to maintain the same capacitive loading
for the level shifter [Tau98]. All these inverters use the conventional 3.3/1.8-V nMOS/pMOS
transistors. The version B is the same as version A, except that the two drive transistors (M1B/
M2B) are replaced by the SDR-26 MOS transistors. These two SDR-26 transistors in version B
are 26% wider than their counterparts in version A, so that the inverters A3 and B3 will see the
same capacitive loads.
In Figure 2-12, both the pull-down and pull-up cases for the level shifters are examined. In
both Figure 2-12 (a) and (b), the input signals (Figure 2-11) for different implementations are the
same and overlaid. This is possible because the drive transistors of these two versions give the
same capacitive load to the preceding stages. The same input signals with 3.3-V swing are
delayed differently and level-shifted to output signals with 1.8-V swing. The time differences of
output signals for both pull-down and pull-up cases directly show the improved speed performance of the level shifter implemented by using the SDR-26 transistors over the conventional
3.3-V transistors.
The data extracted from the waveforms are listed in Table 2-2, including the pull-down
propagation delay (τn) and the pull-up propagation delay (τp), and the fall time (τf), the rise time
(τr). A nearly 20% improvement in the propagation delay is expected from this 3.3-to-1.8-V level
shifter circuit using SDR-26 MOS transistors. This speed improvement is obtained without any
45
τnB
outputB
outputA
input
τnA
A
τpB
input
outputB
outputA
τpA
B
Figure 2-12.
Comparison of the SDR-26 and conventional 3.3-V MOS transistors used
as the drive transistors in 3.3-to-1.8-V level shifters. (A))propagation
delay in pull-down case (τn); (B) propagation delay in pull-up case (τp).
process modifications, therefore using SDR-26 transistors is a low-cost solution. There is no
change in the circuit configuration.
46
Table 2-2. Speed performance of level shifters using the SDR-26 and conventional 3.3-V
MOS transistors as the drive transistors
version A
(conventional 3.3-V)
version B
(SDR-26)
delay
improvement
pull-down delay (ps)
τnA = 28.2
τnB = 23.5
16.7%
pull-up delay (ps)
τpA = 47.4
τpB = 38.2
19.4%
fall time (ps)
τfA = 64.67
τfB = 47.55
26.5%
rise time (ps)
τrA = 100.94
τrB = 66.94
33.7%
2.6 Summary
Level shifters are crucial for digital CMOS I/O interface circuits to translate different voltage levels back and forth. Level shifting needs extra stages, and introduces extra delays, which
should be limited to minimum. In a high-to-low level shifter, the drive transistors have to be realized by using thick-oxide high-voltage MOS transistors to withstand the high voltage swing at
gate node. The drain nodes of drive transistors, however, only need to handle low voltage swing.
These characteristics of high-to-low level shifters provide the opportunities for use of SDR MOS
transistors which have higher current drive capability.
In this chapter, a 3.3-to-1.8-V level shifter circuit using a 0.18-µm CMOS foundry technology is studied. The conventional 3.3-V MOS transistor is compared to a series of thick-oxide
SDR MOS transistors. The measurement results show that, in this particular application, the
0.26-µm long SDR MOS transistor (SDR-26) can deliver 1.28 times the drain current as the conventional one, while maintaining sufficient breakdown voltages to tolerate the signal swing at the
gate and drain nodes. When replacing the conventional 3.3-V drive transistors in the 3.3-to-1.8-V
level shifter, the SDR-26 transistors are 25.6% wider and can provide 60% more drain current. In
47
simulations, this current enhancement translates into a nearly 20% reduction in the propagation
delay.
The use of SDR MOS transistors in the high-to-low level shifters should not be limited
only to this 0.18-µm technology by all means. This concept should be viable in other more
advanced technologies. In general, this application of SDR MOS transistors provides another way
to exploit the scaling of CMOS technologies. This study shows that further scaling and optimizing
the thick-oxide MOS devices are feasible and can provide useful benefits.
48
CHAPTER 3
LOW-TO-HIGH LEVEL SHIFTER APPLICATION
3.1 Introduction
Another circuit needed in the input/output (I/O) blocks is a low-to-high level shifter circuit. Figure 3-1 shows the schematic of a conventional low-to-high level shifter [Koo05, Tan02].
Thick-gate-oxide high-voltage MOS transistors are used as the drive transistors (M15/M17) here,
because they have to sustain high-VDD signal swing at the drain nodes. A problem with this
implementation is that the gates of thick-gate-oxide high-voltage drive transistors (M15/M17)
with higher threshold voltage are driven by a circuit whose output switches only between 0 and
Thin-gate-oxide Transistors
Thick-gate-oxide Transistors
High-VDD
Low-VDD
M12
M11
In
M16
M20
M18
M14
Out
M13
M15
M17
M19
Drive Transistors
Level Shifter
Figure 3-1.
Typical low-to-high level shifter, using thick-gate-oxide drive transistors
at the interface between low-VDD and high-VDD circuitries.
49
low-VDD. Because of this, the gate overdrive (VGS-VT) is small, thus the drive current is limited.
These in turn limit the switching speed of I/O circuits.
In the previous chapter, we have studied a typical 3.3-to-1.8-V CMOS level shifter, and
the way to improve the speed performance by using the SDR MOS transistors. Could this idea of
using thick-oxide sub-design-rule (SDR) MOS transistor become an inspiration to build another
structure suitable for low-to-high level shifter circuits?
Extensive efforts have been taken to improve the voltage and power handling capability of
the MOS transistors, while still keeping the drain current and gm high [Ma99, Buc03, Lia03,
Men04]. In these cases, geometry and/or doping profile need to be modified. Unfortunately, these
solutions usually are either incompatible with standard CMOS technologies, or require certain
modifications to existing foundry processes and increase the fabrication cost.
In this chapter, we want to take advantage of the SDR MOS transistor concept, and build a
novel composite structure suitable for use in the low-to-high level shifter, which is fully compatible with the standard CMOS processes from the foundries.
3.2 Composite MOS Transistor Structure
As discussed, the thin-gate-oxide MOS transistor has higher unit drain current and faster
speed performance. This device is suitable for low power circuits because the voltage tolerance is
limited. On the contrary, the thick-gate-oxide MOS transistor has lower unit drain current and
slower speed performance. However, this type of device is preferable for high voltage, high power
situation due to the thicker gate dielectric layer. To combine the advantages of these two types of
MOS devices, a composite MOS transistor structure is proposed in this chapter [Xu05].
The composite MOS transistor consists of a series combination of a conventional
thin-oxide transistor (TN sub-transistor) and a sub-design-rule thick-oxide sub-transistor (SDR
50
Poly Gate 2
Implant
Mask
Source
Diffusion
Mask
A
B
Drain
Thick Oxide
Mask
Poly Gate 1
Figure 3-2.
Layout of the composite MOS transistor. Only 2 cells are shown here.
sub-transistor). A layout of such a composite MOS transistor is shown in Figure 3-2. A multiple-finger layout is employed, and two cells are shown here as illustration.
The cross-section along dashline AB (see Figure 3-2) is also drawn in Figure 3-3. The TN
sub-transistor and SDR sub-transistor share an n+ diffusion region in the middle without metal
connection. The diffusion on the left side of TN sub-transistor acts as a source, and the diffusion
on the right side of SDR sub-transistor acts as a drain. Their polysilicon gates are connected
together by metal layers to form a single gate, and their bodies are connected together through the
p-substrate. Such a four-terminal structure functions as a single MOS transistor. The equivalent
circuit of the composite MOS transistor as well as its simplified version are shown in Figure 3-4.
Compared to the conventional thin-oxide transistor (TN sub-transistor), the composite
transistor has lower drain current due to the additional SDR sub-transistor in series combination.
51
POLY
Thin Oxide
Gate1
Thick Oxide
Gate2
Source
Drain
n+
n+
n+
Shared Diffusion
TN Sub-transistor
Figure 3-3.
Substrate
p-substrate
SDR Sub-transistor
Cross-section of the composite MOS transistor.
On the other hand, the SDR sub-transistor helps the composite transistor to tolerate a larger voltage drop across its drain and gate, and across its drain and source than the thin-oxide transistor.
This of course increases the breakdown voltage of composite transistor structure compared to that
of the thin-oxide transistor alone. The composite structure is similar to the cascode configuration
with a common gate stage using a thick-oxide transistor, which has been proposed to improve the
voltage handling capability [Web03]. However, besides the gate connections, another key difference is that the channel length of SDR sub-transistor is significantly shorter than the minimum
length of the conventional thick-oxide transistors. This modification increases the drain current.
Because of the strong short channel effects, the SDR sub-transistor has lower threshold voltage
and the dramatically increased leakage current if it is used with a 3.3-V supply. Therefore, such an
SDR sub-transistor does not work normally by its own, and should be used in series combination
with a conventional TN sub-transistor. It is expected that the drain current of the composite MOS
52
SDR Sub-transistor
Drain
Gate2
Drain
Gate
Sub
Gate
Sub
Source
Gate1
Source
TN Sub-transistor
Figure 3-4.
Equivalent schematics of the composite MOS transistor.
transistor is somewhere in between those of the conventional thick-oxide and conventional
thin-oxide transistors, as will be discussed in the following sections.
3.3 Composite MOS Transistors in a 0.18-µm Process
The first composite MOS transistor was fabricated in the same 0.18-µm CMOS technology as the SDR MOS transistors discussed in Chapter 2. This composite structure will be referred
as composite-18 transistor and it consists of a 0.18-µm long thin-oxide transistor (TN transistor)
and a 0.18-µm long thick-oxide transistor (SDR-18 sub-transistor). This combination of channel
lengths is intended to diminish the drain current degradation caused by the SDR transistor in
series. However, having this thin oxide as part of the gate inevitably sets the maximum
gate-to-source voltage to 1.8 V.
53
To study its possible advantages over conventional transistors, a 0.35-µm long 3.3-V
thick-oxide and a 0.18-µm long 1.8-V thin-oxide MOS transistor were also fabricated in the same
technology for comparison. All the transistors have the same channel width (23.25 µm). The layout of the DC test structures is shown in Figure 3-5. A semiconductor parameter analyzer
(HP4155A) and a DC probe station are employed for the measurements.
Transistors
G2
G1
D
G
D
G
D
S
B
S
B
S
B
Figure 3-5.
Test structure layout of the composite-18, conventional 3.3-V thick-oxide
and conventional 1.8-V thin-oxide MOS transistors for DC
measurements.
3.3.1 Current and Breakdown Characteristics
Figure 3-6 shows the measured ID per unit width versus VDS. The gates of composite-18,
conventional 3.3-V and 1.8-V transistors are biased up to 1.8 V, 3.3 V and 1.8 V, respectively. The
composite-18 transistor at VGS = 1.8 V can deliver as much current as the 3.3-V transistor biased
at VGS = 3.3 V. If biased at the same gate voltage (VGS = 1.8 V), the composite-18 transistor provides about 3 times of the saturation current of the 3.3-V transistor. This drive capability is even
comparable to that of a 1.8-V transistor. This result is surprisingly good.
54
0.8
ID / width (mA/µm)
0.6
composite-18
3.3-V
1.8-V
1.8V
1.8V
3.3V
0.4
1.3V
2.8V
1.3V
2.3V
0.2
0.0
0.0
0.8V
0.8V
1.8V
0.3V
0.3V
1.3V
3.0
2.0
1.0
VDS (V)
Figure 3-6.
Normalized I D-VDS of the composite-18, conventional 3.3-V thick-oxide
and conventional 1.8-V thin-oxide MOS transistors.
The breakdown voltages (VBK’s) and threshold voltages (VT’s) of these three types of
transistors are listed in Table 3-1. The composite-18 transistor has comparable breakdown voltage
as the 3.3-V transistor. This is about 50% higher than that of the 1.8-V transistor. Furthermore, the
composite-18 transistor still has the same low threshold voltage as that of the 1.8-V transistor,
which is 0.4 V below that of the 3.3-V transistor. This in turn further increases the current drive
capability of the composite-18 transistor compared to that for the conventional 3.3-V transistor.
Table 3-1. Breakdown voltages and threshold voltages for the composite-18, and the
conventional 3.3-V and 1.8-V MOS transistors
VBK (V)
VT (V)
3.3-V
composite-18
1.8-V
VGS=0
~ 9.0
~ 9.0
~ 6.5
VGS=1.8/3.3
~ 5.5
~ 6.5
~ 4.0
VDS=0.05
~ 0.9
~ 0.5
~ 0.5
55
3.3.2 Subthreshold Current Leakage Issues
As shown in Figure 3-7, the ID-VGS curves in a logarithm scale reveal the subthreshold
behaviors of the composite-18, conventional 3.3-V and 1.8-V MOS transistors. For low VDS
cases (VDS = 0.05 V), all three types of transistors have the same subthreshold slopes and the normal subthreshold behaviors can be observed. However, when the VDS is biased at VDD (3.3 V for
the composite-18 and 3.3-V transistors, 1.8 V for the 1.8-V transistors), the composite-18 transistor obviously has abnormal subthreshold behavior compared to the other two conventional transistors. The drain leakage current of the composite-18 transistor around VGS = 0 levels off, and is
significantly higher than expected.
The cause of this behavior is that abnormally high voltage is present at the shared diffusion region of the composite structure (VM(a) in Figure 3-8 (a)), producing higher leakage current
VDS = 1.8/3.3 V
10-2
10-4
10-8
10-10
10-12
VDS = 0.05 V
(su
bth
res
hol
d re
gio
n)
ID (A)
10-6
10-14
0.0
composite-18
3.3-V
1.8-V
1.0
2.0
3.0
VGS (V)
Figure 3-7.
ID-V GS curves in a logarithm scale for the composite-18, conventional
3.3-V and 1.8-V MOS transistors with V DS = 0.05 V and V DD (1.8/3.3 V).
56
through the drain to body [Cha01]. We are not able to directly measure the voltage at this node
(VM(a)) because there is no pad connection for the node in the test structure. However, this problem can be solved by using source current matching to calculate the voltage of the shared diffusion region.
Using two DC test structures, the currents at any nodes of the composite-18 and the 1.8-V
transistors can be measured separately. The gate current is usually negligible, and other current
IS(a)
n+
ID(a) = ID2
VM(a)
n+
IS(a)
(TN Sub-transistor)
ID1(a)
IB1(a)
(SDR Sub-transistor)
IB(a)
=
IB1(a)
VD
n+
IB2
p-substrate
+ IB2
A
IS(b)
n+
ID(b) = ID1(b)
VM(b)
IS(b)
(1.8-V Transistor)
n+
IB1(b)
p-substrate
IB(b) = IB1(b)
B
Figure 3-8.
Illustration of source current matching between (A) the composite-18
transistors and (B) the conventional 1.8-V MOS transistors.
57
paths in the composite-18 and conventional 1.8-V MOS transistors are shown together in
Figure 3-8. It is obvious that, the source currents (IS(a), IS(b)) are
for the composite-18 transistor,
(a)
IS
(a)
(a)
(a)
(a)
(a)
= I D – I B = I D2 – ( I B2 + I B1 ) = I D1 – I B1 ,
(3-1)
for the 1.8-V transistor,
(b)
IS
(b)
(b)
= ID – IB
(b)
(b)
= I D1 – I B1 .
(3-2)
The TN sub-transistor is exactly the same structure as the conventional 1.8-V transistor,
therefore each of the source current (IS(a) and IS(b)) is the same monotonic function of VM(a) and
VM(b). Despite the discrepancy in the drain current or the body current between the two transistor
structures, each of the transistors should have the same VM (i.e., VM(b) = VM(a)) when the source
currents are same (IS(a) = IS(b)). Therefore, we can match the source currents of the these transistors, and get the voltage of shared diffusion region (VM(a)) by reading the drain voltage of the
1.8-V transistor (VM(b)).
The IS-VDS curves of the composite-18 and 1.8-V MOS transistors are drawn together in
Figure 3-9 to demonstrate the method of source current matching. When VGS is between 1.0 and
0.4 V as shown in Figure 3-9 (a), the matched voltages at the shared diffusion region (VM(a)) are
only between 1.4 and 1.8 V. Just like what we have seen in Figure 3-7, there is no significant
increase of the drain leakage current. When VGS is further lowered as shown in Figure 3-9 (b) and
(c), however, it is evident that the matched voltage (VM(a)) increases quickly and could be higher
than 2.2 V. This is consistent with the deviation of subthreshold current from the normal seen in
Figure 3-7. The worst case occurs at VGS = 0 V, when the matched voltage at the shared diffusion
58
4.0e-3
VGS=1.0
0.9
IS (A)
3.0e-3
VM(a) = VM(b)
2.0e-3
0.8
0.7
1.0e-3
0.0
composite-18
1.8-V
matched VM(a)
0.0
1.0
2.0
IS (A)
2.0e-6
1.5e-6
0.6
0.5
0.4
3.0
A
VGS=0.3
composite-18
1.8-V
matched VM(a)
1.0e-6
VM(a) = VM(b)
5.0e-7
0.0
0.0
8.0e-9
IS (A)
6.0e-9
VGS=0.2
1.0
2.0
composite-18
composite-18
1.8-V
1.8-V
matched VM(a)
3.0
B
VGS=0.1
4.0e-9
VM(a) = VM(b)
2.0e-9
VGS=0.0
0.0
Figure 3-9.
0.0
1.0
2.0
(b)
VM or VD (V)
3.0
C
Calculation of the voltage at the shared diffusion region (VM(a)) by using
source current matching. (A) VGS=1.0~0.4 V; (B) VGS=0.3~0.2 V; (C)
VGS=0.1~0.0 V
59
reaches the highest. This increased voltage (VM(a)) at the shared diffusion is higher than the nominal value (1.8 V), and it can cause the gate-oxide wear-out and the hot-carrier related performance degradation in the TN sub-transistor. This undermines the reliability of the composite-18
transistors even though VM(a) is not sufficient to cause breakdown. Therefore, the 0.18-µm long
SDR sub-transistor can not sustain sufficient voltage drop to protect the TN sub-transistor. In this
0.18-µm CMOS process, an SDR sub-transistor with a channel length longer than 0.18 µm is necessary for the composite transistor.
Because of these, the composite MOS transistors should not only be checked for the
breakdown voltages, but also checked for the subthreshold leakage currents to assure that each
sub-transistor inside the composite structures is reliable throughout the operation voltage ranges.
3.4 Composite MOS Transistors in a 0.13-µm Process
In the second realization, a series of DC test structures of different composite MOS transistors with the same width (2.96 µm) is fabricated in a foundry 0.13-µm CMOS technology. The
TN sub-transistors in all these composite transistors have the minimum length for conventional
1.2-V transistors, which is 0.12 µm. The SDR sub-transistors of these structures include lengths
of 0.20, 0.22, 0.23, 0.25, and 0.27 µm. The lengths of the SDR sub-transistors are used as the
names of different composite transistors, for instance, composite-27 and so forth. Figure 3-10
shows the layout of a DC test structure. For better die area efficiency, the DC pads for drain and
body node connections are shared by three transistor structures. In the same process, the conventional 0.12-µm long 1.2-V thin-oxide transistor and conventional 0.34-µm long 3.3-V thick-oxide
transistors are also fabricated for comparison.
60
composite transistors
S
Figure 3-10.
D1
D2
D3
G1
G2
G3
B
Test structure layout of a group of the composite MOS transistors for
DC measurements.
3.4.1 Current Characteristics
ID-VGS curves of the composite MOS transistors at VDS = 3.3 V are compared to those of
the conventional 3.3-V and 1.2-V transistors in Figure 3-11. The drain currents in the plot are normalized to unit channel width.
As shown in the linear scale plots in Figure 3-11, reducing the length of thick-gate-oxide
SDR sub-transistor in the composite structure from 0.27 to 0.20 µm significantly increases the
drain current, and makes the drain current approach that of the conventional 1.2-V transistor. For
example, between the composite-20 (0.20-µm long SDR transistor) and composite-27 (0.27-µm
long transistor), the current ratio at VGS = 1.2 V is more than 2. Even though it is not straightforW
ward to calculate the effective  ----- ratio for these composite transistors, the use of thick-oxide
 L
SDR MOS structures in the composite transistor design contributes to the drain current increase.
In addition, the threshold voltage of SDR sub-transistor decreases when it is scaled, as discussed in Section 2.3. The SDR sub-transistor sets the limit for channel formation, until its threshold voltage is lowered to that of the TN sub-transistor. When the SDR sub-transistor is scaled
61
10-3
0.8
comp-20
comp-22
comp-23
comp-25
comp-27
10-7
0.6
0.4
ID (mA)
ID (A)
10-5
10-9
composite
3.3-V
1.2-V
10-11
10-13
0.0
Figure 3-11.
1.0
VGS (V)
2.0
3.0
0.2
0.0
Normalized ID-VGS plots for the composite and the conventional 3.3-V
transistors with VDS = 3.3 V, and the conventional 1.2-V transistor with
VDS =1.2 V.
from 0.27 to 0.22 µm, the threshold voltage of the composite transistor decreases. The high-VDS
measurement results in Figure 3-11 show the down-ward shift of threshold voltage (VT) with the
SDR sub-transistor length. The threshold voltages of the composite transistors extracted from the
low-VDS measurement data are listed in Table 3-2. These values are closer to that of the 1.2-V
transistor, rather than to that of the 3.3-V transistor. The composite-22 transistor has about the
Table 3-2.
Measured threshold voltages of the composite transistors, and the
conventional 1.2-V, 3.3-V transistors
transistors
1.2-V
com-22
com-23
com-25
com-27
3.3-V
VT(V)
~ 0.46
~0.46
~ 0.48
~0.52
~0.56
~ 0.72
62
same threshold voltage as the conventional 1.2-V transistor, which is 0.26 V below that of the
3.3-V transistor. In the case of 1.2-to-3.3-V level shifter, the overdrive (VGS-VT) of drive transistor is relatively small (~ 0.5 V) and can be significantly increased in percentage by decreasing the
threshold voltage. When biased at the maximum gate voltage (VGS = 1.2 V), the drive transistors
are still in saturation region. Therefore, the square of overdrive for the composite-20 and composite-27 transistors, for instance, can differ by about
2
2
( V GS – V T20 )
(
1.2
–
0.46
)
----------------------------------------- = -------------------------------- = 1.34 .
2
2
( V GS – V T27 )
( 1.2 – 0.56 )
(3-3)
As discussed, the voltage protection for the TN sub-transistor is degraded when its SDR
sub-transistor becomes shorter. To examine this important aspect of the composite MOS transistors  the subthreshold behaviors, ID-VGS curves are plotted in logarithm scale in Figure 3-11. In
the first case, the drain leakage current of composite-27 MOS transistor is well below that of the
conventional 1.2-V transistor. This is because the voltage at the shared diffusion region (VM(a)) is
well below 1.2 V. The 0.27 µm length for SDR sub-transistor is too long, and the drain current
increase is limited. For the composite-20 transistor, the drain leakage current around VGS = 0 V is
even higher than that of the 1.2-V transistor. When the drain is biased at 3.3 V, the 0.20-µm long
SDR sub-transistor did not sustain sufficient voltage drop so that the voltage at the shared diffusion is higher than 1.2 V and the drain current is increased. This leads to potential reliability
issues at the shared diffusion region inside the composite-20 transistor structure.
Between these two extreme cases, the composite-22 MOS transistor has the similar subthreshold characteristics as the 1.2-V transistor, including that for the worst case when VGS = 0 V.
This indicates that the voltage of the shared diffusion region goes up to 1.2 V. The 0.22-µm long
63
SDR sub-transistor provides sufficient voltage protection to the 0.12-µm long TN sub-transistor
for the whole 3.3-V operating range. This is also consistent with the threshold voltage measurement results which suggest that the channel formation is no longer hindered by the SDR sub-transistor.
The combination of channel lengths in the composite-22 transistor gives a better trade-off
between the drive current capability and the reliability property, and the composite-22 MOS transistor is the optimal for the use as the drive transistors in the 1.2-to-3.3-V level shifter circuits.
3.4.2 Voltage Handling Capability
The breakdown voltage (VBK) sets the maximum voltage that can be applied either across
the drain and source, or across the gate and drain. When VDS approaches the breakdown voltage,
drain current of the device increases rapidly, even jumps abruptly which should be always
avoided. Therefore, sufficient voltage margin should be reserved between the transistor’s operational voltage range and its breakdown voltages. The same measurement method for breakdown
voltage described in Section 2.3.2 is employed here for the composite transistors, and the results
are listed in Table 3-3 together with those of the conventional 3.3-V and 1.2-V MOS transistors.
While the threshold voltages are close to that of the conventional 1.2-V transistor, the
composite MOS transistors have comparable breakdown voltages as that of the 3.3-V transistor,
Table 3-3. Breakdown voltages for the composite transistors, and the conventional 3.3-V
and 1.2-V transistors
Transistors
VBK
(V)
comp-20
comp-22
comp-23
3.3-V
1.2-V
VGS=1.2
~8.9
~ 9.2
~9.5
~ 6.1
~ 3.4
VGS=0
~7.0
~9.0
~9.0
~ 7.5
~ 4.6
64
which is around two times that of the 1.2-V transistor. The breakdown voltages of composite transistors significantly increase when the SDR sub-transistors are added. The reason is that before
the VDS reaches the breakdown voltage, a large portion of the voltage is dropped across the SDR
sub-transistor, and the shared diffusion region is kept below the breakdown voltage of the 1.2-V
transistor. This in turn allows the drain nodes of the composite MOS transistors to be biased at a
higher voltage.
When the SDR sub-transistor is longer, the protection from or the voltage drop across the
SDR sub-transistor increases, therefore the breakdown voltage of the composite structure
becomes higher. Among the different composite structures, the composite-22 MOS transistor is
the shortest one which has sufficient breakdown voltage for 3.3-V supply operation. This high
voltage handling capability is combined with the low threshold voltage of the conventional 1.2-V
transistor.
Having the thin-oxide as part of the gate in the composite MOS transistor structures sets
the maximum gate-to-source voltage (VGS) to only 1.2 V. However, the asymmetric composite
structures, from the gate to the drain, make it almost ideally suited for the asymmetric voltage
swings in the 1.2-to-3.3-V level shifter circuits.
3.5 Composite MOS Transistor Capacitance Property
The speed performance of digital circuits usually is evaluated by propagation delay (τd),
as well as the rise time (τr) and the fall time (τf). Equation 2-3 indicates that both current drive
capability ( I o ) of preceding stage and gate capacitance (Cload) as the load to the preceding stage
determine the speed performance. The data compared in Section 3.4, however, are measured at
the same channel width (W) for all transistors. The transistor structures have different gate capac-
65
G1
D1
GND
GND
Composite
Transistors
3.3-V
Transistor
G3
D3
GND
GND
open
(no device)
D2
Figure 3-12.
D4
G2
G4
Layout of the AC test structures for the composite MOS transistor and
the open structure.
itance due to different channel lengths. For a fairer comparison of current drive capability, the
drain current should be normalized to the same gate capacitance.
The AC test structures of composite and conventional transistors are fabricated in the
same 0.13-µm CMOS technology mentioned in Section 3.4. All transistors have the same channel
width of 44.4 µm. Figure 3-12 shows the layout of four of these AC structures. The ground pads
(GND) are shared by two adjacent structures here due to the area efficiency consideration. The
gate capacitance are extracted from the measured S-parameters. An AC open structure is also
measured to remove the impact of the capacitance associated with the pad frame and metal connections. An HP8510C network analyzer and an AC probe station are employed in these measurements.
The measured gate capacitances of the composite and conventional 1.2-V MOS transistors
are plotted in Figure 3-13. It is shown that the gate capacitance of composite transistors has
approximately linear dependence on the length of the SDR sub-transistor. The y-axis intercept of
66
120
composite
1.2-V
y-intercept
200
Capacitance (fF)
Gate Capacitance (fF)
160
80
1.2-V
transistor
40
composite-22: 157fF
150
3.3-V: 117fF
100
1
0
0.0
0.1
3
f (GHz)
0.2
5
7
0.3
Length of SDR Sub-transistor (µm)
Figure 3-13.
Measured gate capacitance of the composite transistors with different
lengths of SDR sub-transistors, compared to those of the conventional
1.2-V and 3.3-V transistors.
the extrapolation line represents the total capacitance associated with the TN sub-transistor and
gate overlap in the SDR sub-transistor. And this intercept is as expected higher than the gate
capacitance of the conventional 1.2-V transistor, as labeled by the triangle in Figure 3-13.
The composite-22 MOS transistor has gate capacitance of 157 fF. This is compared to that
of the conventional 0.34-µm long 3.3-V MOS transistors in the inset of Figure 3-13. At the same
width, the composite-22 transistor has about 34% higher gate capacitance than the 3.3-V transistor (117 fF). The width of the composite-22 transistor should be only 74% of that of the 3.3-V
transistor to have the same gate capacitance. For instance, a 7.4-µm wide composite-22 transistor
should have the same gate capacitance of 26 fF as a 10-µm wide minimum-length 3.3-V transistor.
67
3.6 Composite-22 MOS Transistors for Level Shifter Application
A set of composite MOS transistors with varying length SDR sub-transistors has been
investigated in the preceding sections. Composite structures consisting of two sub-transistors in
series have higher current drive capability compared to the 3.3-V transistor because the effective
threshold voltages are lowered. At the same time, these composite transistors can handle higher
voltage swing at the drain nodes because the SDR sub-transistors sustain a large portion of the
drain-to-source voltage and provide the voltage protection for the TN sub-transistors.
When the SDR sub-transistor is shorter, the voltage drop across it becomes smaller and the
drain current of the composite structure becomes higher. On the other hand, the voltage protection
from the SDR sub-transistor tends to be diminished and drain voltage tolerance of the composite
structure is lower.
As discussed, the composite-22 MOS transistor consisting of a 0.12-µm long TN sub-transistor and a 0.22-µm long SDR sub-transistor is considered to be well suited for use in
1.2-to-3.3-V level shifter circuits. The thin-oxide layer in the composite-22 structure limits the
maximum gate-to-source voltage to only 1.2 V, and this still fulfills the voltage swing requirement
in the case of 1.2-to-3.3-V level shifter circuits. At the drain side of composite-22 transistor, the
breakdown voltage is comparable to that of a conventional 3.3-V transistor. The composite-22
MOS transistors are ready to replace the conventional 3.3-V MOS transistors (M15/M17 in
Figure 3-1) to improve the speed performance.
The composite-22 MOS transistor has the same drawn length as the conventional 3.3-V
transistor. Its threshold voltage is only 0.46 V, which is 0.26 V lower than that of the 3.3-V transistor (0.72 V). When M15 and M17 in Figure 3-1 are replaced by the composite-22 MOS transistors, the gate overdrive (VGS-VT = 1.2-VT) is increased by about 54%.
68
8.0
VGS=1.2V
comp-22, W=7.4µm, iiiCgg=26fF
3.3-V,wwiiW=10.0µm, Cgg=26fF
1.2-V,wwiiW=13.1µm, Cgg=26fF
ID (mA)
6.0
VGS=0.9V
4.0
2.0
0.0
0.0
VGS=1.2V
VGS=0.6V
VGS=0.9V
VGS=0.6V
VGS=0.3V
1.0
2.0
VGS=1.2V
VGS=0.9V
VGS=0.6V
VGS=0.3V
3.0
VDS (V)
Figure 3-14.
I D-VDS characteristics of the composite-22, conventional 3.3-V and 1.2-V
MOS transistors when gate capacitances (Cgg) are the same.
Considering the difference in unit gate capacitance for the composite-22, the conventional
3.3-V and 1.2-V MOS transistors, ID-VDS curves in Figure 3-14 are compared at different widths.
The transistor widths are 7.4, 10.0 and 13.1 µm, respectively, so that the gate capacitance, or the
capacitive loads to the preceding inverter stage, are all 26 fF. Biased at the same gate-to-source
voltage (VGS), the composite-22 MOS transistor can deliver more than 2 times the current of
3.3-V transistor.
In Figure 3-15, ID-VGS curves of the composite-22 and conventional 3.3-V transistors are
also compared. Once again, all drain currents were normalized by keeping the gate capacitance at
26 fF. In the log scale plots, the normal subthreshold behaviors are observed at both VDS=3.3 V
and VDS=0.05 V. At VDS=3.3 V, the off-state current for composite-22 is comparable to that of the
69
10-2
6.0
10-4
4.0
10-8
10-10
ID (mA)
ID (A)
10-6
comp-22, ”VDS=3.3V 2.0
comp-22, “VDS=0.05V
10-12
10-14
0.0
3.3-V, wwiiVDS=3.3V
3.3-V, wwiiVDS=0.05V
1.0
2.0
3.0
0.0
VGS (V)
Figure 3-15.
Comparison of I D-VGS curves for the composite-22 and conventional
3.3-V MOS transistors in linear and logarithm scales at fixed gate
capacitance, with VDS = 3.3/0.05 V.
1.2-V transistor at VDS=1.2 V (~1nA/µm). However, it is almost 4 decades higher than that for
the 3.3-V transistor. Because the number of I/O transistors used in an integrated circuit is limited,
the higher leakage should be tolerable. The linear scale plots show once again that ID of the composite-22 transistor is at least 2 times that of the 3.3-V transistor. The improvement of IDS at low
VGS is even more dramatic due to the lower threshold voltage of composite transistor. With its
drain connected to 3.3 V and gate swept from 0 V to 1.2 V, it is clearly shown by the shaded area
in Figure 3-15 that the composite-22 transistor can deliver larger current than the conventional
3.3-V transistor. This higher drain current at given gate capacitance suggests that the 3.3-V drive
transistors in the 1.2-to-3.3-V level shifter circuit (M15/M17 in Figure 3-1) can be replaced by the
composite-22 transistors to reduce the propagation delay.
70
3.7 Low-to-high Level Shifter Speed Performance
In the previous section, the composite-22 and the minimum length conventional 3.3-V
MOS transistors are studied. Based on the DC and AC properties from measurements, the proposed composite-22 transistor has higher drive current than the 3.3-V transistor. Cadence Spectre
simulator is used in this section to estimate the improvement in the speed performance for the
1.2-to-3.3-V level shifters when the 3.3-V drive transistors are replaced by the composite-22 transistors.
First, modeling of SDR-26 MOS transistors is necessary. Based on the conventional 3.3-V
transistor’s model, we built a model file to approximately describe the behavior of composite-22
transistor by modifying several parameters, such as gate oxide thickness (tox), threshold voltage
(vth0), mobility (u0) and saturation velocity (vsat). The simulation results match the 2.68 times
the drain current, and 1.34 times the gate capacitance of the conventional 3.3-V transistors at
fixed channel width. These modifications reflect the improvement of current drive capability discussed in Section 3.4.1 and the increase of gate capacitance measured in Section 3.5, respectively.
The same 1.2-to-3.3-V level shifter structure shown in Figure 3-1 is used for simulations.
Figure 3-16 shows the two simulated versions. Version A is the level shifter circuit using the conventional 3.3-V nMOS transistors as the drive transistors (M8A/M9A). Two conventional 3.3-V
pMOS transistors (M10A/M11A) are used as the cross-coupled load. The 3-stage conventional
1.2-V inverter chain (A1 through A3) preceding the level shifter generates the input signal, whose
shape is independent of the number of propagation stages. The 3-stage conventional 3.3-V
inverter chain (A5 through A7) is also used following the level shifter to maintain the same capacitive loading of each stage Tau98. In version B, all components are the same as version A, except
that the two drive transistors (M8B/M9B) are replaced by the composite-22 MOS transistors in
71
1.2-V inverter 3.3-V inverter
3.3V
M10A
A1
A2
A3
M11A
A4
A5
M8A
in
conventional 3.3-V
A6
A7
M9A
outputA outputA
level shifter A
version A
version B
outputB outputB
3.3V
M10B
B1
B2
B3
M11B
B4
B5
M8B
B6
B7
M9B
Composite-22
level shifter B
3.3-V circuitry
1.2-V circuitry
Figure 3-16.
Schematics of level shifter circuits in simulation. Version A uses
conventional 3.3-V MOS transistors as drive transistors; Version B uses
composite-22 MOS transistors as drive transistors.
order to tolerate the 3.3-V swing and deliver higher drain current to the following stage. The
width of composite-22 transistors in version B are only 74% of their counterparts in version A, so
that the stages A3 and B3 can see the same capacitive loads.
Figure 3-17 shows the input and output waveforms of both level shifters for the pull-down
and pull-up cases. In either Figure 3-17 (a) or Figure 3-17 (b), the input signals in those two ver-
72
outputA
outputB
outputB
input
τnB
outputA
τnA
A
outputA
outputB
outputB
outputA
input
τpB
τpA
B
Figure 3-17.
Comparison of the composite-22 and conventional 3.3-V MOS transistors
used in 3.3-to-1.8-V level shifters. (A) propagation delays in pull-down
case (τn), (B) propagation delays in pull-up case (τp).
sions are the same and overlaid on each other. This is because, in both versions, the drive transistors (M8A and M8B, M9A and M9B) give the same capacitive load to the preceding stages. The
same input signals with 1.2-V swing are delayed differently and shifted to output signals with
73
Table 3-4. Speed performance comparison of level shifters using the composite-22 and
conventional 3.3-V MOS transistors
version A
(conventional 3.3-V)
version B
(composite-22)
delay
improvement
pull-down delay (ps)
τnA = 124
τnB = 82
34%
pull-up delay (ps)
τpA = 165
τpB = 93
44%
fall time (ps)
τfA = 221
τfB = 119
46%
rise time (ps)
τrA = 194
τrB = 103
47%
3.3-V swing. The time differences of output signals for both pull-down and pull-up cases directly
show the improved speed performance of the level shifter implemented by using the composite-22 transistors over the conventional 3.3-V transistors.
The data extracted from the waveforms are listed in Table 3-4, including the pull-down
propagation delay (τn), pull-up propagation delay (τp), fall time (τf), and rise time (τr). A propagation delay improvement of around 40% can be expected from this 1.2-to-3.3-V level shifter circuit
by using the composite-22 MOS transistors instead of conventional 3.3-V transistors. This speed
improvement is obtained without any process modifications. In addition, there is no change in the
circuit configuration, and it is convenient for circuit designers to use.
3.8 Summary
Level shifters are crucial for digital CMOS I/O interface circuits to translate different voltage levels back and forth. The level shifting requires extra stages and introduces additional propagation delay, which should be limited to minimum. In a low-to-high level shifter, the drive
transistors have to be realized by using thick-oxide high-voltage MOS transistors to stand the high
voltage swing at the drain nodes. The gate nodes of drive transistors, however, only need to han-
74
dle low voltage swing. These requirements provide opportunities for use of the SDR thick-oxide
MOS transistors.
The composite MOS transistor structure using the SDR thick-oxide MOS transistor is proposed. With its asymmetric voltage characteristics from gate to drain, the composite transistor is
well suited as the drive transistors in the low-to-high level shifter circuits, since it can deliver
higher drain current than the conventional thick-oxide high-voltage MOS transistors.
The composite transistors using two different foundry CMOS processes are discussed in
this chapter. First, the composite-18 structure was implemented in a 0.18-µm CMOS foundry
technology. The potential reliability issues at the internal shared diffusion region is discovered,
and the criteria to monitor this problem is discussed. In the second implementation using a
0.13-µm CMOS technology, the measurements show that a 0.22-µm long SDR thick-oxide MOS
transistor in series with a conventional thin-oxide transistor (composite-22) is the optimal combination for use in the 1.2-to-3.3-V level shifter circuits. This composite-22 transistor can deliver
more than 2 times the drain current as the conventional thick-oxide transistors, while still having
sufficient breakdown voltages and protecting the TN sub-transistors for 3.3-V swing at the drain
node. This current enhancement translates to about 40% reduction in the propagation delay.
The use of composite MOS transistors in the low-to-high level shifters to improve the
speed performance is feasible in the 0.18-µm and 0.13-µm CMOS technologies. This concept
should be applicable in other more advanced technologies. In a more general term, this study on
low-to-high level shifters successfully demonstrates another application of the SDR thick-oxide
MOS structure, namely in digital I/O circuits. Further scaling of the thick-oxide MOS transistors
should be feasible to optimize the performance of digital I/O circuits.
75
CHAPTER 4
RADIO FREQUENCY POWER AMPLIFIER APPLICATION
4.1 Introduction
4.1.1 CMOS RF Power Amplifiers
A typical CMOS RF transceiver is shown in Figure 4-1. Along the transmitting path, the
power amplifier (PA) is the final active stage for delivering a sufficient amount of power through
the T/R switch and antenna to the propagation media. Because the RF signal level becomes the
largest level at this point, the design considerations and methods for PA are different from those
for other RF blocks for small signals.
In the design of CMOS power amplifier circuit, the output power level and power efficiency are two of the most important specifications. To deliver high power level signal, typically
the power amplifier itself becomes the most power-consuming block in the RF transceiver. Poor
power efficiency will cause self-heating problem, and large power consumption will shorten the
battery life for portable wireless communication devices. These performance will eventually be
limited by the power transistor characteristics, such as breakdown voltage, current limitations and
maximum power dissipation [Smi98].
Antenna
Transmitter
T/R Switch
PA
LO
Synthesizer
LO
Receiver
Figure 4-1.
Simplified block diagram of a typical RF transceiver.
76
IF and
Baseband
Circuits
In CMOS power amplifier design, two types of power efficiency are widely used: drain
efficiency (DE) and power added efficiency (PAE). Their definitions are as below:
P out
DE = -------------------- ,
P supply
(4-1)
P out 
P out – P in
P in 

1
PAE = -------------------------- = ---------------------  1 – ----------- = DE  1 – ------- .
P supply 
P supply
P out
G o

(4-2)
Psupply is the power consumption from the DC supply, Pin is the input power, Pout is the power
delivered the output load and Go is the power gain of the PA. If the power gain of the amplifier
(Go) is high enough (which is not always true for PA’s final stage), DE and PAE are close to each
other.
4.1.2 Classification of CMOS RF Power Amplifiers
Power amplifiers are classified according to their mode of operation, i.e. the bias condition
for power transistors and the nature of output network. Traditionally, there are several categories
of power amplifiers: class A, AB, B, C, D, E, F, etc.
Class-A power amplifiers are biased such that its conduction angle is 360°. The amplifier
operates linearly over the full input and output ranges. The output is the sinusoidal waveform of
the same frequency as the input, and the output amplitude is a linear function of the input amplitude. Among all PA’s categories, class-A power amplifier has the highest linearity and the poorest
efficiency. This type of amplifiers always consumes DC power even though there is no output signal. If the power amplifier is biased so that the conduction angle is between 180° and 360°, it is
referred to as class-AB. If the amplifier output is a linear function of the input over half (180°) of
the input waveform, then it is categorized as class-B. This mode of operation can have a greater
efficiency than class-A due to the reduced conduction angle. If the linear conduction angle is less
77
than 180°, it is a class-C power amplifier. From class-A to class-C power amplifiers, there is
increasing distortion in the output waveform, or the linearity of the amplifiers becomes worse.
A main source of power amplifier inefficiency is the dissipation in the power transistors.
Like a class-A amplifier, the current follows continuously through the MOS transistor while the
VDS is non-zero. If VDS can be made to zero while the current flows, there will be no power dissipation in a transistor and the drain efficiency (DE) will approach 100%. This is the basic idea
behind class-D, E, and F power amplifiers.
For power amplifiers under these categories, the power transistors usually operate in a
switching mode, and cooperate with the output network to reduce or eliminate the non-zero overlap between current and voltage waveforms at the drain node. The input signal waveform is not
preserved, just the frequency is. Therefore, these categories are also referred to as non-linear
power amplifiers.
4.1.3 Thick-Gate-Oxide MOS Transistors in Linear Power Amplifiers
Some wireless communication systems, like EDGE, WCDMA transceivers, have very
strict linearity requirements, therefore the linear power amplifiers are necessary. Class-A or AB
power amplifiers are often useful in these applications. However, as mentioned, the efficiency is a
serious concern. When the saturation voltage (VDSsat) is considered, the maximum drain efficiency for a class-A power amplifier is [Smi98]:
V DSsat  2
1
( DE ) max = ---  1 – ----------------.
2
V supply
(4-3)
For the case using the 3.3-V thick-oxide MOS transistor, Vsupply is 3 V and VDSsat is about 0.2 V,
therefore (DE)max is up to 44%. On the other hand, for the case of the 1.2-V thin-oxide MOS transistor, VDSsat doesn’t change much and it takes more percentage of the Vsupply (1 V). The effi-
78
ciency drops to 32%. For such power amplifier applications, high voltage MOS transistors are
preferable.
The composite MOS transistor (proposed in Chapter 3) has the high voltage handling
capability like a conventional 3.3-V MOS transistor, while its current drive capability is better
than the 3.3-V transistor when VGS is limited up to 1.2 V. In this chapter, we will examine the
high frequency capability of the composite-22 MOS transistor amplifiers. The better frequency
response could lead to higher power gain (Go), therefore, increasing the PAE of a power amplifier
in Equation 4-2.
4.2 AC Characteristics of Composite-22 MOS Transistor
4.2.1 fT and fmax
fT (cut-off frequency) and fmax (maximum frequency of oscillation) are often used as the
figures of merits for high frequency performance of a transistor. The small-signal model of a
MOS transistor is shown in Figure 4-2. Aside from the well-known lumped elements, two extra
elements are included. The charging resistance (ri) accounts for the distributed effect along the
channel, and its value is about 1/(5gm). The gate resistance here is split into an intrinsic part (Rg,i)
and an extrinsic part (Rg,e).
Rg,e
Cgd
Rg,i
+
vgs
ri
Cgs
gmvgs
rd
gds
Cdb
intrinsic transistor
Figure 4-2.
Small-signal lumped microwave network model of a MOSFET.
79
fT is defined as the frequency where the extrapolated current gain (h21) decreases to unity,
as expressed below:
h 21
i
= ----o
= 1,
f = fT
ii f = fT
(4-4)
where, ii is the input current and io is the short circuit output current. For this model, the cut-off
frequency can be written as [Man99]
gm
gm
f T = ----------------------------------------------------------------------- ≈ -------------- .
2
2 2πC g
2π C g – ( g m r i C gs – C gd )
(4-5)
Here, it is assumed that g m r i C gs – C gd << Cg, and Cg = Cgs+Cgd. fT has simple definition and is
easy to measure. However, fT does not provide the frequency response information for the transistor power gain.
fmax is the frequency where the maximum available gain (MAG) of a transistor is equal to
unity. It also represents the highest frequency that a transistor could possibly oscillate in a circuit.
The maximum available gain (MAG) is the power gain obtained by a device when the input and
output ports are conjugately matched to the impedance of the source and load simultaneously.
This figure of merit provides a fundamental limit on how much power gain one can achieve from
a device at a given frequency. Under the simultaneous conjugate match condition,
Γ S = Γ in∗ = Γ MS , Γ L = Γ out∗ = Γ ML , the maximum available gain can be written as
[Gon97]:
S 21
2
MAG = -----------  K – K – 1 .

S 12 
where K stands for Kurokawa’s stability factor and can be calculated by
80
(4-6)
2
2
2
1 – S 21 – S 12 + S 11 S 22 – S 21 S 12
K = ----------------------------------------------------------------------------------------------- .
2 S 21 S 12
(4-7)
When K is less than 1, MAG is not defined. This is the typical case that a transistor operates at
lower frequency range and is potentially unstable. When operating frequency is sufficiently high,
K becomes greater than 1 and MAG can be calculated from the S-parameters.
Another power gain called the unilateral power gain (Gmax) was also proposed in [Mas54]
to estimate the fmax. According to this definition, additional feedback network is introduced to the
transistor of interest so that there is no reverse transmission of signals from the output to the input
of this combined network (the transistor of interest, and the additional feedback network). For a
two-port network, the unilateral power gain (Gmax) is described by the y-parameters [Gup92]:
2
y 21 – y 12
1
G max = --- × --------------------------------------------------------------------------------------------------------- .
4 ( Re ( y 11 ) ⋅ Re ( y 22 ) ) – Re ( y 21 ) ⋅ Re ( y 12 )
(4-8)
Furthermore, by applying the transistor parameters accounted by the model shown in Figure 4-2,
the unilateral power gain (Gmax) can be expressed as
2
( fT ⁄ f )
G max ≅ -------------------------------------------------------------------------------------------- .
4R g, i ⋅ ( g ds + g m C gd ⁄ C g ) + 4r i g ds
(4-9)
It is reasonable to assume that ( R g, i + r i ) ⋅ g ds < R g, i ⋅ g m ⋅ C gd ⁄ C g for RF applications, and
the unilateral power gain (Gmax) can be further simplified as
fT
G max ≅ --------------------------------------- .
2
8πR g, i C gd ⋅ f
81
(4-10)
Ideally, Gmax has the dependence of 20dB/dec on frequency, and fmax can be simply expressed as
Equation 4-11
f max =
ft
----------------------------.
8πR g, i C gd
(4-11)
Interestingly, the frequency at which Gmax attains the unity is also the frequency at which
the MAG of the device becomes unity. Therefore, both power gains discussed above will be used
to estimate fmax.
4.2.2 Measurements for f T and fmax
The AC test structures of composite-22 and conventional 3.3-V thick-gate-oxide MOS
transistors discussed in Section 3.5 are used for fT and fmax measurements. As discussed, an AC
open structure is also measured to remove the capacitance associated with the pad frame and
metal connections. An HP8510C network analyzer and an AC probe station are employed. The
measurement frequency is up to 26GHz, which is limited by the network analyzer.
2
In Figure 4-3, h 21 , MAG and Gmax extracted from the S-parameters are plotted in a logarithm scale. For the composite-22 MOS transistor, the gate and drain are biased at 0.8 and 3.0 V,
respectively. For the conventional 3.3-V MOS transistor, the gate and drain are biased at 2.0 and
3.0 V, respectively. For MAG curves, each one has a turning point. For frequencies below this
turning point, the K factor in Equation 4-7 is less than 1, thus the calculated MAG is invalid.
When the frequency is higher than this turning point, K becomes greater than 1, therefore the
extracted MAG is valid. Interestingly, the valid portions of MAG curves merge with the Gmax
curves, and lead to the same fmax values.
82
25
20
h 21
15
turning
point
2
10
(K>1)
MAG (K<1)
2
h 21 , MAG, Gmax (dB)
Gmax
(K>1)
5
0
composite-22
3.3-V
-5
0.4
Figure 4-3.
1.0
Frequency (GHz)
10
40
Measured current gain (h21), maximum available gain (MAG) and
unilateral power gain (Gmax) for the composite-22 and conventional 3.3-V
thick-gate-oxide transistors.
The extracted fT and fmax for multiple samples are shown as function of gate bias condition in Figure 4-4. If VGS is below 1.2 V, the composite-22 transistor has higher fT than the 3.3-V
MOS transistor. fT of the composite-22 transistor reaches the peak value of 15 GHz at VGS=0.8 V.
However, this advantage is overturned when VGS of the 3.3-V transistor is increased above 1.2 V.
fT of the 3.3-V transistor reaches the peak value of 19 GHz at VGS=2.0 V. fmax of the composite-22 transistor reaches peak value of 29 GHz at VGS=0.8 V. While fmax of the 3.3-V transistor
reaches 37.5 GHz at VGS=2.0 V.
In general, the composite-22 MOS transistor has lower fT and fmax than the conventional
3.3-V transistor. However, this is not true if we consider the practical bias conditions at the transistor gate for an amplifier. When the overdrive (VGS-VT) is set to around 0.25 V, for instance, the
83
VT3.3V
40
VDS = 3.0V
comp
=3.0V
VVTDS
0.25V
fT and fmax (GHz)
fmax
fmax
0.25V
fmax
30
fmax
20
fT
fT
fT
fT
10
composite-22
composite-22
3.3-V
3.3-V
0
0.0
1.0
2.0
3.0
VGS (V)
Figure 4-4.
fT and fmax for the composite-22 MOS transistor and conventional 3.3-V
thick-gate-oxide transistors. Threshold voltages for both transistors are
labeled by VTcomp and VT3.3V. Gate overdrives of 0.25 V are also labeled.
composite-22 transistor has ~ 20% higher fT and comparable fmax compared to the conventional
3.3-V transistor. With better frequency response, the composite-22 MOS transistor may slightly
increase the gain of amplifiers (Go) and PAE as calculated in Equation 4-2. However, the
improvement by using composite-22 transistor is expected to be marginal, or even none for some
bias conditions.
There is another consideration of using composite-22 transistors in conventional analog
amplifier circuits. The intrinsic gain (gm⋅ro) is one of the key parameters to characterize amplifier
transistor, and it specifies the highest voltage gain that can be possibly provided by a transistor.
Compared in Figure 4-5 are gm, output resistances (ro) and intrinsic gain of the composite-22, conventional 3.3-V and 1.2-V transistors. The overdrives (VGS-VT) for all transistors are
84
gm (ms)
30
Composite-22
3.3-V
1.2-V
20
10
0
0.0
1.0
2.0
Output Resistance (kΩ)
3.0
Composite-22
3.3-V
1.2-V
2.0
1.0
0.0
0.0
1.0
2.0
40
3.0
Composite-22
3.3-V
1.2-V
30
gmro
3.0
20
10
0
0.0
1.0
2.0
3.0
VDS (V)
Figure 4-5.
gm, output resistance (ro) and intrinsic gain of the composite-22 and
conventional 3.3-V/1.2-V transistors when the overdrives (VGS-VT) are
around 0.25 V.
85
kept around 0.25 V. The transistor widths are scaled so that the drain currents for all transistors are
about the same. The composite-22 transistor has similar gm, but about 1/2 output resistance of the
conventional 3.3-V transistor. This low output resistance degrades the intrinsic gain, as well as
fmax, of the composite transistor. The intrinsic gain of composite transistor is about 1/2 that of the
3.3-V transistor. In addition, the 1.2-V transistor has only about 1/2 output resistance compared to
the composite transistor. However, the higher gm of 1.2-V transistor compensates so that its intrinsic gain is comparable to that of the composite transistor. Finally, the composite transistor doesn’t
show superior characteristics in conventional analog amplifier applications.
4.3 Summary
In this chapter, use of the composite-22 MOS transistor in RF power amplifier circuits is
examined. At first, the RF power amplifier circuit of a transceiver and its large signal characters
are introduced. Output power level and efficiency are the two of the most important specifications
for power amplifiers. Power amplifiers in different classes need compromises between the linearity and power efficiency. PA design in certain applications prefer high-voltage (thick-oxide) MOS
transistors due to the high breakdown voltages.
The composite-22 MOS transistor can handle the same drain voltage swing like the conventional 3.3-V MOS transistor. fT and fmax are measured for the device’s speed characteristics. In
general, the composite-22 MOS transistor is not superior to the conventional 3.3-V transistor.
When considering the practical gate bias conditions, the measurements show that the composite-22 MOS transistor has slightly higher fT and comparable fmax compared to the conventional
3.3-V transistor. Additionally, the composite transistor shows lower intrinsic gain than the 3.3-V
transistor. The composite transistors demonstrate only marginal, or even no advantages over the
3.3-V transistors for RF and analog amplifier circuits.
86
CHAPTER 5
TRANSMIT/RECEIVE SWITCH APPLICATION
5.1 Introduction
A high performance transmit/receive (T/R) switch is a key building block of the radio frequency (RF) front end of time-division duplexing (TDD) communication systems. In this chapter,
the potential use of thick-gate-oxide SDR MOS transistors in RF switch circuits in order to
improve the performance is discussed.
5.1.1 CMOS Transmit/Receive Switches
A simplified block diagram of a TDD RF transceiver is shown in Figure 5-1. Both transmitter and receiver are connect to an antenna (ANT) through a single-pole-double-through
(SPDT) T/R switch. Either a transmitter or a receiver is on one at a time. In receive mode, a T/R
switch connects the antenna to the receiver path, which usually starts with a low noise amplifier
(LNA) or a filter. The signal collected by the antenna which is very weak goes through the switch
and is fed into the LNA. The loss of T/R switch increases the noise figure of LNA by the same
Antenna
LNA
T/R switch
PA
Transmitter
Receiver
Figure 5-1.
T/R switch in a typical TDD RF transceiver.
87
amount. Therefore, the T/R switch should have low loss (<1 dB) to reduce its impact on receiver
sensitivity. In transmit mode, the T/R switch connects the antenna to the transmit path or power
amplifier (PA). The T/R switch should handle high power signal without excessive distortion and
loss. Obviously, high power handling capability and low loss are desirable for the T/R switch.
Also, the T/R switch must have sufficiently high isolation to block the transmit signal from being
fed into the input of receiver.
Key figures of merit for a T/R switch include insertion loss (IL), isolation, return loss, and
power handling capability. The insertion loss measures the power loss through the switch when
the switch is on. At off-state, the switch loss is characterized by isolation. By measuring two-port
S-parameters of a switch, insertion loss and isolation can be expressed as Equation 5-1, or 5-2 in
dB.
1 - , or
IL, isolation = -----------2
S 21
(5-1)
( IL ) dB, ( isolation ) dB = – 20 log ( S 21 ) .
(5-2)
Return loss measures how much power is reflected back from any ports of the switch. This parameter describes how severe the mismatch at the port is and can be expressed using Equation 5-3, or
5-4 in dB.
1
returnaloss = ------------- , or
2
S 11
(5-3)
( returnaloss ) dB = – 20 log ( S 11 ) .
(5-4)
Power handling capability of a switch is usually represented by its 1-dB compression point
(P1dB), or the input referred one (IP1dB). P1dB is defined as the output power where the power
88
gain of switch drops from the small signal power gain by 1 dB. Higher P1dB denotes a higher
power handling capability. This parameter is fundamentally determined by the non-linearities of
the switch. Another parameter commonly used to characterize the linearity of a switch is the
third-order intercept point (IP3 or input referred one IIP3). This parameter is defined as the power
level at which the linearly extrapolated output power of desired signal and that of the third order
intermodulation component intersect. The input referred IP3 is denoted as IIP3.
Using CMOS technology, potentially all RF front end and baseband circuits can be integrated into a single chip. This has been the motivation of tremendous effort for finding ways to
implement high performance RF building blocks in bulk CMOS technologies. However, the commercial RF switch modules are implemented almost exclusively in GaAs technology. This has
impeded the fully exploiting the low cost potential of CMOS solutions.
Mobility of electrons in silicon is only ~ 1/6 of that in GaAs [Sze02]. Compared to GaAs
devices, CMOS transistors have higher channel sheet resistance (ρch), which is directly related to
the switch’s insertion loss. The insertion loss increases with higher channel resistance (Rch). And
L
the channel resistance is equal to ρ ch ⋅ ----- . However, the channel width (W) can not be arbitrarily
W
increased because a larger source/drain area increases the capacitance. This increases the switch
loss because of the associated substrate resistance.
Combatting the substrate loss is another design requirement in RF CMOS switch design.
To lower the insertion loss in CMOS technology, channel length (L) needs to be scaled down.
Since the parasitic capacitance is also reduced with scaling, the insertion loss improves
[HuaF01b]. However, technology scaling inevitably reduces the transistor breakdown voltage
which is already relatively low. This makes it even more difficult to achieve high power handling
performance.
89
In such a junction isolated silicon technology, one more challenge in designing high power
switches is the possibility of forward biasing the source/drain-to-body junction diodes during
large voltage swings at the input and output of the switch [Lar98]. These forward biased junctions
will distort the output signal, thus limit the power handling capability (IP1dB). This may also
inject minority carriers into the body of the nearby transistors and trigger latch-up. Even after
applying DC bias at source/drain to increase the reverse bias of the those junctions, the power performance of CMOS switches is still limited to around 20 dBm.
The 30-dBm RF signal, for instance, corresponds to a ~ 20-V peak-to-peak voltage swing
at the input and output ports of a T/R switch with termination of 50-Ω load. If directly applied to
MOS transistor nodes, such high voltage swing could easily forward bias the junctions of MOS
transistors, and even damage the transistors. In CMOS processes, it is extremely difficult to
deliver power in excess of 30 dBm through a T/R switch.
5.1.2 Techniques to Improve Power Handling Capability
With the continuous speed improvement of technologies from generation to generation,
bulk CMOS radio-frequency (RF) transceivers and power amplifiers have proven to be production worthy. To date, an RF CMOS block which has not found wide spread use is a transmit/
receive (T/R) switch [HuaF01a, HuaF04]. Key reasons for this are that bulk CMOS switches have
limited power handling capability as measured by input referred 1-dB compression point (IP1dB)
and relatively high insertion loss (IL). The power handling capability can be improved while
slightly degrading IL by connecting the body nodes of NMOS transistors through high resistance
[Li03, Ohn04]. By making the high impedance connection to the body using a parallel LC tank,
IP1dB of 28.5 dBm and IL of 1.5 dB have been achieved at 2.4 GHz [Tal04]. It has been suggested
that similar performance should be achievable by using NMOS transistors in isolated p-wells of
90
triple well CMOS processes while eliminating the need for the LC tank which consumes a significant area and makes the switch narrow band. However, to date, the highest IP1dB reported for
switches using isolated p-wells is only 20 dBm with IL of 1.1 dB at 5.8 GHz [Yeh05].
The work presented in this chapter demonstrates the techniques for increasing IP1dB of T/
R switches well beyond 20 dBm using NMOS transistors in isolated p-wells, while reducing the
insertion loss degradation. The techniques are used to demonstrate a 900 MHz single-pole-double-throw (SPDT) switch with IP1dB of 31.3 dBm, and IL’s of 0.5 and 1.0 dB in transmit (TX) and
receive (RX) modes. Isolation is better than 29 dB up to 1 GHz. The techniques are also utilized
to demonstrate a 2.4 GHz SPDT switch with IP1dB of 28 dBm, and IL’s of 0.8 and 1.2 dB in TX
and RX modes. Isolation is better than 24 dB up to 2.4 GHz. The switches are fabricated using the
transistors of UMC 130-nm mixed mode CMOS process with a thicker gate-oxide layer in order
to reliably support the required voltage swing.
5.2 CMOS T/R Switches Using Sub-Design-Rule Transistors
5.2.1 Design of SDR T/R Switches
The switch circuit schematic is shown in Figure 5-2. It is formed with a series transistor
M4 (Width = 925 µm) on the TX leg and 3-stack series transistors M6-M8 (Width = 1115 µm) on
the RX leg, and 3-stack shunt transistors M1-M3 (Width = 370 µm) on the TX node, and a shunt
transistor M5 (Width = 370 µm) on the RX node. The gate and body nodes of all transistors are
biased through 10-kΩ non-silicide polysilicon resistors (R’s in Figure 5-2). TX and RX nodes as
well as the sources of M1 and M5 are biased at 3V to improve the power handling capability
[HuaF01a]. The switches were turned on and off by varying the control voltage (G_TX, G_RX in
Figure 5-2) from 2 to 6 V [HuaF01a]. The switch can be controlled using a circuit similar to that
in [Poi03] and the control voltages can be generated using a voltage doubler [Poi03].
91
G_RX
G_TX
ANT
R
TX
M4
C4
R
C3
R
R
C5
M3
R
M8
R
C6
R
R
M7
R
R
M6
RX
R
R
R
R
M5
G_RX
R
M2
R
M1
C2
C1
Figure 5-2.
G_TX
Simplified schematic of the T/R switch with 3-stack sub-design-rule
(SDR) length transistors.
The stacked shunt transistors M1-M3 and series transistors M6-M8 are used to sustain
higher voltage swings and therefore to improve the power handling of T/R switch [McG91,
Ohn04, Sch90]. Stacking, however, significantly increases the IL of RX leg. Based on the discussions in Chapter 2, it is possible to reduce the channel length of thick-gate-oxide transistors below
that permitted by the design rule to lower the on-resistance thus reducing the IL degradation.
To exploit this, all the transistors were implemented using 3.3-V transistors with a
sub-design-rule (SDR) channel length [Xu05]. The drawn length of SDR transistors in this switch
design is 0.26 µm instead of 0.34 µm required for 3.3-V transistors. DC measurements indicate its
on-resistance is reduced by ~ 25%. Since the gates of 3.3-V and 1.2-V transistors are simultaneously formed, the SDR channel length transistors can be formed without any process modifications. This switch does not utilize impedance transformation to increase IP1dB [HuaF04] and the
peak-to-peak voltage the switch must handle is ~20 V at 30-dBm input power.
92
DNW
p-well
p-well
p-well
deep-n-well
deep-n-well
deep-n-well
Figure 5-3.
Cross-section of the 3-stack transistors in the SDR T/R switch.
Each NMOS transistor of the switch is located in an isolated p-well (Figure 5-3) to allow
the body node to float and follow the RF signal thus increasing IP1dB [Li03,Ohn04,Tal04,Yeh05].
This is similar to the phenomenon that happens in switches fabricated in GaAs as well as silicon
on sapphire (SOS) and silicon on insulator (SOI) processes [Miy95,Joh97,YamK99,Tin03]. To
ensure the isolated p-wells are not AC grounded through the series combination of
p-well-to-deep-n-well and deep-n-well-to-p-substrate junction capacitances (~ 1 pF), the substrate
resistance is increased by using the p-well implantation block (width of ~20 µm), using a small
number of substrate contacts (4 per transistor), and adding a 1-kΩ resistor in series with the substrate contacts as shown in Figure 5-3.
Even after applying these measures, the body nodes of MOSFET’s are not perfectly isolated. Figure 5-4 shows a more detailed schematic for the stacked transistors M1-M3. The shunt
paths from body to AC ground consisting of Cwell’s due to the series combination of
p-well-to-deep-n-well and deep-n-well-to-p-substrate junction capacitances, and substrate resistances (Rsub1 - Rsub3) make the voltage swing unevenly distributed among these 3-stack MOS-
93
VDG3
-
+
M3
VSG3
G_RX
VDG2
-
+
+
-
10kΩ
+
+
M1
VSG1
Rsub3
Cwell
VD1
10kΩ
parasitic
shunt
paths
Cwell
VD2
10kΩ
M2
VSG2
VDG1
VTX
Rsub2
Cwell
+
Rsub1
VS1
C1
Figure 5-4.
Detailed schematic of the 3-stack transistors (M1-M3) including the
parasitic shunt paths.
FET’s. These shunt paths reduce the voltage swing across the drains and gates of M2 and M1,
while increasing the swing across the drain and gate of M3. This is clearly seen as the grey curves
in Figure 5-5(a) which shows the simulated drain-to-gate voltages of M1-M3. The input power
level is 30 dBm. In general, the top transistors M3 and M8 sustain higher gate-to-body and
drain-to-gate voltages than the bottom transistors M1 and M6.
Building on the feed-forward technique proposed for GaAs T/R switches [Miy95], the
switch in this work incorporates feed-forward metal capacitors (C3=C4=50 fF and C5=C6=150
fF) between the drain and body nodes, and between the drain and gate nodes of M3 and M8. The
extra capacitances (1X case) reduce the impedance across the gates and drains of M3 and M8, and
94
4.5
VDG3
with cap (1X)
Voltage (V)
without cap
2.5
VDG2
VDG1
0.5
-1.5
Vsg_M2
0
T/2
Time
T
A
13.0
Voltage (V)
VTX
VDS3
VD2
8.0
VDS2
VD1
3.0
VDS1
VS1
-2.0
with cap (1X)
without cap
-7.0
0
T/2
Time
T
B
Figure 5-5.
Voltage distributions for the 3-stack SDR switches with and without the
feed-forward capacitors, when the input power is 30 dBm. (A) Drain-togate voltages (VDG1~VDG3) for transistors M1-M3. (B) Voltage
waveforms at different nodes along the TX shunt path (M1-M3).
95
help the gate nodes follow the high swing nodes more closely. This makes the voltage swing at
TX and ANT nodes more evenly distributed among the 3 stacked MOSFET’s.
Also shown in Figure 5-5(a) is the simulated drain-to-gate voltages of M1-M3 with 1X
feed-forward capacitors (C3-C6). With the help of feed-forward capacitance, the voltage drop
across M3 is reduced by about 1 V, while those across M2 and M1 sustain larger portions of the
total input voltage. Figure 5-5(b) shows the simulated voltages of drain nodes for M1-M3 once
again at input power of 30 dBm. The maximum voltage including the 3-V DC bias is 13 V.
Despite this, the peak voltage drops across gate oxide (Figure 5-5(a)) and between drains and
sources (Figure 5-5(b)) are ~ 3.5 V to ensure reliable operation when feed-forward capacitors are
used. This modification of voltage distribution among M1-M3 enables the stack as a whole to
withstand a larger voltage swing before any one is turned on or damaged. The feed-forward metal
capacitors (C3-C6) are formed using metal layers 1 through 3 and incorporated as part of the transistor layout.
Simulated drain-to-gate and source-to-gate peak voltages for M1-M3 (VDG1p ~ VDG3p,
VSG1p ~ VSG3p) versus different feed-forward capacitance are plotted in Figure 5-6. The values of
feed-forward capacitors (C3-C6) are varied among 0, 1X (C3=C5=50 fF and C4=C6=150 fF), 2X
and 3X. It shows again that, when the feed-forward capacitors (1X) are added, the drain-to-gate
peak voltages of transistors M1-M3 are closer to each other, therefore, the voltage swings are
more evenly distributed. The peak voltage of M3 is reduced from over 4.6 V to 3.8 V, which is
tolerable for the 3.3-V thicker gate oxide transistor. The drain-to-gate peak voltage of M3 (VDG3p
in Figure 5-6) and the resulting stress can be further reduced by increasing the feed-forward
capacitances.
96
Peak Voltage (V)
5.0
4.0
VDG3p
VSG3p
VDG2p
VSG2p
VDG1p
VSG1p
3.0
2.0
1.0
0X
Figure 5-6.
C3=C4=50 fF
C5=C6=150 fF
1X
2X
Feed-forward Capacitance
3X
Impact of feed-forward capacitance (0X, 1X, 2X and 3X) on the peak
voltages across transistors M1-M3 (VDG1p~VDG3p, VSG1p~VSG3p).
Larger feed-forward capacitance, however, increases the portion of total voltage swing
applied across the gate oxide layer of M1, and eventually, M1 becomes the most stressed transistor among the three stacked transistors. There is an optimal value for the feed-forward capacitor to
evenly distribute the voltage across the 3-stack transistors. Figure 5-6 suggests that the voltage
distribution is better balanced when the capacitance is doubled (2X case). If the capacitance is tripled (3X case), the peak voltage across M1 (VSG1p) becomes larger than that of M3 (VDG3p).
Compared to the switch without feed-forward capacitance, the simulations suggest about 1.5 and
2.3 dB increases in IP1dB at 900 MHz for the 1X and 2X cases.
A potential side effect of increasing C3-C6 is the degradation of insertion loss resulting
from the increases of losses due to input mismatch and through the transistor stack. Simulations
show that IL at 900 MHz increases by 0.03 and 0.08 dB for the 1X and 2X cases. An optimal
feed-forward capacitor values should be between 1X and 2X. In this work, 900-MHz switches
97
with no feed-forward capacitors and that with C3=C4=50 fF and C5=C6=150 fF (1X case) are
fabricated and compared in Section 5.2.2.
The impedances of polysilicon resistors in Figure 5-2 are almost constant with frequency
up to several GHz, while the impedances of parasitic capacitors are frequency dependent. At sufficiently low frequencies, the floating-body resistances are not high enough compared to the
impedances of capacitive voltage divider structures. Therefore, the voltage division among
M1-M3 and among M6-M8, as well as power handling capability is expected to be weakly dependent on frequency. For the 900 MHz switch, the simulated power handling capability is almost
flat from ~ 650 MHz to ~ 2.4 GHz. In this range, IP1dB varies by +/- 1 dB, demonstrating the
broadband characteristics.
Lastly, two 20-pF bypass capacitors (C1 and C2) connect the sources of M1 and M5 to AC
ground, while blocking DC current flow. The inter-metal shuffled metal capacitor structure
[Sow01] consisting of metal layers 1 to 8 is used here for high chip area efficiency.
5.2.2 900-MHz SDR T/R Switch
A T/R switch operating at 900 MHz using such 3-stack SDR transistors (as shown in
Figure 5-2) was implemented in the UMC 130-nm mixed mode triple-well CMOS technology. A
die photograph of the circuit is shown in Figure 5-7. The active area is about 300 µm by 380 µm
or ~ 0.11 mm2. Including the additional area of voltage doubler circuitry with a 200-pF capacitor
(< 0.05 mm2), the SDR switch is still almost 3.5 times smaller than the area of the switch using an
LC-tank connection to the body node [Tal04].
Three GS/SG probes with 150-µm pitch were used at the RF signal ports for all measurements. A 6-pin DC probe was used to provide bias and control signals. One of the three ports was
terminated with a 50-Ω load through an AC coupling capacitor in the measurement setup.
98
Figure 5-7.
Die photo of the 3-stack SDR T/R switch.
Two-port S-parameters are measured using an HP8510C network analyzer. Figure 5-8
shows the measured IL of the SDR CMOS T/R switch. At 900MHz, IL’s for TX and RX legs are
0.5 and 1.0 dB, respectively. A T/R switch using only 2-stack 0.34-µm length MOSFET’s instead
of 3-stack 0.26-µm length SDR transistors is also measured for comparison. The length of 0.34
µm is the minimum allowed by the design rules for 3.3-V transistors. Its IL of RX leg is ~0.2 dB
higher than that for the switch using 3-stack SDR channel length transistors. Isolation and return
loss of SDR CMOS T/R switch as shown in Figure 5-9 are better than 29 dB and 20 dB at 900
MHz, respectively.
Linearity measurements were carried out using an HP-E4421B signal generator together
with an external power amplifier and an HP8563E spectrum analyzer. Figure 5-10 shows the measurement results of SDR CMOS T/R switch at 900MHz. IP1dB at TX mode is about 31.3 dBm,
99
2.5
3-stack of SDR transistors (0.26 µm)
Insertion Loss (dB)
2.0
1.5
RX
1.0
0.5
0.0
0.5
Figure 5-8.
2-stack of 0.34-µm 3.3-V transistors
TX
1.0
1.5
2.0
Frequency (GHz)
2.5
3.0
Measured insertion loss of the SDR switch using 3 stack SDR transistors,
compared to that of the switch using 2 stack 0.34-µm length transistors.
which is the highest ever reported for bulk CMOS T/R switches. As mentioned, TX and RX nodes
as well as the sources of M1 and M5 are biased at 3V, and the switches were turned on and off by
varying the control voltage from 2 to 6 V. Compared to IP1dB for the switch using 2-stack
40
3-stack of SDR transistors
40
Isolation (dB)
30
30
RX
TX
20
20
Return Loss (dB)
TX
RX
10
0.5
Figure 5-9.
1.0
1.5
2.0
2.5
Frequency (GHz)
10
3.0
Measured isolation and return loss for the SDR T/R switch using 3 stack
SDR channel length transistors.
100
20
20
-40
-60
-80 0
10
20
IP1dB = 31.3 dBm
-20
Vbias=3V
w/o cap
Vbias=0V
3rd order
IP1dB = 30 dBm
0
30
IIP3 = 42 dBm
40
IP1dB = 26 dBm
Pout (dBm)
40
0
-20
-40
-60
40
-80
Pin (dBm)
Figure 5-10.
Linearity measurement results of the 3-stack SDR switch with source/
drain biased at 3 and 0 V, and with (1X) and without the feed-forward
capacitors.
0.34-µm length MOSFET’s, this value is about 5 dB higher. These clearly illustrate the benefits of
using SDR transistors. IIP3 of the SDR CMOS switch is 42 dBm. When the source and drain
nodes are biased at 0 V, IP1dB drops to 26 dBm due to forward biased junctions. The linearity of
the SDR CMOS T/R switches with and without the additional feed-forward capacitors are also
compared in Figure 5-10. The additional capacitors improve IP1dB for the SDR switch by about
1.3 dB.
Finally, to examine the reliability characteristics, the SDR CMOS T/R switch is stressed
around IP1dB (31.3 dBm) for 10 hours. The stress was carried out for both conditions when ANT
pad is connected to a 50-Ω load and when it is left open to examine the effects of antenna mismatch. The measured S-parameters showed no difference before and after the stresses. This
experiment verifies that the 3-stack switch circuit using SDR MOS transistors can successfully
handle more than 31-dBm RF signal without reliability problems.
101
5.2.3 2.4-GHz SDR T/R Switch
In the 900-MHz T/R switch, 3-stack transistor structure was chosen and the power handling capability was significantly improved. On the other hand, the necessary stacking limited the
insertion loss performance at the switch’s RX leg. The 900-MHz switch demonstrated reasonable
insertion loss (< 1 dB) only up to ~ 1 GHz. There is design trade-off between IP1dB and IL, or
alternatively between IP1dB and operating frequency because IL increases with frequency. If
power handling requirement of a T/R switch can be relaxed to some extent, fewer number of
stacked transistors can be used so that IL performance can be improved. Furthermore, such a T/R
switch can potentially operate at higher frequencies while keeping the same acceptable IL performance. To further investigate such design trade-off, a 2.4-GHz T/R switch for wireless LAN
(WLAN) applications using SDR transistors has been implemented and presented in this section.
G_RX
G_TX
ANT
R
M4
TX
R
R
R
M7
R
R
R
M6
R
R
M2
RX
R
M5 G_TX
G_RX
R
R
M1
C2
C1
Figure 5-11.
Simplified schematic of the T/R switch for 2.4-GHz applications using
2-stack SDR transistors without feed-forward capacitors.
102
ANT
TX
M4
M7
M6
M2
M5
M1
C2
C1
S/D
Figure 5-12.
G_TX
RX
Body
G_RX
Sub
NW
Die photo of the T/R switch for 2.4-GHz applications using 2-stack SDR
transistors without feed-forward capacitors.
By using these techniques discussed in Section 5.2.1, an SDR T/R switch operating at 2.4
GHz was designed and implemented in the same CMOS foundry process. Figure 5-11 shows the
simplified schematic of this 2.4-GHz T/R switch. In this case, 2-stack SDR transistors (M1-M2
and M6-M7) are chosen to compensate the increased insertion loss along the RX leg at 2.4 GHz,
however, with its power handling capability compromised. The die photo of such T/R switch circuit is shown in Figure 5-12, and its active area is about 300 µm by 300 µm or ~ 0.09 mm2.
Once again, the two-port S-parameters are measured using an HP8510C network analyzer
and shown in Figure 5-13. It clearly indicates that the IL at RX leg is shifted down by stacking
only two SDR transistors and this switch yields acceptable performance even at higher frequencies. The measured insertion loss at 2.4 GHz is about 0.8 and 1.2 dB for TX and RX legs, respectively. Its isolation performance at 2.4 GHz is better than 24 dB. Large-signal performance is also
103
characterized as plotted in Figure 5-14. Measured at 2.4 GHz, its IP1dB is greater than 28 dBm,
which is ~ 3dB lower than that of the 3-stack switch circuit.
4.0
40
TX
3.0
30
RX
2.0
20
RX
1.0
Isolation (dB)
Insertion Loss (dB)
2-stack SDR
TX
0.0
0.5
1.0
1.5
2.0
10
3.0
2.5
Frequency (GHz)
Figure 5-13.
Measured insertion loss and isolation of the 2-stack SDR switch for
2.4-GHz applications.
30
2-stack SDR
@ 2.4 GHz
10
28 dBm
Pout (dBm)
20
0
-10
Figure 5-14.
0
10
20
Pin (dBm)
30
IP1dB measurement of the 2-stack SDR switch working at 2.4 GHz.
104
In this design, power handling capability is sacrificed for better loss performance, or for
higher operating frequency. Using SDR MOS transistors, a T/R switch with better combination of
power and loss performances is achieved for 2.4-GHz wireless application. The insertion losses of
0.8 and 1.2 dB for TX and RX legs at 2.4 GHz are the lowest reported to date for a bulk CMOS
switch with IP1dB greater than 25 dBm. It is also noted that this 2.4-GHz SDR T/R switch does
not use feed-forward capacitance for transistors M2 and M7. Based on the experience of the
3-stack T/R switches in Section 5.2.1, IP1dB of this 2-stack switch is expected to increase further
by about 1 dB when properly sized feed-forward capacitors are used. The performance of this
2.4-GHz and other T/R switches discussed are summarized and compared in Table 5-1.
Table 5-1. Performance summary of CMOS T/R switches.
T/R
switches
3-stack
SDR w/
cap
3-stack
SDR w/o
cap
2-stack
0.34-µm
2-stack
SDR w/o
cap
work
[Ohn04]
work
[Tal04]
work
[Yeh05]
Frequency
(GHz)
0.9
0.9
0.9
2.4
5.0
2.4
5.8
TX
0.5
0.5
0.5
0.8
1.0
1.5
1.1
RX
1.0
1.0
1.2
1.2
1.4
1.6
1.1
Return
Loss (dB)
>20
>19
>19
>13
>17
>12
-
Isolation
(dB)
>29
>29
>31
>24
>22
>17
27
IP1dB
(dBm)
31.3
30
26.5
28
22.7
28.5
20
IIP3 (dBm)
42
-
-
-
-
-
-
chip area
(mm2)
0.11
0.11
0.09
0.09
<0.1
0.56
0.03
IL
(dB)
105
5.3 Discussion
The output power of these SDR T/R switches is normal functions of the available input
power, as long as the input power is kept below IP1dB. When the nominal input power level is sufficiently high, however, the output power of switches abruptly drops and then saturates with the
available power from source. This effect sets the limit on the switch power handling capability.
This behavior is reversible in that when the input power is lowered again, the output power recovers. The measurement results for the 900-MHz SDR T/R switch (Figure 5-10) are magnified in
detail and shown in Figure 5-15.
This output power level drop has weak dependence on the bias conditions of drains/
sources, p-wells and deep n-wells. As shown in Figure 5-16, the measured leakage current
through the vertical drain/source-p-well-n-well-p-sub path is only on the order of 1 mA, which is
much smaller compared to that flowing through the switch transistors (peak current of ~ 200 mA).
32
31
Pout (dBm)
30
29
28
27
IP1dB
26
25
24
25
Figure 5-15.
26
27
28 29 30
Pin (dBm)
31
32
33
Detail of linearity measurement results around 1-dB compression point for
the 3-stack SDR switch. Output power drops abruptly if the nominal input
power is above certain point.
106
10.0
Current (mA)
8.0
6.0
4.0
2.0
0.0
0
Figure 5-16.
2
4
6
8
Voltage (V)
10
12
Measured DC current through the n-p-n-p sandwich structure from source/
drain, through body to p-substrate.
Furthermore, cutting off all the shunt transistors (M1-M3 and M5) from the circuit using a
focused ion beam had almost no effect on the power drop. The only change that significantly
affected the power level at which the drop occurred is leaving the RX node floating instead of terminating with a 50-Ω load after cutting off all the shunt transistors. Under this condition, the measured power drop occurs at ~5-dB higher input power level. The low current through the vertical
drain/source-p-well-n-well-p-sub path and the strong dependence on RX node termination suggest that the power drop is not caused by latch-up phenomenon.
Instead, we believe that the cause is the breakdown of 3-transistor stacks (M1-M3 and
M6-M8). The breakdown characteristics of a single SDR transistor is measured and shown in
Figure 5-17. It is noted that the breakdown voltage decreases with VGS. When the voltage swings
at TX and ANT nodes are small, the capacitively coupled voltage swings at the gates, thus VGS,
are also small. Therefore, each SDR transistors can tolerate higher voltage swing without con-
107
40
breakdown
region
ID (mA)
VGS=0.7
0.6
20
0.5
0.4
0.3
0
0.0
Figure 5-17.
2.0
4.0
VDS (V)
0.2
6.0
0.1
8.0
Measured breakdown characteristics of a single SDR transistor.
ducting measurable current. When the input voltage swing is sufficiently increased, the coupled
voltage swing at gate weakly turns on the devices and simultaneously lowers the breakdown voltage. This clamps the output voltage and power at a reduced level. An associated abrupt impedance change also causes power mismatch at the switch input and contributes to the sudden output
power drop. This can be proved by observation that a sudden power change at the switch’s input
port occurs at the same time when the output power abruptly drops. Interestingly, when the available power from source is then reduced, the measured output power follows a different path
(labeled by stars in Figure 5-15). This is because the breakdown voltage is still low and mismatch
is sever until the RF signal power, thus the gate-to-source voltage swing, is low enough. Then the
breakdown voltage increases and the output power follows the input linearly again.
A positive consequence of this power drop and clamping is that when the switch is
severely mismatched, the resulting high voltage will be clamped, thus protecting the switch from
permanent damages.
108
5.4 Summary
A T/R switch is usually the first building block in a TDD (Time Division Duplex) radio
system. Its performance is crucial to both the transmitter and receiver operations. The key parameters to characterize a CMOS T/R switch have been introduced. The current techniques to
improve the performance and the inherent process limits of switches implemented in CMOS technologies have been discussed.
In this chapter, the focus of our investigation is the use of the SDR NMOS transistors in
radio frequency T/R switch circuits. Design techniques for improving the power handing capability of bulk CMOS T/R switches to above 30 dBm while maintaining acceptable insertion loss
have been demonstrated using the UMC 130-nm mixed-mode triple-well CMOS technology.
Stacked sub-design-rule (SDR) channel length NMOS transistors with a thicker gate oxide layer
are used to improve the power handling capability while keeping IL low. Use of a thicker gate
oxide layer of 3.3-V transistors in SDR transistors enables ~3.5-V drop across the transistors
without reliability concerns. Isolated p-wells and p-well blocks are used to improve the floating-body effect.
At 900 MHz, a switch incorporating 3-stack SDR transistors located in isolated p-wells
exhibits IP1dB of 30 dBm. By using feed-forward capacitors, IP1dB is increased to 31.3 dBm. The
power handling capability is limited by a new mechanism. A decrease of drain-to-source breakdown voltages of the TX shunt and RX series stacked transistors due to un-intentional turning-on
of the transistors by RF input is suggested as the likely cause for a sudden output power drop. The
switch achieves 0.5-dB and 1.0-dB insertion losses in the transmit and receive modes. This switch
has 0.2 dB lower insertion loss in receive mode and 5 dB higher IP1dB in transmit mode compared
to that for a switch using 2-stack design rule compliant 3.3-V transistors. At 2.4 GHz, a switch
109
utilizing 2-stack SDR transistors exhibits IP1dB of 28 dBm. The insertion losses for transmit and
receive modes are 0.8 and 1.2 dB, which should be acceptable for 802.11b and g applications.
Lastly, this work suggests that integration of a bulk CMOS T/R switch for cellular applications is
a realizable goal by using thick-gate-oxide SDR MOS transistors.
110
CHAPTER 6
HIGH-Q MOS VARACTOR APPLICATION
6.1 Introduction
In preceding chapters, use of the sub-design-rule (SDR) MOS structures in transistors for
different circuit applications and their benefits have been demonstrated. Actually, an SDR MOS
structure is naturally a high quality varactor. This is because thick-gate-oxide layer has smaller
gate capacitance, and furthermore, using sub-design-rule channel lengths for MOS varactors can
reduce the series resistance. In this chapter, the performance of SDR MOS varactor structures are
presented and compared to those of conventional thin-gate-oxide MOS varactors.
6.1.1 CMOS Voltage-Controlled Oscillator
Local oscillators (LO) generate periodic output signals for both transmitter and receiver
(LO signals in Figure 4-1). Furthermore, LO frequency should be adjustable but precisely controlled for different channels according to the wireless communication system design. Such function is usually realized using a voltage-controlled oscillator (VCO) in a phase-locked loop.
For many reasons, a differential implementation of the oscillator is usually chosen
[Por00]. A typical VCO in a CMOS technology is shown in Figure 6-1. These two cross coupled
MOSFETs (M1-M2) provide the negative resistance, and the L-C tank makes the circuit resonate
at the desired frequency. In order to control the oscillation frequency, varactors (Cvar) are included
as part of the L-C tuning tank.
In general, higher quality factor (Q) for the L-C tank is preferred in VCO design, because
(1) the output noise shaping function is sharper, (2) power dissipation of circuit is lower, and (3)
noise injected from MOSFETs is reduced [Raz01]. Noise performance and power consumption
requirements are very strict in a wireless communication system. Therefore, much efforts have
111
VDD
Vbias
M3
Vvar
L
Vout+
Vout-
Cvar
Cvar
M1
Figure 6-1.
L
M2
Schematic of a typical differential CMOS voltage-controlled oscillator.
been expended to improve the voltage-controlled oscillator (VCO) design, and more specifically
to realize a high-Q and low parasitic LC-tank.
Q of inductors increases with operating frequency (QL ~ ωL/Rs, where L is inductance, Rs
is series resistance) so that this is less of concern when operating frequency is increased. Unfortunately, Q of capacitors/varactors is inversely proportional to frequency (QC ~ 1/ωCRs, where C is
capacitance, Rs is series resistance). Studies have shown that, at frequencies lower than 10 GHz,
the Q of L-C tanks is usually limited by the on-chip inductors. However, above 20 GHz and in the
millimeter-wave range, Q of capacitors/varactors becomes more problematic for the overall L-C
tank [Cao06a, Cao06b].
6.1.2 MOS Varactors
Conventionally, on-chip varactors have been implemented with p-n junctions under
reverse bias or MOS capacitors in accumulation/depletion regions. The latter structure has dem-
112
onstrated higher Q factor and wider tuning capability over the former one when the voltage supply is scaled down [Sve99, Por00]. Therefore, MOS varactors are often used in VCO circuits.
The cross-section of a typical MOS varactor is shown in Figure 6-2. The top and bottom
plates are formed by silicided polysilicon and n-well, and are separated by the same high quality
gate oxide layer as that of MOSFET’s. Since the gate oxide layer is very thin, the MOS varactor
has a high intrinsic capacitance-area ratio, especially when it is biased in the accumulation mode
[Hun98].
This varactor structure is very similar to an n-channel MOSFET with the exception of
being fabricated in an n-well instead of the normal p-substrate. This choice was made to eliminate
the parasitic pn-junction capacitances at source and drain that would otherwise limit the tuning
range. An alternative structure using a p-channel MOSFET in a p-well/substrate has a lower quality factor due to lower carrier mobility.
The operation principle of varactors is to change the capacitance of a MOS structure by
varying the gate voltage, which changes the operation region among accumulation, depletion, and
inversion [Soo98, Mol02]. By applying positive voltage between the gate and n-well, the Si surMetal2
Metal1
Poly
STI
n+
n+
STI
n-well
p-substrate
Figure 6-2.
Cross-section of MOS varactor structures.
113
face is accumulated and the varactor capacitance equals the gate oxide capacitance. If the applied
voltage is reversed, the Si surface layer is depleted and the series capacitance decreases. The maximum capacitance per unit area of the varactor corresponds to a heavily accumulated surface and
equals the unit area gate oxide capacitance (Cox=εoεox/tox). On the other side, the minimum value
(Cd) is reached when the voltage between the gate and n-well is negative and beyond the threshold voltage. In this case, an inversion layer is formed under the gate. At low frequencies (~ kHz),
this effect brings the value of capacitance close to the gate oxide one. However, at high frequencies where the varactor is supposed to operate in VCOs, this effect is not seen and the capacitance
remains at its minimum value. The difference between Cox and Cd indicates the capacitance tuning capability for varactors.
Ideally, total varactor capacitance can be varied between the maximum and the minimum
as in Equations 6-1 and 6-2.
C max = C ox ⋅ A tot = C ox ⋅ W ⋅ L ⋅ N ,
(6-1)
C min = C d ⋅ A tot = C d ⋅ W ⋅ L ⋅ N .
(6-2)
Here, W and L are the finger width and length, and N is the total number of fingers.
The series resistance Rs of the varactor usually is dominated by n-well and gate resistances, and can be calculated as following [Hun98]:
1 1 1 1
R s = --- ⋅ --- ⋅ --- ⋅ ---- ⋅  R
3 2 2 N 
nw
1
= -------------------------------- ⋅ (R
12 ⋅ W ⋅ L ⋅ N
L
⋅ ----- + R
W
poly
W
⋅ -----
L
2
nw
114
⋅L +R
2
poly
⋅W )
,
(6-3)
where, R
nw
and R
poly are
the sheet resistances of n-well and polysilicon gate, respectively. The
factor 1/3 accounts for the spreading effect, while two 1/2 factors account for the double-sided
contacts for both poly gate and n-well.
The minimum varactor quality factor (Qmin) is obtained when the capacitance is the largest. From Equations 6-1 and 6-3, Qmin is expressed as
1 - = ------------------------------------------------------------------------------12
Q min = ---------------------.
2
2
ωR s C max
ωC ox ( R nw ⋅ L + R poly ⋅ W )
(6-4)
Obviously, Qmin is a monotonic function of L (or W) and it is preferable to use minimum dimensions for both L and W to increase Q.
Another important parameter for a varactor is its capacitance tuning range (γ). Without
losing the generality, γ can be defined as
C max – C mim
C max – C mim
C ox – C d
γ = ------------------------------------------- ≈ ------------------------------- = --------------------- × 100 %,
( C max + C mim ) ⁄ 2
C max
C ox
(6-5)
where γ is independent of dimension parameters L (or W). Higher γ suggests better capacitance
tuning capability, and in turn, wider VCO frequency tuning range.
Until now, parasitic capacitances associated with gate overlap and interconnect layers
have not yet been taken into account. However, those parasitics can be comparable to the varactor
capacitance itself. Therefore, a parasitic term Cpar(W, L, N) should be added to Equations 6-1 and
6-2. In a typical varactor layout, L is much smaller than W. The gate overlap capacitance and the
fringe capacitance between the gate and metal connections dominate in Cpar and they both are
proportional to W ⋅ N . The overlap area capacitance between metal2 and poly gate is relatively
smaller. Even thought Cpar should be a complicate function of W, L and N in general, it is still a
115
good approximation to assume C par ( W, L, N ) ∝ W ⋅ N . Now, Equations 6-1 and 6-2 should be
modified as below,
C max = C ox ⋅ A tot + C par ( W, L, N ) = C ox ⋅ W ⋅ L ⋅ N + β ⋅ W ⋅ N ,
(6-6)
C min = C d ⋅ A tot + C par ( W, L, N ) = C d ⋅ W ⋅ L ⋅ N + β ⋅ W ⋅ N .
(6-7)
Here, β is a constant representing the total parasitic capacitance per unit width.
Accordingly, Equations 6-4 and 6-5 should also be modified:
12
Q min = ----------------------------------------------------------------------------------------------- ,
2
2
ω ( R nw ⋅ L + R poly ⋅ W )  C ox + --β-

L
C max – C mim
C ox – C d
γ ≈ ------------------------------- = --------------------- × 100 %.
C max
C ox + --βL
(6-8)
(6-9)
From Equation 6-8, it is noted that Qmin is no longer a monotonic function of L. With a given W,
Qmin reaches the peak value when L satisfies the Equation 6-10.
R nw
R nw C ox
2 ⋅ ----------------- ⋅ --------- ⋅ L 3 + ----------------- ⋅ L 2 = W 2 .
R poly β
R poly
(6-10)
Also, the capacitance tuning range (γ) has dependence on L as suggested in Equation 6-9. When L
decreases, more contribution of total capacitance will come from parasitics, which is independent
of varactor gate voltage. In turn, this additional parasitic capacitance will degrade γ.
6.1.3 Sub-Design-Rule MOS Varactors
As suggested by the Equation 6-4 or 6-8, the thick-gate-oxide MOS structure inherently
has higher quality factor due to thicker gate-oxide layer (tox) and lower gate capacitance (Cox).
The capacitance area density is smaller compared to the thin-gate-oxide MOS structure. However,
this is not a serious issue for circuits operating above ~ 1 GHz.
116
The Q factor can be further improved if the SDR thick-gate-oxide MOS structures are
employed to reduce the channel length. In addition, there are no reliability issues for SDR MOS
structures in varactor applications because the “source” and “drain” are always tied together to
form the bottom plate connection. However, decreasing channel length L will degrade the varactor tuning range (γ). Therefore, the trade-off of Q factor and the varactor tuning range (γ) is an
important issue in high-Q varactor design. In the next section, the difference and possible advantages of thick-gate-oxide SDR MOS varactors over its conventional thin-gate-oxide counterpart
are discussed.
6.2 High Frequency Characteristics of SDR MOS Varactors
6.2.1 Device Structure
One-port AC test structures of thick-gate-oxide (TK) SDR and conventional MOS varactors are fabricated in the same 0.13-µm CMOS technology as mentioned in Section 3.4.
Figure 6-3 shows a layout and an equivalent circuit model of those varactors. The drawn finger
Lmetal
poly
contact
Rmetal
Rgate
W
metal
Cpar
L
diffusion
Rnwell
varactor
Figure 6-3.
Layout and equivalent circuit model of a MOS varactor.
117
Cvar
channel lengths include 0.12, 0.18, 0.24 and 0.3 µm (SDR varactors), and 0.36 µm (conventional
TK varactor). All the drawn finger width (W) is 0.9 µm. Besides those, one more conventional
TK varactor of 5.0 µm by 1.0 µm is also fabricated to illustrate the better tuning range case. To
investigate the difference of SDR varactors over thin-gate-oxide (TN) varactors, another group of
TN varactor structures with the same dimensions listed above are also built.
As discussed before, a pad frame structure with no device is fabricated as “AC open” in
order to de-embed the capacitance of the pad frame and metal connections. Again, a structure
with device replaced by a wide metal line is also fabricated as “AC short” to de-embed the extra
series resistance and inductance introduce by metal connection (Rmetal and Lmetal in Figure 6-3).
A network analyzer (HP8510C) is employed for S-parameter measurements.
6.2.2 Measurements and Discussions
All thick-gate-oxide and thin-gate-oxide varactor test structures are characterized. As an
example, Figure 6-4 only shows the extracted capacitance and quality factor at 24 GHz versus
gate voltage for TK-24 and TN-24 varactors with channel length at 0.24 µm. The TN-24 varactor
demonstrates wider tuning range than the TK-24, while the quality factor can be as low as ~ 20.
The TK-24 varactor, using SDR channel length, can increase the quality factor to above 100.
Qmin measured at 24 GHz and tuning range γ for different test structures are plotted
together in Figure 6-5. With a decreasing channel length, γ for both TK and TN varactors
decreases relatively smoothly. Also, as expected, TK structures have smaller tuning range than
TN ones. γ values shift down from ~ 65% for TN to ~ 40% for TK structures. On the other hand,
measured Qmin increases rapidly in both TK and TN cases, when varactor channels become
shorter. It is noted that using SDR channel can improve Qmin of TK varactors even more dramatically. At a length of 0.36 µm, the TK varactor has Qmin of 48, which is 3 times that of the TN var-
118
200
60
160
C (TN-24)
120
Q (TK-24)
40
Q (TN-24)
80
Quality Factor
Capacitance (fF)
C (TK-24)
20
40
0
0
0
1
2
Gate Voltage (V)
C-V and Q-V characteristics of the thick-gate-oxide (TK) and
thin-gate-oxide (TN) varactors with L = 0.24 µm.
-2
Figure 6-4.
-1
100
γ (TK)
Qmin
80
60
80
40
40
Qmin (TK)
Tuning Range γ (%)
γ (TN)
120
20
Qmin (TN)
0
0
0
0.2
0.4
0.6
0.8
1.0
Channel Length (µm)
Figure 6-5.
Measurement data of Qmin and γ vs channel length for thick-gate-oxide
(TK) and thin-gate-oxide (TN) varactors.
119
actor. When the length is shorten to 0.24 µm in SDR region, TK varactor’s Qmin can jump to
above 100. It is improved by almost 5 times compared to the corresponding TN varactor. It is
noted that, at extreme high Qmin situation, the series resistance (Rs) is only several ohms and
much smaller than the reactance of capacitor. This makes it difficult to extract reliable Qmin for
those SDR varactors with the channel length below 0.24 µm
Those four lines drawn in Figure 6-5 are calculated Qmin and γ from Equations 6-8 and
6-9. β is extracted from the measurement results by data fitting. The 1st-order approximation fits
most measurement results well. Interestingly, the data points at length of 1.0 µm significantly
deviate from the calculated plots. The reasons include that, for these structures, the gate connections are single-sided, the channel width of 5 µm rather than 0.9 µm is used and the metal connections have no overpass above the poly gate. There are more series resistance and less percentage
of parasitic capacitance compared to predictions from the Equations 6-8 and 6-9, therefore, data
show lower Qmin and higher tuning range.
Equation 6-8 also suggests that, at very small L, term R
exceed R
2
poly
⋅ W may be comparable or
2
nw
⋅ L , and Qmin may drop when L is further reduced. For this 0.13-µm CMOS pro-
cess, the critical channel lengths calculated by Equation 6-10 are ~ 0.1 and ~ 0.08 µm for TK and
TN varactors, respectively. These lengths are below the lithography limit, therefore, shrinking
channel length can always improve Qmin of MOS varactors.
Qmin and tuning range are two major parameters for varactor design. To clearly show the
trade-off between them, curves of Qmin versus tuning range γ, once again, are plotted in
Figure 6-6. TN varactors have superior tuning range to the thicker ones. However, their Qmin are
well below 40. By using SDR varactors, Qmin can be dramatically improved. The design space is
120
120
lower γ
TK
TN
100
Qmin
80
higher
Qmin
60
40
∝ 1/γ
20
0
0
Figure 6-6.
20
40
60
80
Tuning Range γ (%)
100
Varactor design space formed by Qmin and tuning range γ.
extended to region of higher-Qmin-lower-γ combination. Fortunately, the degradation of γ is relatively small in this space.
So, tuning range can be traded off for high-Q performance in SDR varactors. For example,
such varactors can be used in a dual-conversion receiver [Li03] operating around 50 GHz [Che06,
Luo05]. The incoming signal is down-converted twice by using two VCOs. The first VCO operates at higher but fixed frequency, so the wanted channel will not be centered around the first
intermediate frequency (IF1). However, the second VCO has a wide tuning range and will guarantee that the wanted channel is centered around fixed frequency (IF2 or DC) by the second
down-conversion. SDR varactors, which have limited tuning range but superb quality factor fit
well to the first VCO application. The significantly improved Qmin of this type of varactors can
improve the total L-C tank Q and result in better phase noise performance and lower power consumption. Even though the margin for the parasitic capacitance due to the core transistors should
121
be reserved, it is believed that the varactor capacitance tuning range (γ) of ~ 40% is sufficient for
the first VCO to compensate the process, temperature and supply variations.
6.3 Summary
In this chapter, use of the SDR MOS structures as varactors in VCO circuits is studied to
investigate the feasibility of exploiting higher Q components. A series of SDR varactors are fabricated and characterized. Their performance is compared to that of the conventional
thin-gate-oxide MOS varactors.
Qmin and tuning range (γ) are very important parameters for varactor design. However,
Qmin of thin-gate-oxide MOS varactors is limited at frequencies above ~ 20 GHz. Qmin-γ design
space for MOS varactors can be greatly expanded by using thick-gate-oxide SDR structures. A
combination of extreme high Qmin and modest tuning range (γ) is achieved and its possible applications in VCOs is discussed. Using SDR varactors can improve the phase noise and power consumption performances of VCO’s operating at frequencies above 20 GHz.
122
CHAPTER 7
SUMMARY AND SUGGESTION FOR FUTURE WORK
7.1 Summary
Conventional thick-gate-oxide MOS transistors are often part of standard offering in commercial CMOS technologies. They have many advantages, such as higher breakdown voltage,
higher power handling capability and lower drain leakage current. Compared to the
thin-gate-oxide transistors, low-current low-speed characteristics limit the usage and the performance of thick-gate-oxide transistors in many circuits. Because the lithography limit in these processes is significantly lower, the high voltage performance can be traded off to improve their high
frequency performance.
A goal of this research has been to find approaches to improve the performance of
thick-gate-oxide MOS transistors without modifying the existing foundry technologies. It has
proven the sub-design-rule (SDR) channel length transistors is an easy and effective way to
improve the characteristics of transistors with thick-gate-oxide in different circuit applications.
The dissertation began with the exploration of using SDR transistors in digital I/O circuits.
In Chapter 2, a single SDR transistor was investigated as the starting point. Its application in a
3.3-to-1.8-V level shifter circuit using a 0.18-µm CMOS foundry technology is studied. A series
of thick-oxide SDR MOS transistors are compared to the conventional 3.3-V MOS transistors.
The measurements suggest that the 0.26-µm long SDR MOS transistor (SDR-26) can deliver 1.28
times the drain current as the conventional one, while maintaining sufficient breakdown voltages
to tolerate the signal swing at the gate and drain nodes. The conventional 3.3-V drive transistors
in the 3.3-to-1.8-V level shifter can be replaced by 25.6% wider SDR-26 transistors to provide
60% more drain current. In simulations, this current enhancement translates into a nearly 20%
reduction in the propagation delay.
123
Following that, the composite MOS transistor, consisting of a SDR thick-oxide MOS transistor and a conventional thin-oxide transistor, was proposed in Chapter 3. Its low threshold voltage makes it well suited as the drive transistors in the low-to-high level shifter circuits. In a
0.13-µm CMOS technology, the measurement results show that a 0.22-µm long SDR thick-oxide
MOS transistor in series with a conventional thin-oxide transistor (composite-22) is the optimal
combination for use in the 1.2-to-3.3-V level shifter circuits. This composite-22 transistor can
deliver more than 2 times the drain current as the conventional thick-oxide transistors, while still
having sufficient breakdown voltages and protecting the TN sub-transistors for 3.3-V swing at the
drain node. This current enhancement translates to about 40% reduction in the propagation delay.
The study has successfully identified the circuit benefits of using the SDR MOS transistors or the composite MOS transistors in level shift circuits. This concept of further shrinking
thick-gate-oxide transistors is also applicable to other more advanced technologies. In general,
use of the SDR MOS transistors provides another way to exploit the scaling of CMOS technologies.
Building on their digital I/O circuit applications, the role of SDR transistors in RF/analog
applications is investigated. In Chapter 4, use of the composite MOS transistors in RF power
amplifier (PA) circuits was examined. For power amplifiers, the output power level and the power
efficiency are the two key specifications. Compromise between the linearity and power efficiency
are necessary for power amplifiers in different classes. High-voltage (thick-oxide) MOS transistors are preferred for certain PA designs.
The composite-22 MOS transistor can handle the same drain voltage swing like the conventional 3.3-V MOS transistors. fT and fmax of the devices are measured. In general, the composite-22 MOS transistor is not superior to the conventional 3.3-V transistor. When considering the
124
practical gate bias conditions (0 < VGS-VT < 0.25 V), the measurements show that the composite-22 MOS transistor has higher fT and comparable fmax than the conventional 3.3-V
thick-gate-oxide transistors. At best, the improvements of RF power amplifier gain and efficiency
are expected to be marginal. The lower intrinsic gain of the composite transistor limit its applications in analog amplifier circuits.
Use of the SDR MOS transistors in radio frequency T/R switch circuits was the research
focus of Chapter 5. In this chapter, design techniques for improving the power handing capability
of bulk CMOS T/R switches to above 30 dBm while maintaining acceptable insertion loss have
been demonstrated using the UMC 130-nm mixed-mode triple-well CMOS technology. Stacked
sub-design-rule (SDR) channel length NMOS transistors with a thick-gate-oxide layer are used to
improve the power handling capability while keeping IL below 1 dB. Use of a thick-gate-oxide
layer of 3.3-V transistors in SDR transistors enables ~3.5-V drop across the transistors without
reliability concerns. Isolated p-wells and p-well blocks are used to improve the floating-body
effect.
At 900 MHz, a switch incorporating 3-stack SDR transistors located in isolated p-wells
exhibits IP1dB of 30 dBm. By using feed-forward capacitors, IP1dB is increased to 31.3 dBm. A
decrease of drain-to-source breakdown voltages for the TX shunt and RX series stacked transistors due to un-intentional turning-on of the transistors by RF input is suggested as the likely cause
for a sudden output power drop. The switch achieves 0.5-dB and 1.0-dB insertion losses in the
transmit and receive modes. This switch has 0.2 dB lower insertion loss in receive mode and 5 dB
higher IP1dB in transmit mode compared to that for a switch using 2-stack design rule compliant
3.3-V transistors. To demonstrate the trade-off between power handling capability and switch
loss, a 2.4-GHz switch utilizing 2-stack SDR transistors is built. It exhibits IP1dB of 28 dBm and
125
its insertion losses for transmit and receive modes are 0.8 and 1.2 dB, respectively, compared to
0.5 and 1.0 dB for the switch with 31.3-dBm IP1dB. This 2.4-GHz T/R switch should be acceptable for 802.11b and g applications. This work suggested that integration of a bulk CMOS T/R
switch for cellular applications no longer appears to be an unrealizable goal.
In Chapter 6, use of the SDR MOS structures as varactors is discussed. The SDR MOS
varactors have higher quality factor (Q) than thin-gate-oxide varactors. A series of SDR varactors
were fabricated and characterized. Their performance benefits in VCO applications were explored
in comparison to the conventional thin-gate-oxide MOS varactors.
The minimum Q (Qmin) and tuning range (γ) are important parameters for varactor design.
However, Qmin of thin-gate-oxide MOS varactors is limited at frequencies above ~ 20 GHz. The
Qmin-γ design space for MOS varactors can be greatly expanded by using thick-gate-oxide SDR
structures. A combination of extremely high Qmin and modest tuning range (γ) is achieved and its
possible applications in VCOs are discussed. This can be used to reduce high frequency (> ~20
GHz) VCO phase noise and power consumption.
7.2 Suggestion for Future Work
Based on the study presented in this dissertation, additional works on SDR MOS structures are suggested.
7.2.1 Application in high power T/R switches
This study demonstrated that it is feasible to build CMOS T/R switches with power handling capability above 30 dBm. It is difficult but will be interesting to improve this performance
even higher. One possible way is to stack more SDR transistors in the high voltage paths. The
optimal SDR channel length should be experimentally investigated.
126
G_RX
ANT
C31
C
M4
C11
M3
M2
M1
RX
C
Figure 7-1.
C32
C12
Additional nodes to connect feedforward capacitors in a 4-transistor stack
of SDR T/R switches.
More number of stacking transistors means more flexibility for the voltage division
among them. Feedforward capacitance technique should still improve the T/R switch power handling capability. There are additional nodes to add the feedforward capacitors. For example,
capacitors can be connected to the drain node of the second top transistor in the stack (C31, C32 in
Figure 7-1), and the source node of the bottom transistor in the stack (C11, C12 in Figure 7-1),
which otherwise usually sustain higher voltage swings. Optimization of capacitance value and
location should be further examined.
7.2.2 Application in high-Q varactors
The varactor structures used in this work have capacitance around 40 fF. The associated
series resistance is only several ohms and sometimes difficult to measure. This becomes particularly problematic when the length of SDR varactor decreases below 0.24 µm. Varactor structures
with a smaller number of fingers should provide sufficient series resistance and facilitate the
investigation of SDR varactors with even higher Q.
Capacitance tuning range (γ) of SDR MOS varactors is inferior to that of thin-gate-oxide
ones. The reason is the percentage of parasitic capacitance is higher. It should be helpful if the
127
Metal2
S2
Poly
STI
n+
Metal1
S1
n+
STI
n-well
p-substrate
Figure 7-2.
Spacing between poly gate and diffusion connections in MOS varactor
structures.
spacing between poly gate and metal connections of diffusions is further increased (Figure 7-2).
One way is to increase distance between the poly gate and diffusion contacts. The increase in chip
area and additional series resistance along the diffusion region and metal connections are the
drawbacks. Another way is to use metal3 layer as the overpass connection. This method does not
change the area consumption, and the series resistance will slightly increase due to the extra via
connections. Varactor test structures with different S1 and S2 should be fabricated along with the
control structure. The trade-off among tuning range, series resistance and chip area should be
investigated.
128
APPENDIX
MODEL FILE FOR SDR-26 MOS TRANSISTORS
The model used in simulation for the SDR-26 MOS transistors are based on that of the
conventional 3.3-V MOS transistor. Those modified parameters are highlighted.
...
6: type=n minr=1e-60 lmin=3.5e-07 noimod=1 ef=0.907 af=0.9065 kf=8.704e-29 lmax=5e-07 - dxl3 wmin=1.28e-06
+ - dxw3 wmax=1.008e-05 - dxw3 tnom=25 version=3.2 tox= 1.5 * 6.8e-09 toxm=1.5 * 6.8e-09 xj=1.7e-07
+ nch=5.26e+17 lln=-1 lwn=1 wln=1 wwn=1 lint=4e-08 ll=0 lw=0 lwl=0 wint=3e-08 wl=0
+ ww=0 wwl=0 mobmod=1 binunit=2 xl= - 2e-08 + dxl3 xw=0 + dxw3 dwg=0 dwb=0
+ ldif=9e-08 hdif=hdifn3 rsh=6.8 rd=0 rs=0 vth0= -0.18 + 0.8654908 + dvthn3 lvth0=-1.656396e-08
+ wvth0=1.422681e-09 pvth0=-6.085174e-16 k1=0.7481822 lk1=1.029616e-07 wk1=-1.008557e-07
+ pk1=2.007025e-14 k2=0.189703 lk2=-9.366277e-08 wk2=8.466009e-09 pk2=7.544907e-15
+ k3=0 dvt0=0 dvt1=0 dvt2=0 dvt0w=0 dvt1w=0 dvt2w=0 nlx=0 w0=0 k3b=0 vsat= 1.7 * 93128.79
+ lvsat=-0.0008515152 wvsat=-0.004630455 pvsat=1.852182e-09 ua=-6.665338e-10 lua=-9.533202e-17
+ wua=-1.002899e-15 pua=3.95669e-22 ub=2.115918e-18 lub=2.187213e-25 wub=5.45836e-25
+ pub=-4.393103e-31 uc=2.631281e-10 luc=-3.906129e-17 wuc=-1.204542e-16 puc=2.977803e-23
+ rdsw=545 prwb=0 prwg=0 wr=1 u0=1.43 * 0.04367778 lu0=3.770848e-10 wu0=-1.023911e-08
pu0=2.667197e-15
...
129
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136
BIOGRAPHICAL SKETCH
Haifeng Xu was born in Xi’an, China, in June 1975. He received the B.S. degree in Physics from Nanjing University, Nanjing, China, in 1996, and the M.S. and Ph.D. degrees in electrical and computer engineering from the University of Florida, Gainesville, FL, USA, in 2002 and
2007, respectively. He joined the Silicon Microwave Integrated Circuits and Systems (SiMICS)
Research Group in the Department of Electrical and Computer Engineering at University of Florida in 2000. In 2001, he worked on radio frequency (RF) integrated circuit design as a summer
intern at IBM Boston Design Center, Chelmsford, MA, USA. His research interests include
CMOS RF integrated circuits, RF power amplifiers, monolithic microwave IC (MMIC) components and digital I/O circuits.
137