Evaluating TVS Protection
Circuits with SPICE
By Jim Lepkowski, Senior Applications Engineer, ON
Semiconductor, Phoenix, and William Lepkowski,
University of Arizona, Tucson, Ariz.
A transient-voltage-suppression diode macromodel offers greater accuracy than a standard
diode SPICE model.
S
PICE circuit simulations are a powerful design
tool to analyze a system’s immunity against
conducted EMI surge voltages. SPICE can serve
as a valuable tool to validate and optimize the
performance of surge-protection circuits using
transient-voltage-suppression (TVS) avalanche diodes. The
small size, fast response time, low clamping voltage and low
cost of TVS diodes provides for an effective solution to solve
surge problems. A comparison of SPICE simulations with
bench tests demonstrates the ability of TVS avalanche diodes
to clamp the surge voltages caused by noise sources such as
inductive devices and load switching.
Anode
7
ID
L
2
Voltage
1
Cathode
EV1=[ IBV x RBV)-VD3 ]
6
8
+EV1-
D2
4
EV1 +-
IBV
RBV
D3
0
TVS Diode SPICE Models
The majority of the TVS avalanche diode SPICE models
available are created with the SPICE “D” diode statement.
There are several restrictions that limit the accuracy of using
the diode “D” statement to model a TVS avalanche diode.
First, the diode statement does not have a provision for
defining a separate series resistance for the forward- and
Forward
Region
Fig. 1. A TVS avalanche diode’s I versus V characteristics.
Power Electronics Technology January 2006
RL
which provides the ability to absorb high peak energy. The
current versus voltage relationship of a TVS diode is shown
in Fig. 1.
The graph in Fig. 1 depicts various diode parameters. IF is
the forward current and VF is the associated forward voltage
at that current. IR is the reverse leakage current and VRWM is
the reverse-working voltage at IR. Typically, VRWM (typ.) ≅ 0.8
 VBR. Other parameters include IT , the test current; VBR,
the breakdown voltage at IT ; and IPP , the maximum reverse
peak pulse current. IPP is typically specified with either the
8  20-µs or 10  1000-µs surge pulse. In addition, VC is
the clamping voltage at IPP .
IPP
Leakage Region
D1
IR
IT
Fig. 2. The TVS avalanche diode SPICE macro-model is constructed by
combining standard Spice devices.
IF
Breakdown
Region
VD
3
Cathode
Current
IR VF
IT
IL
1
Zener and TVS avalanche diodes have similar electrical
characteristics; however, there are significant differences
between the two devices. A zener is designed to regulate
a steady-state voltage, while a TVS diode is designed to
clamp a transient-surge voltage. In addition, TVS diodes
typically have a larger junction area than a standard zener,
VRWM
IF
-
I Versus V Characteristics
VC VBR
RZ
Anode
+ 7
ID
44
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TVS DIODES
GND
DB
DD
DA
DC
I/O1
I/O2
Fig. 3. The NUP2105 houses dual line
bidirectional TVS diodes in a SOT-23 package.
IS
Saturation Current
SPICE Default
Value
1 E-14
RS
Resistance
0
Ω
BV
Reverse Breakdown Voltage
∞
V
IBV
Current at Reverse Breakdown Voltage
1 E-3
A
Variable
Parameter
A
N
Emission Coefficient (η)
1
-
XT1
Saturation Current Temp. Coefficient
3
-
TT
Transit Time
0
nS
CJO
Zero Bias Junction Capacitance
0
pF
VJ
Junction Potential
1
V
0.5
-
1.11
eV
0
-
1
-
0.5
-
27
°C
reverse-bias breakdown regions. The
resistances in the two regions are
M
Grading Coefficient
not equal; thus, it is not possible to
EG
Activation Energy
accurately model the slope of the
KF
Flicker Noise Coefficient
current versus voltage characteristic in
AF
Flicker Noise Exponent
both regions. Next, the “D” statement
does not have a variable to model the
Depletion Capacitance
FC
Forward Bias Coefficient
variance of the breakdown voltage
with temperature. Table 1 provides the
TNOM
Nominal Temperature
variables available with the PSPICE
Table 1. Default values of the PSPICE diode statement “D” variables.
“D” diode model.
Macro-Model Subcircuit
A TVS diode macro-model offers several advantages
over the standard diode model available in SPICE,
including a more accurate representation of the
breakdown characteristic. TVS macro-models are created
by combining standard SPICE devices into a subcircuit.
Fig. 2 shows a schematic for a macro-model of a TVS
avalanche diode. A PSPICE netlist for this model appears
below. This particular netlist models the NUP2105, a dual,
bidirectional voltage suppressor from Phoenix-based ON
Semiconductor (Fig. 3).
********************************************************
******************************************************
*NUP2105 PSPICE macro-model
*Bidirectional TVS avalanche diode, SOT-23, VBR = 26.4 V
*Model simulates 1 of the 2 bidirectional TVS devices
******************************************************
*DA Cathode = 1, DB Cathode = 2, DA,B Common Anode = 3
.SUBCKT NUP2105 1 2 3
*Bidirectional devices are formed from two unidirectional
*devices
X1 3 1 HALFNUP2105
X2 3 2 HALFNUP2105
.ENDS NUP2105
******************************************************
*Model HALFNUP2105 represents one bidirectional pair
*of a dual device
*Anode = 7, Cathode = 1
.SUBCKT HALFNUP2105 7 1
*Forward Region
*D1’s CJO term models the capacitance
D1 2 1 MDD1
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Units
.MODEL MDD1 D IS=1.83708e-14 N=1 XTI=1 RS=0.2
+ CJO=26.4e-12 TT=1e-08
******************************************************
45
Power Electronics Technology January 2006
TVS DIODES
RZ 2 3 1.28
D2 4 3 MDD2
RS
LS C S
.MODEL MDD2 D IS=2.5e-15 N=0.5
*Breakdown Voltage (VBR) = IBV x RBV
1000
EV1 1 4 6 8 1
R S= 1.28 Ω
IBV 0 6 0.001
L S= 2.48 nH
100
RBV 6 0 MDRBV 26357.1
C S= 26.4 pF
Measured Data
*MDRBV temp. coef. model ∆VBR/∆T
Small Signal Model
.MODEL MDRBV RES TC1=0.00096
10
1
D3 8 0 MDD2
fR =
fR =616 MHz (@ O VDC bias)
IT 0 8 0.001
2π LS C S
***************************************
1
1
10
100
fR 1000
*L models the lead-to-silicon connection
Frequency (MHz)
*package inductance
*L is distributed between two diodes for
Fig. 4. The impedance of a TVS diode can be modeled as a capacitor at relatively low
*bidirectional diodes
frequencies; however, the inductance of the IC package must be included as the frequency
L 7 2 1.24e-9
approaches the resonant frequency.
*
*Leakage Region
.ENDS HALFNUP2105
*RL models leakage current (IL)
********************************************************
*MDR temp. coef. model ∆IL / ∆T
******************************************************
RL 1 2 MDR 4.32244e+08
The TVS macro-model is based on the zener diode model
.MODEL MDR RES TC1=0 TC2=0
provided in references 3 and 4. References 1 and 2 provide
******************************************************
additional information on modeling TVS devices.
*Reverse Breakdown Region
Forward bias region: Diode D1 is the key component when
*RZ models the ∆I / ∆V slope
voltage VD is greater than zero. The TVS diode’s forward-bias
characteristics are controlled by D1’s saturation current (IS),
emission coefficient (N) and series resistance (RS) variables.
The forward-bias current equations are as follows:
NUP2105
Impedance (Ω)
10000
ID = IF + IL + IR
VD
+ IS _ D2 ,
RL
where IL and IR << IF .
= IF _ D1 +
Therefore, ID @ IF _ D1 @
Ê hVVD1
ˆ
Ê hVVD1 ˆ
T
IS _ D1 Á e - 1˜ @ IS _ D1 Á e T ˜ , where
Ë
¯
Ë
¯
VT =
kT
@ 26 mV at 25∞C
q
Leakage region: The leakage or reverse bias before
breakdown region is defined when voltage VD is between 0 V
and the breakdown voltage (VBR). Currents IF and IR are small
in comparison to IL because diodes D1 and D2 are reverse
biased; thus, the leakage current is approximated by VD/RL:
ID = IF + IL + IR
VD
- IS _ D2 , where
RL
IF and IR << IL
= IS _ D1 +
Therefore, ID @
Power Electronics Technology January 2006
46
VD
RL
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TVS DIODES
(a)
10 A
(b)
NUP2105
NUP2105
TVS Clamping Voltage
5A
8 x 20 µs Current
Waveform
8A
40.8 V
0
50 V
8A
5 µs/div.
VC(max.) = 40.7
TVS Clamping Voltage
8 x 20 µs Current Waveform
0
0
10
20
30
40
50
Time (µs)
Fig. 5. Comparing bench measurements (a) on a surge-tested TVS device with Spice simulation (b). SPICE predicts a maximum clamping
voltage of 40.7 V, which matches the 40.8 V bench test measurement.
the product of current source IBV and resistor RBV , minus the
voltage of D3. D3 is used to compensate for the voltage drop
of D2. The clamping voltage (VC), specified at current IPP ,is
equal to the sum of the voltages of EV1, RZ and D2:
Breakdown region: The breakdown region is modeled by
EV1, D2 and RZ. Current flows through this path when the
voltage exceeds EV1 plus the forward voltage of D2. The
breakdown voltage (VBR), represented by EV1, is equal to
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47
Power Electronics Technology January 2006
TVS DIODES
(a)
(b)
1A
10 x 1000 µs
Current Waveform
NUP2105
1A
TVS Clamping Voltage
NUP2105
0A
35 V
35.6 V
VC(max.) = 28.9 V
RZ = 1.28 Ω
10 x 1000 µs Current Waveform
1A
TVS Clamping Voltage
0V
40 V
VC(max.) = 35.4 V
RZ = 8 Ω
200 µs/div.
0V
0
0.5
TVS Clamping Voltage
1.0
Time (ms)
1.5
2.0
Fig. 6. Bench tests (a) versus SPICE (b) for a 10 x 1000-s surge pulse. SPICE predicts a maximum clamping voltage of 28.9 V with the nominal
device resistance (RZ = 1.28 
)) versus 35.6 V for the actual measurement. The simulated results match the bench test if RZ is increased to 8 .
Ê VD ˆ
ID @ IS Á e hVT ˜ ; therefore, VD @
Ë
¯
È Ê I ˆ˘
hVT Í1n Á D ˜ ˙
Î Ë IS ¯ ˚
VC at IPP = VBR + VD2 + VRZ =
È
Ê IT ˆ ˘
Í(IBV R BV ) - h3 VT 1n Á ˜ ˙ +
Ë IS3 ¯ ˚
Î
ÊI ˆ
h2 VT 1n Á PP ˜ + (IPP R Z )
Ë IS2 ¯
AC Model
influences the transient performance of
the clamping response.
The impedance plot of a TVS
avalanche diode is shown in Fig. 4.
The measured impedance can be
modeled by an equivalent circuit that
consists of resistor (RS), inductor (LS)
and capacitor (CS) connected in series.
RS is equal to the real portion of the
complex impedance and is measured
at the resonant frequency (fR). At fR, the
impedance is purely resistive because
the impedance of the LS and CS are equal
in magnitude but opposite in polarity.
CS is obtained by measuring the
capacitance at 1 MHz. LS is obtained
from the resonant frequency, which
co r re s p o n d s to t h e m i n i mu m
impedance. Table 2 provides a
correlation of the small signal model
to the SPICE macro-model.
Modeling the inductance ensures
the magnitude of the overshoot pulse
due to the inductance (V = L (∆I/∆t))
Equivalent Macro-
Comments
Impedance
Component
Model Component
characteristics: The
RZ ∝ clamping voltage VC
transient response
RS
RZ + D2RS
RZ ∝ 1/ power rating
of the macro-model
is simulated by
LS
L
L produces a short overshoot pulse due to V = L (I/t)
including the TVS
D1CJ0 is specified at a 0 V and decreases as the
CS
D1CJ0
device’s impedance
reverse-bias voltage increases
versus frequency Table 2. Correlation of the ac and macro-model components.
characteristics.
It is necessary
Region
Key Design Parameter
Limitation
to model the
VF is typically specified as a maximum value at a single
impedance
current point in the data sheet.
Forward
Forward
voltage
(V
)
F
because the
The accuracy is enhanced if two typical test points are used.
fast rise time
IL is modeled as a linear function of the bias voltage.
and high peak
Leakage
Leakage current (IL)
IL actually varies as an exponential function of the bias
current of the
voltage.
surge pulse
∆VC due to self-heating is not modeled.
creates highBreakdown
Clamping voltage (VC)
Overcurrent failures are not modeled.
frequency
information that Table 3. Simulation limits of TVS diode macro-models.
Power Electronics Technology January 2006
48
www.powerelectronics.com
TVS DIODES
of the IC package is simulated. Matching
the capacitance helps in predicting the
shape of the clamped waveform, while
including an accurate resistance term
is important in predicting the power
capability of the device.
Simulation Test Results
The ability of the SPICE macromodel to predict the performance of
a TVS device is shown by comparing
simulation and bench data for the 8
 20-µs and 10  1000-µs surge tests.
These waveforms are often used to
specify the power rating of a TVS device,
in addition to representing the surge
pulses produced by common noise
sources. The surge pulses are defined by
their rise time (tR), measured at 10% to
90% of the pulse amplitude, and their
pulse duration, measured at 50%. The
voltage and current waveforms represent
the open- and short-circuit—that is, R =
2 Ω—conditions, respectively.
Fig. 5 shows the clamping
performance of a TVS diode for the
8  20-µs surge test. The 8  20-µs
surge pulse represents the positive
voltage transient created by the sudden
interruption of current in a load that is
connected in parallel with an electronic
module. Low-side drivers that are used
to turn on electronic modules, motors
and relays are examples of systems that
can produce this surge pulse.
The clamping performance of a TVS
diode for the 10  1000-µs surge test is
shown in Fig. 6. The 10  1000-µs surge
pulse occurs when power is removed
from an inductive load and the device
under test (DUT) simultaneously. The
DUT remains connected in parallel
with the inductance, which produces
a negative surge voltage. DC motors,
solenoids and relays are common
examples of inductive loads that can
produce this surge pulse.
The discrepancy between the
measured and simulated 10  1000µs clamping voltage is due to the
self-heating of the device by the surge
current. In addition, the macro-model
was calibrated to the 8  20-µs pulse
instead of the 10  1000-µs pulse.
The accuracy of the predicted
clamping voltage for high-energy,
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long-duration surges can be improved
by calibrating the model with the 10 
1000-µs pulse. Future enhancements
of the macro-model will include
integrating a thermal model to simulate
the increase in the TVS device’s junction
temperature due to self-heating.
Macro-models provide an accurate
SPICE representation of the TVS
avalanche diode’s current and voltage
characteristics for most applications.
The macro-models solve several of the
limitations associated with the SPICE
diode “D” statement and the curvefit models. Macro-models provide a
powerful design tool to analyze surge
suppression circuits; however, they
are not a replacement for hardware
development tests. A summary of the
limitations of the macro-models is
shown in Table 3.
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Enhancing System Reliability
System designers are being challenged to meet stringent surgesuppression requirements. In order
to produce competitive products,
they must increase the reliability
and reduce the size and cost of their
circuits. TVS avalanche diodes can be
used to increase the surge immunity
without significantly adding to the
cost, size and complexity of power
circuits. The ability of TVS diodes to
dissipate surge voltages that contribute
to the early failure of semiconductors
can be evaluated using SPICE macromodels.
PETech
References
1. Bley, M., Filho, M. and Raizer,
A. “Modeling Transient Discharge
Suppressors,” IEEE Potentials, August/
September 2004.
2. Hageman, S. “Model Transient
Voltage Suppression Diodes,” MicroSim
Application Notes, 1997.
3. Lepkowski, J. “AND8250—Zener
Macro-Models Provide Accurate SPICE
Simulations,” ON Semiconductor,
2005.
4. Wong, S., Hu, C. and Chan, S., “SPICE
Macro Model for the Simulation of Zener
Diode Current-Voltage Characteristics,
Characteristics,”
International Journal of Electronics, Vol.
71, No. 24, August 1991.
49
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Power Electronics Technology January 2006