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AD9388A / ADV7441A Front End Board Quick Start Guide
ATV- Applications
Rev. 0 25/06/2008
Page 1 of 9
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APPLICATION NOTE
Table of Contents
Table of Contents .............................................................................................................................................................. 2
Introduction ...................................................................................................................................................................... 2
Evaluation Kit .................................................................................................................................................................... 3
Initial Configuration ........................................................................................................................................................ 3
Register Control Software ........................................................................................................................................... 3
Configuring AD9388A / ADV7441A Modes Using Script Files ........................................................................... 4
Configuring HDMI Jumpers ...................................................................................................................................... 5
Board Level Description .............................................................................................................................................. 5
EDID Configuration ........................................................................................................................................................ 7
Configuring the External EDID ................................................................................................................................. 7
Configuring the Internal EDID .................................................................................................................................. 7
FPGA Configuration ........................................................................................................................................................ 8
List of Figures .................................................................................................................................................................... 9
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APPLICATION NOTE
Introduction
This Evaluation Note is intended to provide application support for the EVAL-ADV7441AFEZ_x / EVALAD9388AFEZ_x evaluation kit. It also provides details on the set up and manual configuration of the
evaluation board. Software drivers are available for this evaluation board (a user guide is available for these
software drivers).
Evaluation Kit
Each front end evaluation kit consists of the following:


EVAL-ADV7441AFEZ_x / EVAL-AD9388AFEZ_x Video Input Board
Evaluation kit CD
Evaluation Kit Setup
1.
2.
3.
4.
5.
6.
Connect J9 of the EVAL-ADV7441AFEZ_x / EVAL-AD9388AFEZ_x to J1 of the ATV Mother
Board.
Connect J1 of the Video Output Module to J2 of the ATV Mother Board.
Power up the ATV Mother Board. (Connect the power supply provided to J18 and set switch S10 to
ON.)
Press S1 to reload the FPGA from PROM.
Wait until the Status LED (D2, D4-D7) turn on: this indicates that the software driver is ready to
run.
The EVAL-ADV7441AFEZ_x / EVAL-AD9388AFEZ_x evaluation kit is now ready to use with
either the embedded software driver (refer to SoftwareDriver_quick_start_guide) or the Register
Control software provided on the evaluation kit CD.
Initial Configuration
REGISTER CONTROL SOFTWARE
The USB cable should be connected via J12 of the Motherboard before the application is loaded.
1.
Install the Register Control software from the evaluation kit CD. (Refer to the Installation Guide on
the evaluation CD for step-by-step instructions.)
2.
Once the software is installed, connect the USB connector and power up the board.
3.
Start the application (select Start, Program, ADV Register Control).
The ADV Register Program Configuration screen appears, as shown in
Figure 1.
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APPLICATION NOTE
Figure 1. ADV Register Software Configuration
4.
Ensure the options shown in Figure 1 are set, and click on the OK button.
If the green USB is visible, this indicates that the USB firmware and communication is functional. When the
Register Control software starts, it first initializes all the selected devices and then loads the reset defaults for
each device. I2C control and reset signals are connected to the evaluation board via USB.
CONFIGURING AD9388A / ADV7441A MODES USING SCRIPT FILES
To enable easy and efficient evaluation, the ADV Register Control software is provided with script files that
Figure 2 illustrates how a script file can be accessed and selected from the drop down menu.
Figure 2. Configuration of AD9388A / ADV7441A with ADV Register Control Software
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APPLICATION NOTE
CONFIGURING HDMI JUMPERS
Jumpers need to be configured correctly for various HDMI options. Table 1 describes the required settings
for various options.
Table 1. Jumper Settings
Jumper Pair
Setting
Function
K5 and K6
Removed
Uses internal EDID for Port A
Set to B
Port A PROM (U6) connected to I2C bus for programming
Set to A
Uses external EDID for Port A
Removed
Uses internal EDID for Port B
Set to B
Port B PROM (U9) connected to I2C bus for programming
Set to A
Uses external EDID for Port B
K1 and K4
BOARD LEVEL DESCRIPTION
The primary features of the boards and their positions are marked in Figure 3, Figure 4, and Figure 5.
Figure 3. ATV Mother Board
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APPLICATION NOTE
Figure 4. Video Output Module Board
Figure 5. EVAL-AD9388A/ADV7441AFEZ_x Rev. A Input Module Board
Page 6 of 9
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APPLICATION NOTE
EDID Configuration
There are two options for configuring a receiver EDID on the AD9388A/ADV7441AFEZ_x Input Module
board:
An external EEPROM per port is provided on the board to which an EDID can be programmed
The AD9388A / ADV7441A have an internal EDID PROM available to the user.
CONFIGURING THE EXTERNAL EDID
The external PROMs U6 (for Port A) and U9 (for Port B) can be programmed via I 2C. This section describes
the steps needed to configure the external EDID PROMs.
1.
2.
3.
4.
5.
6.
Connect the EEPROMs to the I2C bus (jumper setting B) via jumpers K5 and K6 for U6 and jumpers K1
and K4 for U9, as indicated in Table 1. Refer to the Input
AD9388A_ADV7441A_Front_End_Evaluation_Board_Rev.A_Schematics.pdf s for more details.
Connect the platform to PC via USB interface.
Launch the hdcp_eedid_downloader application.
Click on 'Open' and browse to the EDID image file you wish to download in the EDID EEPROMs. An
example EDID image file (.dat file) is available on the evaluation CD. The EDID image file must have a
format that matches the example EDID image.
Click on 'Download' and wait until the operation passes
The EDID is now downloaded to the prom. Reset the jumper for external EDID use (refer to Table 1).
CONFIGURING THE INTERNAL EDID
The configuration of the internal EDID is detailed in the AD9388A / ADV7441A Hardware Manual. It can
also be configured using the Register Control software.
1.
2.
3.
4.
Disconnect the external EDID by removing jumpers K1, K4, K5, and K6, as indicated in Table 1.
Place the required EDID data file in the Setup_Files folder of the software.
From the HDMI drop down menu and from the EDID submenu, select the Load from File option.
Select a .dat file that details the EDID. This program loads the internal EDID appropriately and
enables the EDID for Port A and Port B.
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APPLICATION NOTE
FPGA Configuration
The ATV Mother Board FPGA firmware can be upgraded by programming the XCF16P Platform Flash via
the JTAG interface. The firmware is available in the form of an *.mcs file. The ATV Mother Board FPGA
firmware includes both the evaluation board software driver and the hardware multiplexing function that
routes the data to the backend devices and to the Video Output Module.
The following procedure must be followed:
1.
2.
3.
4.
5.
6.
7.
8.
Ensure the Xilinx iMPACT software and the latest ISE service pack are installed on the PC (these
are available from the Xilinx website, www.xilinx.com.)
Connect the PC to the JTAG connector (J26) on the board via a Crossed Serial to JTAG cable.
Ensure that the JTAG cable is connected in the correct orientation.
Launch the iMPACT application and cancel the dialog box requesting to load a project.
Power up the board and ensure that the JTAG cable is connected. Right click anywhere in the
iMPACT window and select Initialize Chain. The XCF16P PROM and XC3S4000 FPGA will be
detected in the JTAG chain.
Bypass any request to configure the FPGA. This is automatically configured later by the PROM.
When prompted to assign a configuration file to the PROM, select the new MCS file and click
Open.
Right click on the PROM icon and then click on Program. In the Program Options screen, check
Erase before programming and Verify, and then click OK.
After completion, the Programming Succeeded message appears in the iMPACT window.
Page 8 of 9
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APPLICATION NOTE
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List of Figures
Figure 1. ADV Register Software Configuration ............................................................................................. 4
Figure 2. Configuration of AD9388A / ADV7441A with ADV Register Control Software ........................... 4
Figure 3. ATV Mother Board ........................................................................................................................... 5
Figure 4. Video Output Module Board ............................................................................................................. 6
Figure 5. EVAL-AD9388A/ADV7441AFEZ_x Rev. A Input Module Board ................................................. 6
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© 2010 Analog Devices, Inc. All rights reserved.