EE247
Lecture 21
ADC Converters (continued)
– Comparator architecture examples
– Flash ADC sources of error
• Sparkle code
• Meta-stability
– Techniques to reduce flash ADC complexity
• Interpolating
• Folding
– Pipelined ADCs
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 1
Latched Comparator
fs
Vi+
Vi-
Av
Latch
Do+
Do-
Preamp
•
•
•
•
•
•
•
•
Clock rate fs
Resolution
Overload recovery
Input capacitance (and linearity!)
Power dissipation
Common-mode rejection
Kickback noise
…
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 2
Comparators Overdrive Recovery
Linear model for a single-pole amplifier:
UÆ amplification after time ta
During reset amplifier settles
exponentially to its zero input
condition with τ0=RC
Assume Vm Æ maximum input
normalized to 1/2lsb (=1)
EECS 247 Lecture 21: Data Converters
Example: Worst case input/output waveforms
Æ Limit output voltage swing by
1. Passive clamp
2. Active restore
3. Low gain/stage
© 2005 H.K. Page 3
Comparators Overdrive Recovery
Limiting Output
Clamp
Adds parasitic capacitance
EECS 247 Lecture 21: Data Converters
Active Restore
After outputs are latchedÆ Activate φR &
equalize output nodes
© 2005 H.K. Page 4
CMOS Comparator Example
•Flash ADC: 8bits, +-1/2LSB INL @ fs=15MHz (Vref=3.8V, LSB~15mV)
•No offset cancellation
Ref: A. Yukawa, “A CMOS 8-Bit High-Speed A/D Converter IC,” JSSC June 1985, pp. 775-9
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 5
Flash ADC
Comparator with Auto-Zero
Ref: I. Mehr and D. Dalton, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel
Applications,” JSSC July 1999, pp. 912-20.
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 6
Flash ADC
Comparator with Auto-Zero
Voffset
VC + −VC − =
(VR e f + −VR e f − ) −VO ffs et
Ref: I. Mehr and D. Dalton, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel
Applications,” JSSC July 1999, pp. 912-20.
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 7
Flash ADC
Comparator with Auto-Zero
Voffset
Vo
Vo = AP1 ∗ AP2 [(VIn+ −VIn− ) − (VC + − VC − ) − −VO f fs e t ]
Subs tituting for (VC + −VC − ) fr om pre v ious c yc le:
Vo = AP1 ∗ AP2 ⎡⎣(VIn+ −VIn− ) − (VRe f + −VRe f − )⎤⎦
Note: O ffse t is c a nc e lle d & differ enc e be twe e n
in p ut & re fe re nc e e st a b li sh e d
Ref: I. Mehr and D. Dalton, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel
Applications,” JSSC July 1999, pp. 912-20.
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 8
Auto-Zero Implementation
Ref:I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC,” JSSC
March 2000, pp. 318-25
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 9
Comparator Example
• Used in a pipelined ADC with digital
correction
Æno offset cancellation required
• Note: Differential reference
• M7, M8 operate in triode region
• Preamp gain ~10
•Input buffers suppress kick-back
• φ1 high Æ Cs charged to VR & φ2B is
also high Æ current diverted to latch
φ2 highÆ Cs connected to S/Hout &
comparator input (VR-S/Hout), current
sent to preamp Æ comparator
operates
•
Ref: S. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC ,NO.
6, Dec. 1987
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 10
Comparator Example
• Application: Pipelined ADC
with low resolution/stage
• Variation on Yukawa latch
used without preamp
Vo1
• Good for low resolution &
low accuracy ADCs
• During resetÆ φ is low
•
φ high Æ Comparison ….
Ref: T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE
Journal of Solid-State Circuits, vol. 30, pp. 166 - 172, March 1995
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 11
Comparator Example (continued)
• M1, M2, M11, M12 operate in triode
mode
• M11 & M12 added to control comparator
threshold
G1 =
G2 =
μCo x
L
μCo x
L
→ ΔG =
× ⎡⎣W1 (VI1 −Vth ) − W1 1 (VR − −Vth )⎤⎦
Vo2
× ⎣⎡W1 (VI 2 −Vth ) − W1 1 (VR + −Vt h )⎦⎤
μCox
L
× ⎡⎣W1 (VI1 −VI 2 ) − W1 1 (VR − −VR + )⎤⎦
• To 1st order, for W1= W2 & W11=W12
Vth
VVo1
o1
latch
G1
G2
= W11/W1 x VR
where VR = VR+ - VRÆ Eliminates need for resistive divider
Ref: T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE
Journal of Solid-State Circuits, vol. 30, pp. 166 - 172, March 1995
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 12
Bipolar Comparator Example
•Used in 8bit 400Ms/s & 6bit
2Gb/s flash ADC
•Signal amplification during
φ1 high, latch operates
when φ1 low
•Input buffers suppress kickback & input current
•Separate ground and
supply buses for front-end
preamp Æ kick-back noise
reduction
Preamp
Latched Comparator
Ref: Y. Akazawa, et al., "A 400MSPS 8b flash AD conversion LSI," IEEE International Solid-State Circuits
Conference, vol. XXX, pp. 98 - 99, February 1987
Ref: T. Wakimoto, et al, "Si bipolar 2GS/s 6b flash A/D conversion LSI," IEEE International Solid-State Circuits
Conference, vol. XXXI, pp. 232 - 233, February 1988
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 13
Flash Converter Sources of Error
VREF
VIN
fs
R/2
• Comparator input:
R
..
..
.
Encoder
R
Digital
Output
R
R
– Offset
– Nonlinear input capacitance
– Kickback noise (disturbs
reference)
– Signal dependent sampling
time
• Comparator output:
R/2
– Sparkle codes (… 111101000
…)
– Metastability
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 14
Typical Flash Output Encoder
Binary Output (negative)
VDD
b3
b2
b1
b0
0
0
b3 b2 b1 b0
OutputÆ 0 1 1 1
0
1
1
•
Thermometer
code Æ 1-of-n
decoding
•
Final encoding Æ
NOR ROM
0
1
0
1
Thermometer to Binary encoder ROM
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 15
Sparkle Codes
VDD
Erroneous 0
(comparator
offset?)
b3
b2
b1
b0
0
1
1
Correct Output:
1000
0
0
1
1
0
Erroneous
Output:
0000
1
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 16
Sparkle Tolerant Encoder
0
0
0
1
1
0
0
0
1
0
Protects against a single sparkle.
Ref: C. Mangelsdorf et al, “A 400-MHz Flash Converter with Error Correction,” JSSC February
1990, pp. 997-1002
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 17
Meta-Stability
Different gates interpret
metastable output X differently
0
0
0
1
X
1
1
0
Correct output:
1000
Erroneous output:
0000
Solutions:
–Latches (high power)
–Gray encoding
1
Ref: C. Portmann and T. Meng, “Power-Efficient Metastability Error Reduction in CMOS Flash
A/D Converters,” JSSC August 1996, pp. 1132-40
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 18
Gray Encoding
Thermometer Code
Gray
Binary
T1
T2
T3
T4
T5
T6
T7
G3
G2
G1
B3
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
0
1
0
0
1
1
1
1
1
1
0
0
0
1
1
0
1
0
0
1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
•
Each Ti affects only one Gi
Æ Avoids disagreement of interpretation by multiple gates
Protects also against sparkles
Follow Gray encoder by (latch and) binary encoder
•
•
EECS 247 Lecture 21: Data Converters
G1 = T1T3 + T5 T7
G2 = T2 T6
G3 = T4
© 2005 H.K. Page 19
Reducing Flash ADC Complexity
E.g. 10-bit “straight” flash
–
–
–
–
–
Input range: 0 … 1V
LSB = Δ: ~ 1mV
Comparators: 1023 with offset << LSB
Input capacitance: 1023 * 100fF = 102pF
Power: 1023 * 3mW = 3W
Techniques to reduce complexity & power dissipation :
–
–
–
–
Interpolation
Folding
Folding & Interpolation
Two-step, pipelining
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 20
Interpolation
• Idea
– Interpolation between preamp outputs
• Reduces number of preamps
– Reduced input capacitance
– Reduced area, power dissipation
• Same number of latches
• Important “side-benefit”
– Decreased sensitivity to preamp offset
Æ improved DNL
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 21
Preamp Output
Vin
A1
A1
A2
0.5
Preamp Output
0.4
A2
0.3
0.2
0.1
0
-0.1
Zero crossings (to be
detected by latches) at Vin =
-0.2
-0.3
-0.4
-0.5
0
0.5
1
1.5
Vin / Δ
2
2.5
EECS 247 Lecture 21: Data Converters
3
Vref1 = 1 Δ
Vref2 = 2 Δ
© 2005 H.K. Page 22
Simulink Model
Vin
1
Vin
Vi
A2
Preamp2
2*Delta
Vref2
2
Y
A1
Preamp1
1*Delta
Vref1
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 23
Preamp Output
Differential Preamp Output
0.6
0.4
0.2
0
-0.2
-0.4
A1
-A1
A2
-A 2
0
0.5
1
1.5
2
0.6
0.4
0.2
0
-0.2
-0.4
2.5
Zero crossings at Vin =
3
A1+A2
A1+A2
0
0.5
1
1.5
Vin / Δ
2
EECS 247 Lecture 21: Data Converters
2.5
Vref1 = 1 Δ
Vref12 = 0.5*(1+2) Δ
Vref2 = 2 Δ
3
© 2005 H.K. Page 24
Interpolation in Flash ADC
Vin
A1
Half as many reference
voltages and preamps
Interpolation factor:x2
A2
Possible to accomplish
higher interpolation factor
Æ Resistive interpolation
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 25
Resistive Interpolation
• Resistors produce
additional levels
• With 4 resistors,
the “interpolation
factor” M=8
(ratio of
latches/preamps)
Ref: H. Kimura et al, “A
10-b 300-MHz
Interpolated-Parallel
A/D Converter,”
JSSC April 1993, pp.
438-446
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 26
DNL Improvement
• Preamp offset distributed over
M resistively interpolated
voltages:
Æ impact on DNL divided by
M
• Latch offset divided by gain of
preamp
Æ use “large” preamp gain …
Ref: H. Kimura et al, “A
10-b 300-MHz
Interpolated-Parallel
A/D Converter,”
JSSC April 1993, pp.
438-446
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 27
Preamp Output
Preamp Input Range
0.6
0.4
0.2
0
-0.2
-0.4
A1
-A1
A2
-A2
0
0.5
1
1.5
2
2.5
0.6
0.4
0.2
0
-0.2
-0.4
3
A1+A2
A1 +A2
0
0.5
1
1.5
Vin / Δ
2
2.5
EECS 247 Lecture 21: Data Converters
Linear preamp input ranges
must overlap
i.e. range > Δ
Sets upper bound on preamp
gain << VDD / Δ
3
© 2005 H.K. Page 28
Interpolated-Parallel ADC
10-bit overall resolution:
Æ7-bit flash (127
comparators and 128
resistors) & x8
interpolation
Ref: H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,” JSSC April 1993, pp.
438-446
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 29
Measured Performance
(7+3)
Low input
capacitance
Ref: H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,” JSSC April 1993, pp.
438-446
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 30
Folding Converter
MSB
ADC
VIN
Digital
Output
LSB
ADC
Folding Circuit
• Significantly fewer comparators than flash ~2B/2+1
• Fast
• Nonidealities in folder limit resolution to ~10Bits
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 31
Folding
• Folder maps input to
smaller range
• MSB ADC determines
which fold input is in
• LSB ADC determines
position within fold
Folder Output
1.2
0.8
LSB
ADC
0.4
0
0
• Logic circuit combines
LSB and MSB results
0.5 1
1.5 2
2.5 3
Normalized Input
3.5 4
MSB ADC
Analog Input
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 32
Generating Folds
A1-A2
A1
0.5
0
-0.5
0
0
-0.5
A1-A2+A3
-0.5
A1-A2
0
0.5
A3
A2
0.5
1
0.5
0.5
0
1
0.5
0
0.5
1
1.5
2
Vin / Δ
2.5
3
3.5
0
-0.5
4
0
0.5
1
1.5
2
Vin / Δ
EECS 247 Lecture 21: Data Converters
2.5
3
3.5
4
© 2005 H.K. Page 33
Folding Circuit
VDD
R1
R2
-Vo+
M1
M2
Vref1
M3
I1
M4
I2
Vref2
M5
M6
Vref3
M7
M8
Vref4
I4
I3
Vin
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 34
Folder Output
CMOS Folder Output
0.5
Ideal
Folder
0
-0.5
Accurate only at
zero-crossings
CMOS
Folder
0
0.5
1
1.5
0.5
1
1.5
2
2.5
3
3.5
4
2
2.5
3
3.5
4
0.1
Error
0.05
0
-0.05
-0.1
0
Lowdown Æ
In fact, most folding
ADCs do not use the
folds, but only the
zero-crossings!
Vin /Δ
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 35
Parallel Folders
Folder 4
Fine Flash
ADC 4
Vref + 3/4 * Δ
Folder 3
Fine Flash
ADC 3
Vref + 2/4 *Δ
Folder 2
Logic
Fine Flash
ADC 2
Vref + 1/4 *Δ
Folder 1
Fine Flash
ADC 1
Vref + 0/4 *Δ
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 36
Parallel Folder Outputs
0.5
F1
F2
F3
F4
0.4
0.3
• 4 Folders with 4 folds
each
• 16 Zero crossings
• Æ only 4 LSB bits
Folder Output
0.2
0.1
0
-0.1
• Better resolution
• More folders
-0.2
-0.3
Æ Large complexity
-0.4
-0.5
0
1
2
3
4
5
• Interpolation
Vin / Δ
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 37
Folding & Interpolation
Folder 4
Vref + 3/4 * Δ
Folder 3
Vref + 2/4 *Δ
Folder 2
Vref + 1/4 *Δ
Fine
Flash
ADC
E
N
C
O
D
E
R
Folder 1
Vref + 0/4 *Δ
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 38
Folder / Interpolator Output
Folder / Interpolator Output
0.5
F1
F2
I1
I2
I3
0.4
0.3
0.04
0.2
0.02
0.1
0
0
-0.02
-0.1
1.5
-0.2
1.6
1.7
1.8
-0.3
-0.4
-0.5
0
1
2
3
Vin / Δ
4
5
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 39
Folder / Interpolator Output
Folder / Interpolator Output
0.5
0.06
F1
F2
I1
I2
I3
0.4
0.3
0.04
0.02
0
0.2
-0.02
0.1
-0.04
0
-0.06
1.5 1.6 1.7 1.8 1.9
-0.1
2
2.1
-0.2
-0.3
-0.4
-0.5
0
1
2
3
Vin / Δ
EECS 247 Lecture 21: Data Converters
4
5
Interpolate only
between closely
spaced folds to avoid
nonlinear distortion
© 2005 H.K. Page 40
A 70-MS/s 110-mW 8-b CMOS Folding
and Interpolating A/D Converter
Ref: B. Nauta and G. Venes, JSSC Dec 1985, pp. 1302-8
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 41
A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 42
A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 43
Pipelined ADCs
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 44
Pipelined A/D Converters
• Ideal operation
• Errors and correction
– Redundancy
– Digital calibration
• Implementation
– Practical circuits
– Stage scaling
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 45
Block Diagram
Vin
Stage 1
B1 Bits
Vres1
Stage 2
B2 Bits
Vres2
MSB...
Stage k
Bk Bits
...LSB
Align and Combine Data
Digital output
(B1 + B2 + ... + Bk) Bits
• Idea: Cascade several low resolution stages to obtain
high overall resolution
• Each stage performs coarse A/D conversion and
computes its quantization error, or "residue"
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 46
Characteristics
• Number of components (stages) grows
linearly with resolution
• Pipelining
– Trading latency for conversion speed
– Latency may be an issue in e.g. control systems
– Throughput limited by speed of one stage → Fast
• Versatile: 8...16bits, 1...200MS/s
• Many analog circuit non-idealities can
be corrected digitally
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 47
Concurrent Stage Operation
φ1
φ2
Vin
CLK
acquire
convert
convert
acquire
Stage 1
B1 Bits
Stage 2
B2 Bits
...
...
Stage k
Bk Bits
φ1
φ2
Align and Combine Data
Digital output
(B1 + B2 + ... + Bk) Bits
• Stages operate on the input signal like a shift register
• New output data every clock cycle, but each stage
introduces at least ½ clock cycle latency
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 48
Data Alignment
φ1
φ2
Vin
CLK
acquire
convert
convert
acquire
Stage 1
B1 Bits
Stage 2
B2 Bits
...
...
Stage k
Bk Bits
φ1
φ2
+
CLK
Dout
+
CLK
CLK
• Digital shift register aligns sub-conversion
results in time
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 49
Latency
[Analog Devices, AD 9226 Data Sheet]
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 50
Pipelined ADC Analysis
• Ignore timing and use simple static model
Vin
Stage 1
B1 Bits
Vres1
Stage 2
B2 Bits
Vres2
+
Stage k
Bk Bits
Dout
+
• Let's first look at "two-stage pipeline"
– E.g.: Two cascaded 2-bit ADCs to get 4 bits of
total resolution
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 51
Two Stage Example
11
2-bit ADC
Vin
Vin
10
Dout
2-bit ADC
01
00
0
???
[LSB]
Dout = Vin+ εq1
2
3
0.5
εq1
+
1
1
0
-0.5
-1
0 1 2 3
ADC Input Voltage [LSB]
•
•
•
Using only one ADC: output contains large quantization error
"Missing voltage" or "residue" (-εq1)
Idea: Use second ADC to quantize and add -εq1
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 52
Two Stage Example
2-bit ADC
Vin
2-bit DAC
“Coarse“
-
+
-εq1
2-bit ADC
“Fine“
-εq1 + εq2
+
Dout= Vin + ε
ε
-ε
+
q1 q1 q2
• Use DAC to compute missing voltage
• Add quantized representation of missing voltage
• Why does this help? How about εq2 ?
EECS 247 Lecture 21: Data Converters
© 2005 H.K. Page 53
Two Stage Example
−εq1
11
V
ref1
10
/22
Vref1 Vin
V
01
ref2
Second ADC
“Fine“
00
00
01
10
11
First ADC
“Coarse“
• Fine ADC is re-used 22 times
• Fine ADC's full scale range needs to span only 1 LSB of coarse
quantizer
V
V
ε q2 =
EECS 247 Lecture 21: Data Converters
ref 2
2
2
=
ref 1
2 ⋅ 22
2
© 2005 H.K. Page 54
Two Stage Pipelined ADC Transfer Function
Dout
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Coarse
Bits
(MSB)
Fine
Bits
(LSB)
EECS 247 Lecture 21: Data Converters
Vref1
Vin
© 2005 H.K. Page 55