Lecture 6: DC & Transient
Response
Deming Chen
Slides based on the initial set from David Harris
CMOS VLSI Design 4th Ed.
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Outline
Pass Transistors
DC Response
Logic Levels and Noise Margins
Transient Response
RC Delay Models
Delay Estimation
 Readings 2.5, 4.1-4.3
DC and Transient Response
CMOS VLSI Design 4th Ed.
2
Pass Transistors
 We have assumed source is grounded
 What if source > 0?
VDD
– e.g. pass transistor passing VDD
VDD
 Vg = VDD
– If Vs > VDD-Vt, Vgs < Vt
– Hence transistor would turn itself off
 nMOS pass transistors pull no higher than VDD-Vtn
– Called a degraded “1”
– Approach degraded value slowly (low Ids)
 pMOS pass transistors pull no lower than Vtp
 Transmission gates are needed to pass both 0 and 1
DC and Transient Response
CMOS VLSI Design 4th Ed.
3
Pass Transistor Ckts
DC and Transient Response
CMOS VLSI Design 4th Ed.
4
DC Response
 DC Response: Vout vs. Vin for a gate
 Ex: Inverter
– When Vin = 0
->
Vout = VDD
– When Vin = VDD
->
Vout = 0
VDD
– In between, Vout depends on
Idsp
transistor size and current
Vin
Vout
– By KCL, must settle such that
Idsn
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight
DC and Transient Response
CMOS VLSI Design 4th Ed.
5
Transistor Operation
 Current depends on region of transistor behavior
 For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?
DC and Transient Response
CMOS VLSI Design 4th Ed.
6
Cutoff
nMOS Operation
Vgsn < Vtn
Vin < Vtn
Vgsn = Vin
Vdsn = Vout
DC and Transient Response
Linear
Saturated
Vgsn > Vtn
Vin > Vtn
Vdsn < Vgsn – Vtn
Vout < Vin - Vtn
Vgsn > Vtn
Vin > Vtn
Vdsn > Vgsn – Vtn
Vout > Vin - Vtn
VDD
Vin
CMOS VLSI Design 4th Ed.
Idsp
Idsn
Vout
7
Cutoff
pMOS Operation
Vgsp > Vtp
Vin > VDD + Vtp
Vgsp = Vin - VDD
Vdsp = Vout - VDD
DC and Transient Response
Linear
Saturated
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp > Vgsp – Vtp
Vout > Vin - Vtp
Vtp < 0
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp < Vgsp – Vtp
Vout < Vin - Vtp
VDD
Vin
CMOS VLSI Design 4th Ed.
Idsp
Idsn
Vout
8
I-V Characteristics
 Make pMOS is wider than nMOS such that bn = bp
DC and Transient Response
CMOS VLSI Design 4th Ed.
9
Current vs. Vout, Vin
Idsn, |Idsp|
Vin0
Vin5
Vin1
Vin4
Vin2
Vin3
Vin3
Vin4
DC and Transient Response
Vout
CMOS VLSI Design 4th Ed.
VDD
Vin2
Vin1
10
Load Line Analysis
 For a given Vin:
– Plot Idsn, Idsp vs. Vout
– Vout must be where |currents| are equal in
Idsn, |Idsp|
Vin0
Vin5
Vin1
Vin4
Vin2
Vin3
Vin3
Vin4
DC and Transient Response
Vout
VDD
CMOS VLSI Design 4th Ed.
Vin2
Vin1
VDD
Vin
Idsp
Idsn
Vout
11
Load Line Analysis
 Vin = 0V
0.4V
0.6V
0.8V
.2V
DD DD
DD
Idsn, |Idsp|
Vin0
Vin5
Vin1
Vin4
Vin2
Vin3
Vin3
Vin4
DC and Transient Response
Vout
CMOS VLSI Design 4th Ed.
VDD
Vin2
Vin1
in0
12
DC Transfer Curve
 Transcribe points onto Vin vs. Vout plot
Vin0
Vin5
Vin1
Vin4
Vin2
Vin3
Vin3
Vin4
Vout
DC and Transient Response
VDD
Vin2
Vin1
VDD
Vin0
Vin1
Vin2
B
A
Vout
C
Vin3
0
CMOS VLSI Design 4th Ed.
Vtn
VDD/2
Vin
D
Vin4
E
VDD+Vtp
Vin5
VDD
13
Operating Regions
 Revisit transistor operating regions
Region
A
B
C
D
E
nMOS
Cutoff
Saturation
Saturation
Linear
Linear
pMOS
Linear
Linear
Saturation
Saturation
VDD
A
Vout
C
Cutoff
0
DC and Transient Response
B
CMOS VLSI Design 4th Ed.
Vtn
VDD/2
Vin
D
E
VDD+Vtp
VDD
14
Beta Ratio
 If bp / bn  1, switching point will move from VDD/2
 Called skewed gate
 Other gates: collapse into equivalent inverter
VDD
bp
 10
bn
Vout
2
1
0.5
bp
 0.1
bn
0
DC and Transient Response
Vin
VDD
CMOS VLSI Design 4th Ed.
15
Noise Margins
 How much noise can a gate input see before it does
not recognize the input?
Logical High
Output Range
Output Characteristics
VDD
Input Characteristics
NMH
VIH
VIL
Logical Low
Output Range
DC and Transient Response
Logical High
Input Range
VOH
NML
Indeterminate
Region
VOL
GND
CMOS VLSI Design 4th Ed.
Logical Low
Input Range
16
Logic Levels
 To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic
Vout
Unity Gain Points
Slope = -1
VDD
VOH
bp/b n > 1
Vin
VOL
0
Vtn
DC and Transient Response
VIL VIH VDD- VDD
|Vtp|
Vout
Vin
CMOS VLSI Design 4th Ed.
17
Transient Response
 DC analysis tells us Vout if Vin is constant
 Transient analysis tells us Vout(t) if Vin(t) changes
– Requires solving differential equations
 Input is usually considered to be a step or ramp
– From 0 to VDD or vice versa
DC and Transient Response
CMOS VLSI Design 4th Ed.
18
Inverter Step Response
 Ex: find step response of inverter driving load cap
Vin (t )  u(t  t0 )VDD
Vout (t  t0 )  VDD
Vin(t)
dVout (t )
I dsn (t )

dt
Cload

0


2
b
I dsn (t )  
V

V


DD
t
2

 b  VDD  Vt  Vout (t )
2
 
DC and Transient Response
Vout(t)
Cload
Idsn(t)
Vin(t)
t  t0
Vout  VDD  Vt
 V (t ) V  V  V
 out
out
DD
t

CMOS VLSI Design 4th Ed.
t0
Vout(t)
t
19
Delay Definitions
 tpdr: rising propagation delay
– From input to rising output
crossing VDD/2
 tpdf: falling propagation delay
– From input to falling output
crossing VDD/2
 tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
 tr: rise time
– From output crossing 0.2
VDD to 0.8 VDD
 tf: fall time
– From output crossing 0.8
VDD to 0.2 VDD
DC and Transient Response
CMOS VLSI Design 4th Ed.
20
Delay Definitions
 tcdr: rising contamination delay
– From input to rising output crossing VDD/2
 tcdf: falling contamination delay
– From input to falling output crossing VDD/2
 tcd: average contamination delay
– tpd = (tcdr + tcdf)/2
DC and Transient Response
CMOS VLSI Design 4th Ed.
21
Simulated Inverter Delay
 Solving differential equations by hand is too hard
 SPICE simulator solves the equations numerically
– Uses more accurate I-V models too!
 But simulations take time to write, may hide insight
2.0
1.5
(V)
1.0
0.5
Vin
tpdf = 66ps
tpdr = 83ps
Vout
0.0
0.0
200p
DC and Transient Response
400p
t(s)
600p
800p
1n
CMOS VLSI Design 4th Ed.
22
Delay Estimation
 We would like to be able to easily estimate delay
– Not as accurate as simulation
– But easier to ask “What if?”
 The step response usually looks like a 1st order RC
response with a decaying exponential.
 Use RC delay models to estimate delay
– C = total capacitance on output node
– Use effective resistance R
– So that tpd = RC
 Characterize transistors by finding their effective R
– Depends on average current as gate switches
DC and Transient Response
CMOS VLSI Design 4th Ed.
23
Effective Resistance
 Shockley models have limited value
– Not accurate enough for modern transistors
– Too complicated for much hand analysis
 Simplification: treat transistor as resistor
– Replace Ids(Vds, Vgs) with effective resistance R
• Ids = Vds/R
– R averaged across switching of digital gate
 Too inaccurate to predict current at any given time
– But good enough to predict RC delay
DC and Transient Response
CMOS VLSI Design 4th Ed.
24
RC Delay Model
 Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
 Capacitance proportional to width
 Resistance inversely proportional to width
d
g
d
k
s
R/k
g
kC
s
DC and Transient Response
s
kC
kC
g
d
k
s
CMOS VLSI Design 4th Ed.
g
kC
2R/k
kC
kC
d
25
RC Values
 Capacitance
– C = Cg = Cs = Cd = 2 fF/mm of gate width in 0.6 mm
– Gradually decline to 1 fF/mm in 65 nm
 Resistance
– R  10 KW•mm in 0.6 mm process
– Improves with shorter channel lengths
– 1.25 KW•mm in 65 nm process
 Unit transistors
– May refer to minimum contacted device (4/2 l)
– Or maybe 1 mm wide device
– Doesn’t matter as long as you are consistent
DC and Transient Response
CMOS VLSI Design 4th Ed.
26
Inverter Delay Estimate
 Estimate the delay of a fanout-of-1 inverter
R
A
2 Y
1
2C
2
1
d = 6RC
DC and Transient Response
2C
R
C
2C
Y
C
2C
R
C
2C
C
C
CMOS VLSI Design 4th Ed.
27
Delay Model Comparison
DC and Transient Response
CMOS VLSI Design 4th Ed.
28
Example: 3-input NAND
 Sketch a 3-input NAND with transistor widths chosen to
achieve effective rise and fall resistances equal to a unit
inverter (R).
2
2
2
3
3
3
DC and Transient Response
CMOS VLSI Design 4th Ed.
29
3-input NAND Caps
 Annotate the 3-input NAND gate with gate and diffusion
capacitance.
2C
2
2C
2C
2C
2
2C
2C
3C
3C
3C
DC and Transient Response
2C
2
3
3
3
CMOS VLSI Design 4th Ed.
2C
2C
3C
3C
3C
3C
30
Elmore Delay
 ON transistors look like resistors
 Pullup or pulldown network modeled as RC ladder
 Elmore delay of RC ladder
t pd 

Ri to  sourceCi
 R1C1   R1  R2  C2  ...   R1  R2  ...  RN  CN
nodes i
R1
DC and Transient Response
R2
R3
C1
C2
RN
C3
CMOS VLSI Design 4th Ed.
CN
31
Example: 3-input NAND
 Estimate worst-case rising and falling delay of 3-input NAND
driving h identical gates.
2
2
DC and Transient Response
3
3 n1
h copies
t pdr   9  5h  RC
2
3
Y
9C
5hC
n2
3C
3C
t pdf   3C   R3    3C   R3  R3    9  5h  C   R3  R3  R3 
 12  5h  RC
CMOS VLSI Design 4th Ed.
32
Delay Components
 Delay has two parts
– Parasitic delay
• 9 or 12 RC
• Independent of load
– Effort delay
• 5h RC
• Proportional to load capacitance
DC and Transient Response
CMOS VLSI Design 4th Ed.
33
Contamination Delay
 Best-case (contamination) delay can be substantially less than
propagation delay.
 Ex: If all three inputs fall simultaneously
2
2
2
3
3 n1
3
Y
9C
5hC
n2
3C
3C
tcdr
DC and Transient Response
5 
R 
  9  5h  C      3  h  RC
3 
3 
CMOS VLSI Design 4th Ed.
34
Diffusion Capacitance
 We assumed contacted diffusion on every s / d.
 Good layout minimizes diffusion area
 Ex: NAND3 layout shares one diffusion contact
– Reduces output capacitance by 2C
– Merged uncontacted diffusion might help too
2C
Shared
Contacted
Diffusion
Merged
Uncontacted
Diffusion
2C
Isolated
Contacted
Diffusion
2
3C 3C 3C
DC and Transient Response
CMOS VLSI Design 4th Ed.
2
2
3
7C
3
3C
3
3C
35
Layout Comparison
 Which layout is better?
VDD
A
B
VDD
Y
GND
DC and Transient Response
A
B
Y
GND
CMOS VLSI Design 4th Ed.
36
Summary
 Continued on transistors
– Pass Transistors, Operations, I-V Characteristics,
DC Response, Noise Margins, Transient
Response, etc.
 Delay Models and Delay Estimation
 Next lecture
– SPICE
– Readings 8.1-8.2
CMOS VLSI Design 4th Ed.
37