DISCRETE SEMICONDUCTORS
DATA SHEET
BF1100WR
Dual-gate MOS-FET
Product specification
1995 Apr 25
NXP Semiconductors
Product specification
Dual-gate MOS-FET
BF1100WR
FEATURES
PINNING
 Specially designed for use at 9 to 12 V supply voltage
 Short channel transistor with high forward transfer
admittance to input capacitance ratio
 Low noise gain controlled amplifier up to 1 GHz
 Superior cross-modulation performance during AGC.
PIN
SYMBOL
DESCRIPTION
1
s, b
2
d
drain
3
g2
gate 2
4
g1
gate 1
source
APPLICATIONS
 VHF and UHF applications such as television tuners and
professional communications equipment.
d
handbook, halfpage
3
4
DESCRIPTION
g2
Enhancement type field-effect transistor in a plastic
microminiature SOT343R package. The transistor
consists of an amplifier MOS-FET with source and
substrate interconnected and an internal bias circuit to
ensure good cross-modulation performance during AGC.
g1
2
1
Top view
s,b
MAM192
CAUTION
Marking code: MF.
The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.
Fig.1 Simplified outline (SOT343R) and symbol.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
drain-source voltage


14
V
ID
drain current


30
mA
Ptot
total power dissipation


280
mW
Tj
operating junction temperature


150
C
yfs
forward transfer admittance
24
28
33
mS
Cig1-s
input capacitance at gate 1

2.2
2.6
pF
Crs
reverse transfer capacitance
f = 1 MHz

25
35
fF
F
noise figure
f = 800 MHz

2

dB
1995 Apr 25
2
NXP Semiconductors
Product specification
Dual-gate MOS-FET
BF1100WR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
drain-source voltage

14
V
ID
drain current

30
mA
IG1
gate 1 current

10
mA
IG2
gate 2 current

10
mA
Ptot
total power dissipation

280
mW
Tstg
storage temperature
65
+150
C
Tj
operating junction temperature

+150
C
see Fig.2; up to Tamb = 50 C; note 1
Note
1. Device mounted on a printed-circuit board.
MLD156
MLD180
40
300
handbook, halfpage
Y fs
(mS)
Ptot
(mW)
30
200
20
100
10
0
0
0
50
100
50
150
200
Tamb ( oC)
Fig.3
Fig.2 Power derating curve.
1995 Apr 25
3
0
50
100
150
T j ( oC)
Forward transfer admittance as a function
of junction temperature; typical values.
NXP Semiconductors
Product specification
Dual-gate MOS-FET
BF1100WR
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth j-a
thermal resistance from junction to ambient
note 1
350
K/W
Rth j-s
thermal resistance from junction to soldering point
Ts = 91 C; note 2
210
K/W
Notes
1. Device mounted on a printed-circuit board.
2. Ts is the temperature at the soldering point of the source lead.
STATIC CHARACTERISTICS
Tj = 25 C; unless otherwise specified.
SYMBOL
PARAMETER
V(BR)G1-SS
gate 1-source breakdown voltage
V(BR)G2-SS
V(F)S-G1
CONDITIONS
MIN.
MAX.
UNIT
VG2-S = VDS = 0; IG1-S = 1 mA
13.2
20
V
gate 2-source breakdown voltage
VG1-S = VDS = 0; IG2-S = 1 mA
13.2
20
V
forward source-gate 1 voltage
VG2-S = VDS = 0; IS-G1 = 10 mA
0.5
1.5
V
V(F)S-G2
forward source-gate 2 voltage
VG1-S = VDS = 0; IS-G2 = 10 mA
0.5
1.5
V
VG1-S(th)
gate 1-source threshold voltage
VG2-S = 4 V; VDS = 9 V;
ID = 20 A
0.3
1
V
VG2-S = 4 V; VDS = 12 V;
ID = 20 A
0.3
1
V
VG1-S = 4 V; VDS = 9 V;
ID = 20 A
0.3
1.2
V
VG1-S = 4 V; VDS = 12 V;
ID = 20 A
0.3
1.2
V
VG2-S = 4 V; VDS = 9 V;
RG1 = 180 k; note 1
8
13
mA
VG2-S = 4 V; VDS = 12 V;
RG1 = 250 k; note 2
8
13
mA
VG2-S(th)
IDSX
gate 2-source threshold voltage
drain-source current
IG1-SS
gate 1 cut-off current
VG2-S = VDS = 0; VG1-S = 12 V

50
nA
IG2-SS
gate 2 cut-off current
VG1-S = VDS = 0; VG2-S = 12 V

50
nA
Notes
1. RG1 connects gate 1 to VGG = 9 V; see Fig.26.
2. RG1 connects gate 1 to VGG = 12 V; see Fig.26.
1995 Apr 25
4
NXP Semiconductors
Product specification
Dual-gate MOS-FET
BF1100WR
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 C; VG2-S = 4 V; ID = 10 mA; unless otherwise specified.
SYMBOL
yfs
PARAMETER
CONDITIONS
forward transfer admittance
input capacitance at gate 1
Cig1-s
input capacitance at gate 2
Cig2-s
drain-source capacitance
Cos
MIN.
TYP.
MAX.
UNIT
pulsed; Tj = 25 C
VDS = 9 V
24
28
33
mS
VDS = 12 V
24
28
33
mS
VDS = 9 V

2.2
2.6
pF
VDS = 12 V

2.2
2.6
pF
VDS = 9 V

1.6

pF
VDS = 12 V

1.4

pF
VDS = 9 V

1.4
1.8
pF
VDS = 12 V

1.1
1.5
pF
VDS = 9 V

25
35
fF
VDS = 12 V

25
35
fF
VDS = 9 V

2
2.8
dB
VDS = 12 V

2
2.8
dB
f = 1 MHz
f = 1 MHz
f = 1 MHz
reverse transfer capacitance f = 1 MHz
Crs
F
f = 800 MHz; GS = GSopt; BS = BSopt
noise figure
MLD157
MLD158
120
0
handbook, halfpage
handbook,
gain halfpage
Vunw
(dBμV)
reduction
(dB)
10
(1)
110
(2)
20
100
30
90
40
80
50
0
1
2
3
4
0
10
20
30
VAGC (V)
(1) RG = 250 k to VGG = 12 V.
(2) RG = 180 k to VGG = 9 V.
fw = 50 MHz; funw = 60 MHz; Tamb = 25 C.
f = 50 MHz.
Tj = 25 C.
Fig.5
Fig.4
1995 Apr 25
40
50
gain reduction (dB)
Gain reduction as a function of the AGC
voltage; typical values.
5
Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; see Fig.26.
NXP Semiconductors
Product specification
Dual-gate MOS-FET
BF1100WR
MLD159
MLD160
20
20
handbook, halfpage
handbook, halfpage
ID
(mA)
16
ID
(mA)
16
V G1 S = 1.4 V
1.3 V
1.2 V
12
V G2 S = 4 V 3 V
2.5 V
2V
12
1.1 V
1.5 V
8
8
1.0 V
0.9 V
4
4
1V
0
0
0
4
8
12
0
16
0.4
0.8
1.2
1.6
2.0
V G1 S (V)
V DS (V)
VG2-S = 4 V.
Tj = 25 C.
VDS = 9 to 12 V.
Tj = 25 C.
Fig.6 Output characteristics; typical values.
Fig.7 Transfer characteristics; typical values.
MLD162
MLD161
250
40
handbook, halfpage
handbook, halfpage
I G1
(μA)
V G2 S = 4 V
y fs
(mS)
200
3.5 V
V G2 S = 4 V
3.5 V
30
3V
150
3V
20
100
2.5 V
10
2V
50
2.5 V
2V
0
0
0
1
2
V G1 S (V)
0
3
VDS = 9 to 12 V.
Tj = 25 C.
Fig.8
1995 Apr 25
10
20
I D (mA)
30
VDS = 9 to 12 V.
Tj = 25 C.
Gate 1 current as a function of gate 1
voltage; typical values.
Fig.9
6
Forward transfer admittance as a function
of drain current; typical values.
NXP Semiconductors
Product specification
Dual-gate MOS-FET
BF1100WR
MLD164
MLD163
16
20
handbook, halfpage
handbook, halfpage
ID
(mA)
R G1 = 100 kΩ
ID
(mA)
12
147 kΩ
15
180 kΩ
205 kΩ
8
249 kΩ
10
301 kΩ
402 kΩ
511 kΩ
4
5
0
0
0
20
40
60
I G1 (μA)
80
0
4
8
12
V GG = V DS (V)
16
VG2-S = 4 V.
RG1 connected to VGG.
Tj = 25 C.
VDS = 9 to 12 V.
VG2-S = 4 V.
Tj = 25 C.
Fig.11 Drain current as a function of gate 1 supply
voltage (= VGG) and drain supply voltage;
typical values; see Fig.26.
Fig.10 Drain current as a function of gate 1 current;
typical values.
MLD165
12
MLD166
12
handbook, halfpage
handbook, halfpage
ID
(mA)
ID
(mA)
8
8
4
4
0
0
0
2
4
6
8
10
V GG (V)
0
4
8
V GG (V)
12
VDS = 9 V; VG2-S = 4 V.
RG1 = 180 kconnected to VGG); Tj = 25 C.
VDS = 12 V; VG2-S = 4 V.
RG1 = 250 k (connected to VGG); Tj = 25 C.
Fig.12 Drain current as a function of gate 1 voltage
(= VGG); typical values; see Fig.26.
Fig.13 Drain current as a function of gate 1 voltage
(= VGG); typical values; see Fig.26.
1995 Apr 25
7
NXP Semiconductors
Product specification
Dual-gate MOS-FET
BF1100WR
MLD167
50
MLD168
50
handbook, halfpage
handbook, halfpage
I G1
(μA)
40
I G1
(μA)
40
V GG = 9 V
V GG = 12 V
11 V
8V
10 V
7V
30
9V
30
8V
6V
7V
5V
20
20
4V
10
10
0
0
0
2
4
V G2 S (V)
6
0
2
4
V G2 S (V)
6
VDS = 9 V.
RG1 = 180 k (connected to VGG); Tj = 25 C.
VDS = 12 V.
RG1 = 250 k (connected to VGG); Tj = 25 C.
Fig.14 Gate 1 current as a function of gate 2 voltage;
typical values.
Fig.15 Gate 1 current as a function of gate 2 voltage;
typical values.
MLD169
MLD170
16
16
handbook, halfpage
handbook, halfpage
ID
(mA)
ID
(mA)
V GG = 9 V
12
12
V GG = 12 V
8
11 V
10 V
9V
8V
7V
8V
7V
6V
8
5V
4V
4
4
0
0
0
2
4
V G2 S (V)
6
0
VDS = 9 V.
RG1 = 180 k (connected to VGG); Tj = 25 C.
4
V G2 S (V)
6
VDS = 12 V.
RG1 = 250 k (connected to VGG); Tj = 25 C.
Fig.16 Drain current as a function of the gate 2
voltage; typical values; see Fig.26.
1995 Apr 25
2
Fig.17 Drain current as a function of the gate 2
voltage; typical values; see Fig.26.
8
NXP Semiconductors
Product specification
Dual-gate MOS-FET
BF1100WR
MLD181
10 2
handbook, halfpage
MLD182
10 3
y is
(mS)
10 3
ϕ rs
(deg)
y rs
(μS)
10 2
10
ϕ rs
b is
10 2
y rs
1
10
10
g is
10 1
10
102
f (MHz)
1
1
10 3
10
VDS = 9 V; VG2 = 4 V.
ID = 10 mA; Tamb = 25 C.
102
f (MHz)
10 3
VDS = 9 V; VG2 = 4 V.
ID = 10 mA; Tamb = 25 C.
Fig.18 Input admittance as a function of
frequency; typical values.
MLD183
10 2
y fs
MLD184
10 2
10halfpage
handbook,
yos
(mS)
ϕ fs
(deg)
y fs
(mS)
Fig.19 Reverse transfer admittance and phase as
a function of frequency; typical values.
bos
1
ϕ fs
10
10
10 1
gos
10 2
10
1
1
10
102
f (MHz)
10 3
VDS = 9 V; VG2 = 4 V.
ID = 10 mA; Tamb = 25 C.
f (MHz)
10 3
VDS = 9 V; VG2 = 4 V.
ID = 10 mA; Tamb = 25 C.
Fig.20 Forward transfer admittance and phase as
a function of frequency; typical values.
1995 Apr 25
102
Fig.21 Output admittance as a function of
frequency; typical values.
9
NXP Semiconductors
Product specification
Dual-gate MOS-FET
BF1100WR
MLD185
10 2
handbook, halfpage
MLD186
10 3
y is
(mS)
10 3
ϕ rs
(deg)
y rs
(μS)
10 2
10
ϕ rs
b is
10 2
y rs
1
10
10
g is
10 1
10
102
f (MHz)
1
1
10 3
10
102
f (MHz)
10 3
VDS = 12 V; VG2 = 4 V.
ID = 10 mA; Tamb = 25 C.
VDS = 12 V; VG2 = 4 V.
ID = 10 mA; Tamb = 25 C.
Fig.22 Input admittance as a function of
frequency; typical values.
MLD187
10 2
y fs
MLD188
10 2
10
handbook, halfpage
yos
(mS)
ϕ fs
(deg)
y fs
(mS)
Fig.23 Reverse transfer admittance and phase as
a function of frequency; typical values.
bos
1
ϕ fs
10
10
10 1
gos
10 2
10
1
1
10
102
f (MHz)
10 3
f (MHz)
10 3
VDS = 12 V; VG2 = 4 V.
ID = 10 mA; Tamb = 25 C.
VDS = 12 V; VG2 = 4 V.
ID = 10 mA; Tamb = 25 C.
Fig.24 Forward transfer admittance and phase as
a function of frequency; typical values.
1995 Apr 25
102
Fig.25 Output admittance as a function of
frequency; typical values.
10
NXP Semiconductors
Product specification
Dual-gate MOS-FET
BF1100WR
VAGC
handbook, full pagewidth
R1
10 k Ω
C1
4.7 nF
C2
R GEN
50 Ω
R2
50 Ω
C3
DUT
4.7 nF
12 pF
L1
≈ 450 nH
RL
50 Ω
C4
RG
4.7 nF
VI
VGG
V DS
For VGG = VDS = 9 V, RG = 180 k.
For VGG = VDS = 12 V, RG = 250 k.
Fig.26 Cross-modulation test circuit.
1995 Apr 25
11
MGC420
NXP Semiconductors
Product specification
Dual-gate MOS-FET
Table 1
f
(MHz)
BF1100WR
Scattering parameters: VDS = 9 V; VG2-S = 4 V; ID = 10 mA
s11
s21
s12
s22
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
50
0.985
3.9
2.618
175.1
0.001
137.9
1.000
1.9
100
0.981
7.3
2.602
170.5
0.001
80.4
0.999
4.0
200
0.975
14.4
2.577
160.7
0.002
74.0
0.995
7.6
300
0.965
21.6
2.555
151.6
0.002
79.3
0.994
11.3
400
0.947
28.3
2.513
141.8
0.003
80.5
0.992
15.0
500
0.927
34.9
2.449
133.4
0.003
82.8
0.988
18.5
600
0.913
41.7
2.339
124.6
0.003
78.9
0.984
22.0
700
0.890
47.9
2.361
115.4
0.003
80.6
0.982
25.3
800
0.869
54.0
2.302
106.4
0.003
93.9
0.979
28.8
900
0.845
59.7
2.228
97.6
0.003
104.8
0.976
32.1
1000
0.823
65.4
2.167
89.6
0.003
129.3
0.974
35.5
Table 2
Table 3
f
(MHz)
Noise data: VDS = 9 V; VG2-S = 4 V; ID = 10 mA
opt
f
(MHz)
Fmin
(dB)
(ratio)
(deg)
800
2.00
0.67
43.9
rn
0.89
Scattering parameters: VDS = 12 V; VG2-S = 4 V; ID = 10 mA
s11
s21
s12
s22
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
50
0.985
3.7
2.576
175.3
0.000
125.0
1.000
1.6
100
0.980
7.4
2.563
170.9
0.001
111.2
1.000
3.3
200
0.973
14.6
2.541
161.6
0.002
83.0
0.997
6.4
300
0.962
21.5
2.519
152.9
0.002
85.2
0.996
9.3
400
0.946
28.5
2.479
143.5
0.003
79.4
0.995
12.4
500
0.929
35.0
2.419
135.5
0.003
78.2
0.991
15.3
600
0.912
41.6
2.373
127.2
0.003
80.0
0.989
18.1
700
0.895
47.8
2.336
118.7
0.003
83.4
0.987
20.9
800
0.868
53.8
2.284
110.0
0.003
91.3
0.985
23.7
900
0.845
59.8
2.213
101.6
0.003
95.9
0.983
26.5
1000
0.823
65.7
2.160
94.1
0.003
112.2
0.981
29.3
Table 4
Noise data: VDS = 12 V; VG2-S = 4 V; ID = 10 mA
opt
f
(MHz)
Fmin
(dB)
(ratio)
(deg)
800
2.00
0.66
43.3
1995 Apr 25
12
rn
0.97
NXP Semiconductors
Product specification
Dual-gate MOS-FET
BF1100WR
PACKAGE OUTLINE
Plastic surface-mounted package; reverse pinning; 4 leads
D
SOT343R
E
B
A
X
HE
y
v M A
e
3
4
Q
A
A1
c
2
w M B
1
bp
Lp
b1
e1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
b1
c
D
E
e
e1
HE
Lp
Q
v
w
y
mm
1.1
0.8
0.1
0.4
0.3
0.7
0.5
0.25
0.10
2.2
1.8
1.35
1.15
1.3
1.15
2.2
2.0
0.45
0.15
0.23
0.13
0.2
0.2
0.1
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
97-05-21
06-03-16
SOT343R
1995 Apr 25
EUROPEAN
PROJECTION
13
NXP Semiconductors
Product specification
Dual-gate MOS-FET
BF1100WR
DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Qualification
This document contains data from the preliminary specification.
Product data sheet
Production
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
Right to make changes  NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
DEFINITIONS
Product specification  The information and data
provided in a Product data sheet shall define the
specification of the product as agreed between NXP
Semiconductors and its customer, unless NXP
Semiconductors and customer have explicitly agreed
otherwise in writing. In no event however, shall an
agreement be valid in which the NXP Semiconductors
product is deemed to offer functions and qualities beyond
those described in the Product data sheet.
Suitability for use  NXP Semiconductors products are
not designed, authorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
the customer’s own risk.
DISCLAIMERS
Limited warranty and liability  Information in this
document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
Applications  Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks
associated with their applications and products.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
1995 Apr 25
14
NXP Semiconductors
Product specification
Dual-gate MOS-FET
BF1100WR
Export control  This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Quick reference data  The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products  Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified products in automotive equipment or
applications.
Limiting values  Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at
customer’s own risk, and (c) customer fully indemnifies
NXP Semiconductors for any liability, damages or failed
product claims resulting from customer design and use of
the product for automotive applications beyond NXP
Semiconductors’ standard warranty and NXP
Semiconductors’ product specifications.
Terms and conditions of commercial sale  NXP
Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an
individual agreement is concluded only the terms and
conditions of the respective agreement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license  Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
1995 Apr 25
15
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: salesaddresses@nxp.com
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R77/01/pp16
Date of release: 1995 Apr 25