2010 International Conference on Power System Technology
Thyristor Valve for the 12-Pulse Converter for the 3
Gorges - Shanghai II HVDC Transmission Scheme
M.H. Jodeyri IET Member, J.Z. Cao IET Member, C. Zhou & G. Tang
Abstract — This paper presents the design of the thyristor
valve for the 3 Gorges-Shanghai II 3000MW, ±500kV HVDC
scheme. The thyristor valves are based on AREVA’s H400
series valve design using 7.2kV 5” electrically-triggered
thyristor technology and the scheme is the first application of
the valve design for such a voltage level. Details of the valve
configuration, the cooling circuit, as well as the protective
strategy are presented. Detailed electrical ratings such as the
steady-state and temporary overload capabilities, the fault
current capability, the valve losses, as well as the valve
capabilities to cope with the fault scenarios such as the loss of
AC voltage are described. The thyristor valve design satisfies
the requirements of the scheme.
when the De-icer installation is not being used as a De-icer,
it operates as a Static VAr Compensator (SVC), using the
HVDC valves as a Thyristor Controlled Reactor (TCR).
However during the ice storm season, the valves can be reconfigured into two parallel-connected rectifier bridges to
melt the ice on the high voltage transmission lines, by
passing a high DC current through them [3]. Another
application of the H400 technology was the Sino-Russia
back-to-back (BtB) project. This scheme is rated at
750MW DC power with a rated DC voltage of ±125kV and
a rated direct current of 3000A [4]. In these schemes 5”
8.5kV electrically-trigged thyristors were used.
KEYWORDS — HVDC, ±500kV, Transmission, Thyristor,
Converter
I. INTRODUCTION
H
igh Voltage DC transmission (HVDC) technology has
been increasingly used for transferring bulk
electricity over long distances to minimize the conduction
losses of the transmission lines or connecting electricity
networks of different frequencies. Additional advantages
with the HVDC technology include the capability to isolate
two network grids of high power capacities under fault
conditions [1].
978-1-4244-5939-1/10/$26.00©2010 IEEE
Ldc
12 Pulse Converter
R neutral line
510kV AC BUS
The H400 technology is a relative new generation of
electrically triggered thyristor valve developed by AREVA
especially for HVDC applications. The first application of
the technology was the Konti-Skan HVDC pole 1
replacement project between Sweden and Demark [2]. The
H400 technology was then successfully applied to the Deicer project in Québec, Canada [3]. In a normal situation
+500 kV / 3000A Pole
535kV AC BUS
The 3 Gorges-Shanghai II ±500kV HVDC
refurbishment project is one of the HVDC projects
scheduled by the State Grid Corporation of China (SGCC)
to reinforce the electricity grid in the Shanghai region. The
3 Gorges-Shanghai II ±500kV HVDC scheme consists of a
12 pulse bi-pole rectifier-inverter circuit installed at
Jingmen and Fengjing stations respectively. The project
started in 2009 and the commissioning date is scheduled for
2010. The converter valves for the scheme are based on the
AREVA’s H400 thyristor valve technology and use 5”
7.2kV electrically - trigged thyristors. AREVA
is
responsible for the design and supply of the main
components of the thyristor valves as well as the support
for assembly, site installation and commissioning of the
valves.
II. SCHEME PARAMETERS
The converters for the 3 Gorges-Shanghai II ±500kV
HVDC project are to be installed indoor in climatic
controlled valve halls with slightly positive pressure. The
altitudes of the sites are less than 1000m above sea level
and the bulk air temperatures of the valve halls are
controlled between +10°C and +50°C. The external
ambient temperature for the Jingmen station ranges from
-14°C to 40°C and that for the Fengjing station ranges from
-10°C to 38°C. The peak ground acceleration of the sites is
rated at 0.1g in the horizontal direction and the peak
acceleration in the vertical direction is 65% of that in the
horizontal direction.
R electrode
Ldc
Jingmen Rectifier Station -500 kV / 3000A Pole
Fengjing Inverter Station
Fig. 1 The Single Line Diagram for the Proposed Main Circuit
Configuration of the Scheme
As shown by the single line circuit diagram given in Fig.
1, the complete transmission scheme comprises four 12pulse line commutated converters (LCC). The Jingmen
station is normally operated in rectifier mode and the
Fengjing station in inverter mode (henceforth referred as
rectifier and inverter respectively). The middle points of the
rectifier and inverter are firmly earthed. The scheme is
rated at 3000MW power with a rated DC voltage of
±500kV and a rated direct current of 3000A. The
converters at either end of the scheme are connected to the
respective AC networks via twelve single phase two
winding transformers. The normal operation voltage of the
AC system for the Jingmen station ranges from 500kV to
550kV (1p.u. voltage = 535kV) and the AC voltage for the
Fengjing station ranges from 490kV to 525kV (1p.u.
voltage = 510kV). The nominal operating frequency for
both systems is 50Hz. The AC systems maximum short
circuit capacity at Jingmen station is 45466MVA and is
57288MVA at the Fengjing station. The maximum
temporary overvoltage factor for the converter design for
Jingmen station is specified at 1.35 and is 1.15 for the
Fengjing station.
Under normal steady-state operation, the firing angle
for the rectifier ranges between 12° and 18°, with a nominal
value of 15°. The extinction angle for the inverter ranges
from 16° to 18° with a nominal value of 17°.
For reactive power control purpose, the rectifier and
inverter are further required to operate at firing and
extinction angles respectively up to 24°. The maximum
fault current for the converter is specified at 36kA,
occurring when there is a short-circuit fault between valve
terminals.
As far as the voltage stresses are concerned, the valves
at the Jingmen station are more severe than the valves at
Fengjing station. The valve design reported in the
following sections will be based on the valve design for the
Jingmen station. TABLE I summaries the key parameters
of the scheme for the Jingmen converter station.
TABLE I. Main Scheme Parameters for the Jingmen Converter Station
DC Bridge Current
Nominal
Maximum continuous
2 hour overload
3s overload
Pole to Neutral DC Voltage
Nominal
Maximum continuous
Minimum continuous
Transformer Valve Winding Voltage
Nominal
Maximum continuous
Minimum continuous
Maximum Fault Current
3000A
3047A
3389A
4466A
500kV
515kV
489kV
210kVrms
220kVrms
199kVrms
36000A
The Switching Impulse Protection Level (SIPL) for the
valve surge arresters for the Jingmen station is rated at
496.3kV and the coordination current at SIPL is 2kA. The
required Lightning Impulse Protection Level (LIPL) and
fast-front Impulse Protection Level (FWPL) for the valve
surge arresters are 492kV and 559kV respectively.
The required safety margins for the insulation levels for
the thyristor valves are 15% for the switching and lightning
impulse voltages and 20% for the fast-front impulse voltage.
Fig. 2 Schematic Diagram for the Double-Valve MVU Structure at
Jingmen Station
III. H400 THYRISTOR VALVE STRUCTURE
As shown by the double-valve Multivalve Unit (MVU)
structure in Fig. 2, the proposed thyristor valves for the 12pulse converters at Jingmen station are assembled in six
double valves (of two valves each). Individual double
valves are then suspended from the suspension beams of
the valve hall via valve top suspension insulators. The
active components of individual MVU structures are
covered by the top and bottom stress shields as well as the
module corona shields to minimize the local electrical field
stresses due to the high voltage application. Each valve of a
12-pulse converter for the station consists of a total of 87
series connected thyristor levels including three redundant
levels. The thyristor levels of a valve are distributed over
eight modules of two valve sections each. There are six or
five thyristor levels per valve section. Each thyristor level
comprises a single thyristor, a gate electronics unit, and
associated damping and DC grading circuits. The damping
and DC grading components are used for proper internal
distribution of valve voltage from DC to impulse wavefronts as well as the transient voltage at recovery. The gate
electronics unit provides electrical gating of the thyristor
under normal and abnormal operating conditions. It
provides normal triggering in response to control action and
protective triggering in response to overvoltage, high dv/dt
and forward recovery. Six or five thyristor levels of each
valve section share a common di/dt limiting reactor to limit
the rate of change of the thyristor current at turn-ON and
the valve voltage at thyristor turn-OFF. See Fig. 3 for valve
module mechanical structure and Fig. 4 for the simplified
electrical circuit of a valve section consisting of 6 thyristor
levels.
di/dt
Reactor
Damping
Capacitors
Damping
Resistors
di/dt reactors. The coolant is routed to and returned from
the top of each MVU via stainless steel (AISI 316) pipes.
The coolant is then distributed between each valve sections
by larger (75mm) diameter manifold pipes. The heatdissipating elements in each valve section are routed
hydraulically in series as shown in Fig. 6. The three
separate paths of each section are then connected in parallel
to the manifold pipes.
The communications between Valve Base Electronics
(VBE) and each thyristor level are carried out using two
optical fibres, one ‘firing’ fibre which carries the ‘startstop’ pulses and one ‘data-back’ fibre which feeds
information on the status of each thyristor level such as
thyristor healthy or failed back to the VBE.
Gate Electronics
Thyristor
Clamped
Assembly
Fig. 3 A Valve Module Housing 2 Electrical Valve Sections
Fig. 4 Basic Electrical Circuit of a Valve Section of 6 Thyristor Levels
The thyristors within a valve section are held together
between high-efficiency liquid cooled heatsinks as one
'clamped assembly'. Glass Reinforced Plastic (GRP)
tension bands are used to tightly secure the assembly and to
provide the high clamping load necessary for good
electrical and thermal contacts between thyristors and
heatsinks. The clamping system facilitates replacement of a
thyristor without opening any power or coolant connections.
The photograph in Fig. 5 illustrates a six thyristor clamped
assembly for the project.
GRP clamping straps
Thyristor
Heatsink with coolant
connection
Power
connection
Fig. 5 Clamped Assembly for 6 Active Thyristor Levels
A coolant of de-ionized pure water is used to cool the
thyristors, the damping and DC grading resistors, and the
Fig. 6 Series Cooling Arrangement for Elements Inside a Valve Sections
The auxiliary power for the gating electronics unit at
each level is derived locally from the voltage across the
thyristor during the OFF-state intervals. The power supply
contains a storage capacitor with sufficient capacity to
maintain full control of the valve for more than 1 second
with no voltage appearing between valve terminals.
Due to the increased operating voltage of the scheme, a
large number of series connected thyristors and
consequently a large valve size must be used. As the valve
size increases, the voltage distribution between different
levels of the series connected components will be more
severely distorted by the associated stray capacitance. This
is particularly true for the fast-front impulse voltage
because of its higher dv/dt. The stray capacitances for a
valve structure include those between valve modules and
earth, between modules in the same vertical position and
those between modules belonging to the same tier.
Additionally, the stray capacitances between top and
bottom stress shields and earth must be accounted for in
voltage distribution studies. The study for the project
reveals that the influence of the stray capacitance on
voltage distribution is negligible if a 3nF valve section
capacitance is connected in parallel with the combined
thyristor and reactor branch as shown in Fig. 4. This gives
the best compromise between the cost for the valve section
capacitance and the voltage distribution between valve
suspension insulators. The equivalent value of the stray
capacitance Cs for each double-valve is equal to 94pF
which is calculated as follows:
Cs =
Css
Dv × N s × N m
Where:
Css = 3nF, Section stray capacitance
Ns = 2, Number of sections per module
Nm = 8, Number of modules per valve
Dv = 2, Number of valves in a double-valve
Therefore:
Cs =
3 × 10 −9
= 94 pF
2× 2×8
IV. VALVE RATING
The thyristor valves for HVDC application are typically
designed for a lifetime of up to 40 years with minimum
maintenance requirements of every few years. The thyristor
valves need to withstand not only the thermal and voltage
stresses under various continuous and temporary operations,
but also those voltage and thermal stresses as the results of
the switching, lightning, and steep front impulse voltages
caused externally and internally, as well as the stresses
resulting from a fault either due to disturbances originating
from the AC and DC systems or due to a major insulation
failure within the converter. Additionally, the valves are
optimized for minimum losses at specified operating
conditions and to remain operational even when the system
voltage is at its minimum or when it is temporarily lost.
This section discusses the most important aspects of the
valve design, in connection with its reliable operation for
the 3 Gorges-Shanghai II HVDC project.
A. Thermal Rating
The thyristor valves for this project are required to
withstand the worst case thermal and voltage stresses due
to the short-circuit fault in conjunction with the most
unfavourable temporary overvoltage conditions. The
maximum amplitude of the single and three loop fault
currents for the thyristor valves for this project is estimated
at 36kApk, occurring at a minimum firing angle of 5°. The
associated AC system temporary overvoltage factor for
fault current study was assumed at 8%. The initial thyristor
junction temperature prior to the fault is defined by the 2hour overload followed by the 3 second overload. The most
unfavourable cooling condition is defined at the maximum
external ambient temperature in coordination with the
minimum cooling flow and the maximum thyristor losses.
As far as the two operating modes (rectifier and inverter) of
the converter are concerned, the smaller firing angle in
rectifier mode means that the fault current amplitude in
rectifier mode is significantly greater than in inverter mode.
The rectifier mode is therefore used to rate the fault current
capability of the valve design.
To allow for sufficient margins for the thyristor valves
to survive the fault current conditions, the worst-case
thyristor junction temperature due to the combined events
of the 2-hour overload followed by the 3 second overload
scenarios is limited to 90°C. The predicted thyristor
junction temperatures for the proposed valves under
various operating conditions are tabulated in TABLE II.
The worst-case thyristor junction temperature due to the 2
hour overload followed by 3 second overload is 81.3°C,
less than the 90°C limit. Due to the heat capacities of the
thyristors and associated heatsinks, the thyristor junction
temperature does not reach thermal equilibrium at the end
of the 3 second duration.
TABLE II. Thyristor Junction Temperature at Different DC Bridge
Currents
Condition
1) Nominal
2) Max. Continuous
3) 2h Overload
4) 3s Overload
IDC, A
Tj, °C
3000
3047
3389
4466
71.0
71.6
75.5
81.3
Fig. 7 and Fig. 8 illustrate the detailed simulation
waveforms by using PSCAD software for the single and
three loop fault currents. Uthy, Ithy, and Tj in the plots are
respectively the voltage, current, and junction temperature
for the worst-case thyristor assumed. The single loop fault
current is assumed such that the further fault current loops
are prevented by successfully blocking the healthy thyristor
valves of the converter. The most critical requirement for
the valve thyristors in such a scenario is that the reapplied
AC voltages in the forward direction of individual thyristor
levels must be less than the non repetitive forward voltage
withstands capabilities of the thyristors. However, the three
loop fault current occurs only when the healthy valves in
the same converter fail to block the reapplied AC voltages
and the system is tripped by opening the main circuit
breakers. In such a scenario, only the AC voltages
reapplied in the reverse direction of individual thyristor
levels matter. For comparison purpose, the plots also give
the rated thyristor forward/reverse voltage withstand
capacities (Udsm and Ursm), specified as functions of
thyristor junction temperature.
The simulation results indicate that in both events, the
actual voltage experienced by the worst-case thyristor
remains well within the voltage blocking capabilities of the
thyristor. The margins are large and thus no thyristor is at
risk. The highest thyristor temperatures due to both the
single and three loop fault currents are well within the
withstand capabilities of the thyristors. The minimum
duration from current zero to positive-going voltage zero-
40
180
35
160
30
140
25
120
20
100
15
80
10
60
Ithy
40
Tj
0
20
-5
0
0
5
10
15
20
25
30
35
40
Time (ms)
(a)
8
Thyristor Voltage, Uthy & Udsm (kV)
7
6
5
4
2.2
2.0
1.8
1.6
1pu DC current =3000A
Cont. overload without redundant coolers
1.4
Cont. overload with redundant coolers
Temp. overload without redundant coolers
1.2
3
2
Temp. overload with redundant coolers
1.0
1
-15
0
-1
-10
-5
0
5
10
15
20
25
Ambient Air Temperature (deg C)
30
35
40
Fig. 9 Converter Over-Current Capabilities at Different Ambient
Temperatures
-2
-3
Udsm
-4
Uthy
-5
0
5
10
15
(b)
20
Time (ms)
25
30
35
40
Fig. 7 Simulation Waveforms for Single Loop Fault Current Condition (a)
Thyristor Current and Temperature, (b) Thyristor Voltage Blocking
Capability and Reapplied Thyristor Voltage in the Forward Direction
300
35
250
30
25
200
20
15
150
10
100
5
0
50
Ithy
-5
Thyristor Junction Temperature, Tj (°C)
40
Thyristor Current, Ithy (kA)
B. Overload Capability
For reduced external ambient temperatures, the thyristor
valves are allowed to operate at higher DC bridge current
without compromising the thermal limits of the valve
design. As shown by the 2 hour and 3 second over-current
capabilities in Fig. 9, the maximum DC bridge current can
be as high as 1.79p.u. for the 2 hour overload operation and
2.07p.u. for the 3 second overload operation, both derived
by assuming the maximum continuous transformer valve
winding voltage.
DC bridge Current, PU
5
Thyristor Junction Temperature, Tj (°C)
Thyristor Current, Ithy (kA)
crossing is more than the required turn-OFF time for the
thyristor at the relevant junction temperature.
Tj
-10
0.03
0
0.04
0.05
0.06
0.07
Time (ms)
0.08
0.09
0.1
(a)
In order for the thyristor valves to operate in the
optimized range of junction temperature, the coolant
temperature at the inlet of the valve stacks must be
maintained above a minimum limit. For the 3 GorgesShanghai II HVDC project, the minimum coolant
temperature at the valve inlets is limited to 20°C. The
maximum converter overload capabilities therefore do not
change with the decreased external ambient temperature as
soon as the coolant inlet temperature reaches the minimum.
C. Valve Losses
Although the efficiency of a typical thyristor converter
could be as high as 99.5%, the absolute power losses
consumed by the converter are still significant and majority
of the utility operators generally apply a heavy
capitalization factor for the losses.
Thyristor Voltage, Uthy (kV) & Ursm (kV)
4
2
0
-2
-4
-6
-8
Uthy
Ursm
-10
0.03
0.04
0.05
0.06
0.07
Time (ms)
(b)
0.08
0.09
0.1
Fig. 8 Simulation Waveforms for Three Loop Fault Current Condition (a)
Thyristor Current and Temperature, (b) Thyristor Voltage Blocking
Capability and Reapplied Thyristor Voltage in the Reverse Direction
The capitalization factor applied by the utility operators
is typically around $4800 per kW of the power consumed.
Among the total losses of a converter, the majority of them
are dissipated by the high voltage power thyristors due to
the ON-state voltage drop and the stored charge at turnOFF. The other types of losses include those in the
damping and DC grading circuits, the busbar connections
as well as those in the di/dt limiting reactors. The valve
losses were calculated in accordance with the methods
recommended in [5]. The valve loss calculations were
based on the nominal system operation but with different
levels of DC bridge current. The valves were assumed to
have the maximum number of thyristor levels and operate
at the specified minimum coolant flow rate with a
maximum coolant inlet temperature of 43°C. TABLE III
253.7kW × 12 = 3044.5kW
Considering that the total DC transmission power per
12-pulse converter at 1p.u. operation is 1500MW, the
efficiency for the proposed 12-pulse converter is:
pulse converter in rectifier mode was estimated at 378.5kV
while the PCAV in inverter mode is less than in rectifier
mode.
200
100
Valve Voltage, Uv (kV)
reports the evaluated losses dissipated in an individual
thyristor valve of a 12-pulse converter at Jingmen station.
Taking the case for 1p.u. DC bridge current for example,
the total losses in an individual thyristor valve at 1p.u.
current are 253.7kW. The total losses for a 12-pulse
converter at 1p.u. operation are therefore:
0
-100
-200
-300
PCAV
1 – (3044.5kW / 1500000kW) = 99.8%
-400
0
TABLE III. Per Valve Losses at Different DC Bridge Currents
PV1: Thyristor
conduction loss
PV2: Thyristor
spreading loss
PV3: Other conduction
losses
PV4: DC voltagedependent loss
PV5: Low-frequency
damping loss
PV6: High-frequency
damping loss
PV7: Turn-off losses
PV8: Reactor loss
PVT: Total valve losses
No-load dc Loss
No-load Damping Loss
PVSB: Total No-load
Losses
Per valve losses at different DC
bridge current in p.u. (kW)
0.25
0.5
0.75
1.0
8
Time (ms)
12
16
(a)
400
1.1
61.17
100.4
145.2
164.6
1.98
2.89
3.58
3.71
3.71
0.72
2.84
6.29
11.05
13.31
7.85
7.65
7.43
7.20
7.11
3.02
2.98
2.92
2.86
2.84
19.9
26.82
33.47
39.80
42.25
-100
15.2
4.54
80.8
22.68
4.54
131.6
30.63
4.54
189.3
3.408
1.523
39.34
4.54
253.7
43.06
4.54
281.4
-200
4.931
D. PCAV
As with any other switching device, voltage overshoot
exists at thyristor turn-OFF. The voltage overshoot at turnOFF is a phenomenon in association with the leakage
inductance of the converter transformers, the di/dt limiting
reactors and stray capacitance of the converter valves, as
well as the stored charge of the valve thyristors. The scale
of voltage overshoot for the HVDC converter is quantified
using the Peak of the Continuous Applied Voltage (PCAV).
The amplitude of PCAV is generally controlled by adding
the damping circuits to individual thyristor levels. The
reduced level of PCAV will be beneficial to minimize the
number of series connected thyristor levels as well as the
voltage and energy requirements for the associated valve
surge arresters [6], [7].
As shown by the simulation waveforms in Fig. 10, the
worst-case PCAV for the 12-pulse converter in rectifier
mode occurs when the valve winding voltage, the rectifier
firing angle, and the DC bridge current are at their
continuous maxima whereas the valve transformer
impedance is at the minimum. The worst-case PCAV for
the converter in inverter mode occurs when the extinction
angle is at maximum. The maximum PCAV for the 12-
PCAV
300
27.6
Valve Voltage Uv (kV)
IEC Reference
4
200
100
0
-1
1
3
Time (ms)
5
7
(b)
Fig. 10 Valve Voltage Waveforms for Maximum PCAVs in (a) Rectifier
Mode and (b) Inverter Mode
E. Redundancy and Failure Rate
As described in Section III above, the maximum number
of series connected thyristor levels per valve is 87
including 3 redundant levels. The total number of thyristor
levels for a 12 pulse converter is 12 x 87 = 1044.
According to AREVA’s operational data from previous
projects, the annual failure rate for each thyristor level
including the damping circuit, the DC grading resistor and
the gate electronics unit is approximately 0.283%.
Therefore, the predicted number of failed thyristor levels
for a 12 pulse converter for a 12 month operation is:
0.283% × 1044 = 2.96
A reliability study has shown that within any one valve,
there should be no more than 3 redundant thyristor levels
failure during any 12 month period of operation. For the
same operating period, the number of valves with failed
thyristor levels is no more than two.
F. Minimum Continuous and No-Voltage Operations
The H400 gate electronics unit requires a minimum
voltage of approximate 1kVrms per thyristor level for
continuous firing. With an assumed voltage sharing factor
of 1.05, the minimum valve winding voltage for continuous
operation of the converter with a maximum of 87 thyristor
levels per valve is:
1kV × 1.05 × 87 levels = 91.35kVrms
This is less than the minimum continuous valve winding
voltage specified in TABLE I. In addition, the gate
electronics power supply for the H400 valve design
contains a storage capacitor with sufficient capacity to
maintain full control of the valve for more than 1 second
with no voltage appearing between the valve terminals. No
recovery time is required if a fault lasts less than this,
which is more than the 0.7 second duration specified by the
client for either a single phase-to-ground fault or a 30%
under-voltage operation. This is also more than the 0.2
second duration specified for a three phase-to ground fault.
G. Temporary Operation at α=90°
Operating at a high firing angle will result in greater
heat losses in the valve thyristors and relevant damping
resistors, which requires an increased cooling capacity to
bring the element temperatures within limits. It is a
compromise between the requirement for a high firing
angle operation and the cost of the cooling system,
components for the H400 series valve design have been
rated to allow for maximum operation at α equal to 90° for
up to 50 seconds and at 30% of the nominal DC current
(3000A). However, taking account that the type test
duration for maximum temporary operation is generally
twice the permitted duration in operation, the acceptable
duration for temporary operation at α equal to 90° shall be
limited to 25 seconds.
V. CONCLUSIONS
Design of the electrically-triggered thyristor valves for
the 3 Gorges-Shanghai II HVDC project satisfies the
requirements of the scheme. The valve design uses
thyristors of high voltage and high current capabilities that
is a compromise between the scheme’s low cost and high
efficiency requirements. Use of an efficient cooling system
allows the thyristor valves to operate at their maximum
ambient temperature in conjunction with the worst-case
operating conditions. The valve assembly uses a doublevalve structure and will be suspended from the roof of the
valve hall to ensure improved earthquake withstanding
capability. In addition to the valve surge arresters,
individual thyristor levels are safe-guarded by the gate
electronics units. The high storage circuits for the gate
electronics units at individual thyristor levels allow the
valves to operate with no voltage between valve terminals
for more than 1 second, which is longer than the
requirement of the scheme.
ACKNOWLEDGMENT
The authors wish to express gratitude to SGCC and
AREVA T&D for permitting the publication of this paper.
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BIOGRAPHIES
Mohammad Hassan Jodeyri received his M.Phil.
in 1994 from Swansea University, UK. He
received his Ph.D. in Power Electronics in 2007
from the Staffordshire University, UK.
Dr. Jodeyri joined AREVA T&D in 2007 and is
working for PES with HVDC valve design
department. He is a Member of the IET. His
special fields of interest include power electronics,
energy savings for refrigeration and Airconditioning applications, HVDC and FACTS.
Junzheng Cao received his M.Sc. in 1985 from
Xi’an Jiaotong University in China. He received
his Ph.D. in Electrical Eng. in 1997 from the South
Bank University, UK.
Dr. Cao currently works as a principal engineer
and HVDC expert for PES, AREVA T&D. He is a
member of the IEC working group. His special
fields of interest include power electronics,
electromagnetics, HVDC and FACTS.
Changchun Zhou received his PhD in 2004 from
HVDC & FACTS Group of Zhejiang University,
China. He joined AREVA T&D in 2008 and is
working with HVDC Engineering in AREVA
T&D (China).
Dr Zhou previous work was in the area of HVDC
& FACTS system study plus Wide Area control &
stability.
Guangfu Tang received his M.Sc. and PhD in
Electrical Engineering from the Institute of Plasma
Physics, Chinese Academy of Sciences (ASIPP) in
1993 and 1996 respectively.
Dr. Tang currently is a vice-chief engineer of
CEPRI and in charge of the HVDC engineering
research institute of CEPRI. He is a member of
Cigre and power electronics society of China. His
major research field is application of electric
power system of high power electronic technology
including SVC, TCSC, STATCOM and HVDC.