VCU110 ExaMax Backplane
and Interlaken
November 2015
XTP381
Revision History
Date
Version Description
11/24/15
2.0
Updated for 2015.4.
10/22/15
1.1
Updated scripts for 2015.3.
10/06/15
1.0
Initial version.
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VCU110 IBERT Overview
Xilinx VCU110 Board
VCU110 Software Install and Board Setup
Testing IBERT ExaMax and Interlaken
References
Note: This presentation applies to the VCU110
VCU110 IBERT Overview
Description
– This tutorial tests the ExaMax and Interlaken interfaces on the VCU110
– Requires two VCU110 boards
– The LogiCORE Integrated Bit Error Ratio (IBERT) core is used to create a
pattern generation and verification design to exercise the UltraScale Virtex
GTY transceivers. A graphical user interface is provided through the Vivado
Hardware Manager.
Reference Design IP
– LogiCORE UltraScale IBERT GTY Example Designs
– See XTP374 – VCU110 GT IBERT Design Creation for details on compiling
this design
Note: Presentation applies to the VCU110
Xilinx VCU110 Board
VCU110 Software Install and Board Setup
Complete setup steps in XTP380 – VCU110 Software Install and
Board Setup:
– Software Requirements
– VCU110 Board Setup
– UART Driver Install
– Clock setup
– ExaMax/Interlaken Hardware
Setup
Note: Presentation applies to the VCU110
VCU110 Setup
Open the RDF0343 - VCU110 ExaMax and Interlaken Design Files
(2015.4 ES2) ZIP file, and extract the files to your C:\ drive
Note: Presentation applies to the VCU110
Testing IBERT GTY ExaMax Interlaken
Testing IBERT GTY ExaMax Interlaken
From a Command Prompt type:
cd C:\vcu110_backplane
vcu110_ibert_bank_examax_interlaken.bat
Note: Presentation applies to the VCU110
Testing IBERT GTY ExaMax Interlaken
Two Tera Term windows will open, connected to the two Enhanced
UART ports of the two VCU110 boards
Note: Presentation applies to the VCU110
Testing IBERT GTY ExaMax Interlaken
Push SW14 on both boards to show the UART
menu
Note: Presentation applies to the VCU110
Testing IBERT GTY ExaMax Interlaken
Press “1”, Enter, “3”, Enter, then type “175”; press “Enter”
– This sets the ExaMax and Interlaken clocks
Do this for both UART windows
Note: The Si5328 must be set whenever power is cycled
Testing IBERT GTY ExaMax Interlaken
In the Command Prompt, press any key to continue
This will open two Vivado GUIs, program the FPGAs and setup the
serial links
Note: Presentation applies to the VCU110
Testing IBERT GTY ExaMax Interlaken
If needed, set both Vivado GUIs’ layout to Serial I/O Analyzer
Note: Presentation applies to the VCU110
Testing IBERT GTY ExaMax Interlaken
ExaMax (links 0-7) and Interlaken (links 8-27) line rate is 28 Gbps
Using FCI Backplane, Test Board 0 has all links working without errors
Testing IBERT GTY ExaMax Interlaken
Using FCI Backplane, Test Board 1 shows all links working without
errors
Testing IBERT GTY ExaMax Interlaken
Using Samtec Backplane, Test Board 0 has all links working without
errors
Testing IBERT GTY ExaMax Interlaken
Using Samtec Backplane, Test Board 1 shows all links working
without errors
References
References
IBERT IP
– LogiCORE IP Integrated Bit Error Ratio Tester for UltraScale GTY – PG196
• http://www.xilinx.com/support/documentation/ip_documentation/ibert_ultrascale_gty/
v1_2/pg196-ibert-ultrascale-gty.pdf
Vivado Programming and Debugging
– Vivado Design Suite Programming and Debugging User Guide – UG908
• http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/
ug908-vivado-programming-debugging.pdf
Documentation
Documentation
Virtex UltraScale
– Virtex UltraScale FPGA Family
• http://www.xilinx.com/products/silicon-devices/fpga/virtex-ultrascale.html
VCU110 Documentation
– Virtex UltraScale FPGA VCU110 Evaluation Kit
• http://www.xilinx.com/products/boards-and-kits/dk-u1-vcu110-es-g.html
– VCU110 – Known Issues Master Answer Record
• http://www.xilinx.com/support/answers/62604.html