Application Report
SLVA233A – April 2006 – Revised August 2006
Electrical Transient Immunity for Power-Over-Ethernet
Jean Picard ................................................................................................................ Systems Power
ABSTRACT
Electrical overstresses can cause failure, permanent degradation, or temporary erratic
behavior of electronic devices or systems. The trend to reduce circuit geometries for
communication systems and applications results in an increasing sensitivity to such
electrical transients. The suppression of these transients can be a challenge to
designers because the origin and severity of the overvoltage may be unknown.
To assist designers in coping with these issues, this application report defines simple
design rules that can adequately protect the sensitive electronic parts of the system
with cost-effective solutions.
1
2
3
4
5
6
7
Contents
Introduction .......................................................................................... 2
ESD................................................................................................... 3
EFT ................................................................................................... 4
Electrical Surge ..................................................................................... 7
Transients Protection Circuit Guidelines......................................................... 8
Circuit Protection Solutions for PoE .............................................................. 9
References ......................................................................................... 19
List of Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Typical PoE Application Diagram ................................................................. 2
Typical Waveform of Output Current of ESD Generator ...................................... 4
Voltage of EFT Into 50-Ω Load ................................................................... 5
General Graph of EFT (Fast Transient/Burst) .................................................. 6
EFT Test Setup ..................................................................................... 6
Typical Waveform of Open-Circuit Voltage of Surge Generator When Set to 1-kV Peak 7
Typical Waveform of Short-Circuit Current of Surge Generator When Set to 1-kV
Peak with 2-Ω Source Impedance................................................................ 7
Interconnection of Transient Voltage Suppressor on Printed-Circuit Board ................ 9
Effect of ESD/EFT on PSE Power Switch When There is no Protection Circuitry ....... 10
Basic Circuit With Transient Protection ........................................................ 11
Current Path in Positive Polarity ESD/EFT Event Common Mode: Line-to-GND ........ 14
Current Path in Negative Polarity ESD/EFT Event Common Mode: Line-to-GND ....... 14
Current Path in Positive Polarity Surge Event Common Mode: Line-to-GND............. 15
Current Path in Negative Polarity Surge Event Common Mode: Line-to-GND ........... 15
Negative EFT Simulation on N Terminal With 56V Power Supply ON..................... 15
Negative EFT Simulation on N Terminal With 56V Power Supply OFF ................... 16
Negative EFT Simulation on N Terminal With 56V Power Supply OFF and With 3V
Initially on C2 ...................................................................................... 16
Negative Surge Simulation on N Terminal With 56 V Power Supply ON .................. 17
Layout for a Dual Port PSE ...................................................................... 18
Interconnection to Clamping Devices .......................................................... 18
Layout for a Quad Port PSE ..................................................................... 19
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Introduction
List of Tables
IEC61000-4-2 Test Levels .........................................................................
IEC61000-4-2 Waveform Parameters ...........................................................
IEC61000-4-4 Severity Test Levels .............................................................
IEC 61000-4-5 Severity Levels ...................................................................
1
2
3
4
1
3
3
5
8
Introduction
Electrical overstresses can cause failure, permanent degradation, or temporary erratic behavior of
electronic devices or systems. The trend to reduce circuit geometries for communication systems and
applications results in an increasing sensitivity to such electrical transients. The suppression of these
transients can be a challenge to designers because the origin and severity of the overvoltage may be
unknown.
When designing an electronic circuit or when defining a complete system, it is important to identify the
sources of those stresses and have a correct understanding of their mechanism, for a defined
environment in which the system will operate. In so doing, it is possible to define simple design rules that
can adequately protect the sensitive electronic parts of the system with cost-effective solutions
This application report discusses the Ethernet network application, specifically Power-over-Ethernet (PoE)
equipment which provides power to Ethernet remote equipment or powered device (PD) through the data
cable (see Figure 1).
RJ 45
Up to 100 m
of CAT 5
RJ 45
4
4
5
5
PSE
PD
Spare Pair
+ 48 V
1
1
2
2
Rx
Tx
P
TPS2384
Optional
MSP430
Micro
Controller
VDD
TPS2375
Signal Pair
DET
(1/4)
SCL
SDA-I
SDA-O
Ret
PG
ILIM
CLASS
3
N
3
Rx
VEE
Tx
6
DC/DC
Converter
6
Signal Pair
+ 48 V
Return
7
7
8
8
Spare Pair
Figure 1. Typical PoE Application Diagram
In a PoE application, the environment can range from offices to industrial networks. Installations of
Ethernet cables and/or equipment are located mostly indoors, but in some applications part of the
installation can be outdoors.
Many standards have been developed to simulate or represent the transient overvoltage environment in
various applications, including telecom and industrial. For example, per IEC transient immunity standards,
the transients can be classified into three categories:
• IEC 61000-4-2: Electrostatic Discharge (ESD)
• IEC 61000-4-4: Electrical Fast Transient/Burst (EFT)
• IEC 61000-4-5: Surges
These IEC standards also define immunity test methods applicable to each transient category. They
provide to manufacturers of transient suppression components some standardized waveforms and
overvoltage levels to which their components can be characterized and specified.
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ESD
2
ESD
ESD (electrostatic discharge) results from conditions which allow the build up of electrical charge from
contact and separation of two nonconductive materials, followed by the release of the corresponding
energy when the charged body is brought into proximity to another object of lower potential. For example,
a person walking across a carpet can charge to over 15 kV.
ESD is first of all a common-mode electrical event; normally, ESD is a discharge from one unit to the
chassis ground. One important design guideline is to clearly identify the path that is taken by the current
and to ensure that this is not harmful to sensitive circuitry. It is even better to provide an alternate path for
the discharge current to bypass this sensitive circuitry.
The IEC 61000-4-2 standard simulates an ESD event of a human holding a metal implement, referred to
as the Human/Metal Model. Discharge into equipment can be through direct contact (contact discharge) or
through proximity (air discharge).
The test levels of this model are listed in Table 1. A diagram showing the ESD waveform is presented in
Figure 2.The waveform parameters of the ESD generator in contact mode are summarized in Table 2. The
rise time can be expected to be less than 1 ns, which is extremely fast. The total duration of the current
pulse is around 150 ns.
Table 1. IEC61000-4-2 Test Levels
CONTACT DISCHARGE
AIR DISCHARGE
LEVEL
TEST VOLTAGE
(kV)
LEVEL
TEST VOLTAGE
(kV)
1
2
1
2
2
4
2
4
3
6
3
8
4
8
4
15
Table 2. IEC61000-4-2 Waveform Parameters
LEVEL
INDICATED
VOLTAGE
(kV)
FIRST PEAK CURRENT
OF DISCHARGE
(A)
RISE TIME tr WITH
DISCHARGE SWITCH
(ns)
CURRENT AT
30 ns
(A)
CURRENT AT
60 ns
(A)
1
2
7.5
0.7 to 1
4
2
2
4
15
0.7 to 1
8
4
3
6
22.5
0.7 to 1
12
6
4
8
30
0.7 to 1
16
8
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EFT
I
100%
90%
I at 30 nsec
I at 60 nsec
10%
t
30 nsec
0.7 to
1 nsec
60 nsec
Figure 2. Typical Waveform of Output Current of ESD Generator
Another threat is identified as a cable discharge event (CDE). For example, this occurs when an Ethernet
cable becomes charged and then is discharged into a circuit when the cable is connected to it. The cable
could be charged primarily due to tribocharging (e.g., by dragging it on the carpet) or induction (e.g., from
a charged person holding it).
A standard to define a cable discharge event with test method has yet to be established, but most
manufacturers use internal CDE test setups to evaluate their designs; a few deem it sufficient to test to the
IEC Level-4 specifications to protect against such discharges.
Note:
3
The idea of the equipment being able to withstand CDE if it passes IEC 61000-4-2
Level-4 discharges is not always correct. This is because the charged capacitances in the
two tests are different, which is 150 pF for IEC ESD versus much larger capacitance
depending on the length of the cable involved for CDE and the cable elevation over the
earth GND. There is also a transmission line effect with some distributed capacitance as
opposed to a lumped capacitance. CDE discharges typically dump more energy than IEC
Level-4 discharges into the equipment under test.
EFT
EFT (electrical fast transient) occurs as a result of arcing contacts in switches and relays, with motors and
other inductive loads, which is common in industrial environments. This type of transient is normally of
common-mode type and is introduced on telecommunication cables by capacitive coupling.
IEC 61000-4-4 defines this transient as a burst of fast and high-voltage spikes at a repetition rate of 5 kHz
or 100 kHz. A diagram showing the EFT waveform, the EFT burst repetition rate, and burst period is
presented in Figure 3 and Figure 4. Also, the voltage and current characteristics of the EFT burst
generator are summarized in Table 3. Short-circuit current values are estimated by dividing the
open-circuit voltage by the 50-Ω source impedance.
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EFT
Table 3. IEC61000-4-4 Severity Test Levels
Open-Circuit Output Test Voltage, Short-Circuit Current, and Repetition Rate of the Impulses
LEVEL
POWER-SUPPLY PORT
I/O SIGNAL, DATA, AND CONTROL PORTS
OPEN-CIRCUIT
VOLTAGE PEAK
(kV)
SHORT-CIRCUIT
CURRENT PEAK
(A)
OPEN-CIRCUIT
VOLTAGE PEAK
(kV)
SHORT-CIRCUIT
CURRENT PEAK
(A)
REPETITION RATE
(kHz)
1
0.5
10
2
1
20
0.25
5
5 or 100
0.5
10
3
2
5 or 100
40
1
20
5 or 100
4
4
80
2
40
5 or 100
It is worth noting that even though it is a power signal that is transmitted on the PoE cable, this
transmission is still on a communication data cable, which means that it is considered as such when
installed and used. Consequently, it belongs to the I/O signal, data, and control ports category.
The following equation gives a good approximation of the EFT voltage waveform:
V EFT(t) + A
with:
A + 1.270
Vp
ǒ
ǒ ǓǓ
1 * exp *t
t1
t 1 + 3.5 ns
ǒ Ǔ
exp *t
t2
t2 + 55.6 ns
(1)
EFT Waveform
1100
1000
V( t90%)
900
volt
800
700
Volt
600
500
50 nsec Duration
400
300
200
V( t10%)
5 nsec Rise Time
100
volt
0
0
10
20
30
40
50
60
70
80
90
100
t - Time - nsec
Figure 3. Voltage of EFT Into 50-Ω Load
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EFT
V
Pulse
t
Burst
V
15 msec
Burst
Duration
0.75 msec if
at 100 kHz
t
Burst Period 300 msec
Figure 4. General Graph of EFT (Fast Transient/Burst)
Per IEC61000-4-4, a capacitive coupling clamp over the communication cable is the preferred method for
coupling the test voltage in communication ports, and this includes an Ethernet cable. This means that the
coupling is done without any galvanic connection to the port.
POE
Cable
EUT
EFT
Generator
GND Reference
Plane
Figure 5. EFT Test Setup
Another acceptable means is directly through a 100-pF discrete capacitor.
It is worth noting that because of their repetitive nature, EFT events can also result in erratic behavior of a
communication system.
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Electrical Surge
4
Electrical Surge
These transients are the most severe of all, in terms of peak current and duration, although they are the
least severe in terms of rate of rise. They are caused by lightning strikes (direct strike or induced voltages
and currents due to an indirect strike) and switching on power systems (also includes load changes and
short circuit). The degree of severity of the transient can change depending on if the cable installation is
inside or outside the building.
This type of transient is either of common-mode type or differential-mode type. It is introduced on
telecommunication cables by capacitive or magnetic coupling. Remember that in PoE applications, the DC
power is transmitted by using both wires of each transmit and receive pair which means, for example, that
the positive P-side of DC voltage could be on the TX pair while the return N-side would be on the RX pair.
On a twisted-pairs cable, the two wires of each pair are twisted together, but there is no twisting between
pairs at all (in fact, each pair is well separated from its neighbors). Consequently, a differential-mode
transient between P and N is likely with that type of cable, and this tandem of pairs can be considered as
an unbalanced line as far as the test voltages are concerned.
IEC 61000-4-5 defines this transient as two surge waveforms: the 1.2 × 50-µs open-circuit voltage
waveform and the 8 × 20-µs short-circuit current waveform. See Figure 6, Figure 7, and Table 4.
The following equation gives a good approximation of the surge short-circuit current waveform:
I surge(t) + Ai I p t 3 exp *t
t
ǒ Ǔ
with:
t + 3.911
Ai + 0.01243
ms 3
ms
(2)
SURGE VOLTAGE WAVEFORM
1100
1000
T1 = 1.207 ms,
V t90%
1.666T = 1.202 ms,
T2 = 49.972 ms
900
800
volt
700
600
500
400
V t30%
300
T2
volt
200
100
0
0
10
20
30
40
50
60
70
80
T
t - Time - ms
T1
Figure 6. Typical Waveform of Open-Circuit Voltage of Surge Generator When Set to 1-kV Peak
SURGE CURRENT WAVEFORM
600
550
T1 = 8.039 msec,
1.25T = 8.028 msec,
T2 = 19.934 msec
500
Amps
450
400
I t 90%
amp
350
300
250
200
150
T2
100
50
0
0
I t10%
amp
5
T
T1
10
15
20
25
30
35
40
45
50
t -Time - msec
Figure 7. Typical Waveform of Short-Circuit Current of Surge Generator When Set to 1-kV Peak with 2-Ω
Source Impedance
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Transients Protection Circuit Guidelines
Table 4. IEC 61000-4-5 Severity Levels
TEST LEVELS
INSTALL
CLASS
POWER-SUPPLY
UNBALANCED
OPERATED
CIRCUITS/LINES, LONG
DISTANCE BUS
COUPLING MODE
1
Voltage
Line to Line
Zs = 42
Ω
Line to
GND
Zs = 42
Ω
Line to
Line
Zs = 42
Ω
Line to
GND
Zs = 42
Ω
Line to
Line
Zs = 42
Ω
Line to
GND
Zs = 42
Ω
N/A
0.5 kV
N/A
0.5 kV
N/A
0.5 kV
N/A
N/A
N/A
0.5 kV
42 A
12 A
0.5 kV
1.0 kV
0.5 kV
1.0 kV
Current
250 A
83 A
12 A
24 A
3
Voltage
1.0 kV
2.0 kV
1.0 kV
2.0 kV
Current
500 A
167 A
24 A
48 A
4
Voltage
2.0 kV
4.0 kV
2.0 kV
4.0 kV
Current
1 kA
333 A
48 A
95 A
2.0 kV
4.0 kV
48 A
95 A
Voltage
Current
COUPLING MODE
L8ine to
GND
Zs = 12
Ω
Voltage
5
SHORT DISTANCE
DATA BUS
(Less Than 30 m)
Line to Line
Zs = 2
Ω
Current
2
COUPLING MODE
BALANCED
OPERATED
CIRCUITS/LINES
Depends on class of local
power supply system
12 A
N/A
1.0 kV
24 A
N/A
2.0 kV
N/A
2.0 kV
12 A
N/A
N/A
N/A
N/A
N/A
N/A
48 A
48 A
N/A
4.0 kV
95 A
IEC 61000-4-5 classes 3 to 5 are applicable to outdoor applications and higher threat-level conditions. In
the majority of PoE applications, only indoor cable installation (office environment) is considered. Also, the
IEEE 802.3 requires the networks to withstand a 1500-V dielectric test to earth. As a result, only Class 2
(semi-protected environments) is applicable.
Also, for an Ethernet cable used for PoE, the categories applicable are the unbalanced and balanced
circuits/lines. Note that for a balanced line, there is no explicit line-to-line test, but this is implicitly done
with a line-to-GND test setup using coupling through arrestors instead of capacitors; this setup is such that
it does not influence the specified functional condition of the circuit to be tested.
Other possible standards are the ITU-T recommendations K.20, K.21, K.44, and K.45, and in some cases
the GR-1089-CORE (intra-building lightning surge specification).
Another typical telecommunication standard is the 10/700-µs voltage waveform. This standard is not
applicable for Ethernet networks because it only applies in situations of long-distance telecommunication
signal lines, with both indoor and outdoor installation.
5
Transients Protection Circuit Guidelines
Many guidelines apply to voltage transients protection for electronic systems. The following is a list of
some practical rules along with circuits design strategies.
• The source of transient voltage can be of differential- or common-mode type or both.
• The main categories of protection techniques against transient voltages are shielding and grounding,
filtering, isolation, and nonlinear devices.
• A well-designed circuit protection interface is normally the result of a good combination of blocking and
diverting techniques.
• The selected voltage suppressor must have the speed/robustness (short-circuit current and waveform)
required for the application. Shunt (line-to-earth GND) capacitors that may take direct transient hits
should be rated for high voltage (≥ 2 kV). These capacitors must also have the following
characteristics: low ESR at high frequency and low parasitic inductance.
• The protection circuit should not interfere with the normal behavior of the circuitry to be protected.
• The protection circuit should be able to prevent any voltage transient from causing an erratic (repetitive
or not) behavior of the complete system. EFT is an example. Use common-mode chokes when
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Circuit Protection Solutions for PoE
•
necessary.
The basic rules of circuit layout design are:
– Define a low-impedance path that diverts any transient current/voltage away from sensitive
components. Do not let ESD find its way to earth GND by itself.
– Have a good, solid, and low-impedance earth ground connection onboard.
– Keep the transient current density and the current path impedances as low as possible by using
multipoint grounds where the current is designed to flow, and single-point grounds where it is not.
– The loop within which the fast-rising currents have to circulate must be a small area. For fast
transients, use local ceramic capacitors whenever necessary, particularly when clamping diodes to
a power-supply rail are used. See Figure 20.
– Create physical separation between high-voltage/current transients area, in close proximity to I/O
connectors, and the sensitive circuitry. The high-current suppressors must be located in that I/O
area, as well as the switches, LEDs, and displays
– Put all the connectors on one edge of the circuit, if possible. Place sensitive circuitry at the center
of the printed-circuit board, if possible.
– Route each protected signal from the suppressor to the sensitive circuitry in parallel with its
individual return signal in order to prevent any inadvertent transformer effect.
– Use surface-mount package for suppressors. Use 4-terminal connection type in order to mitigate
parasitic inductance effect. See Figure 8 and Figure 20.
– Mitigate parasitic capacitances bypassing blocking series elements. However, having parasitic
inductance in series with blocking elements is not a problem.
From
Transient
Source
Suppressor
Device to be
Protected
From
Transient
Source
Device to be
protected
Suppressor
GOOD
BAD
Figure 8. Interconnection of Transient Voltage Suppressor on Printed-Circuit Board
6
Circuit Protection Solutions for PoE
Only secondary protection, usually deployed within the equipment to be protected, is discussed in this
document. However, it is worth noting that where telecommunication cable is run outside, primary
telecommunication protectors (PTC thermistors, SIDACtors, etc.) must be deployed at points where
exposed twisted pairs enter a building or residence.
In a PoE application, the PSE (power source equipment) is powered from a 48-V power supply, which
normally has some common-mode capacitances connected to earth ground; those capacitances can be
either discrete capacitors and/or capacitance between layers in the printed-circuit board.
Therefore, because the PSE is not really floating, any common-mode voltage transient applied on the data
connector can result in a voltage breakdown of PSE components, and particularly the PSE port power
switch.
Figure 9 presents an example of the effect of such a transient, along with the high-current path which
results in the destruction of the PSE power switch when no appropriate protection is implemented. C_CM
represents the capacitance between the 48-V lines and chassis GND. Such capacitance can be either on
the + or – line of the 48 V, but in order to simplify the illustration, C_CM is shown only on the – line. The
configuration shown is applicable when the AC disconnect circuitry is used, which requires the use of D1.
This is the worst case for transient protection.
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Circuit Protection Solutions for PoE
D1
Schottky
STPS1H100A
+48 V
220 nF
48 V
SW
D5
SMJ58
To RJ45
C1
0.1 mF
220 mF
P
N
+48 V
Voltage
Breakdown
C _ CM
V48
Common Mode
(Parasitics and
Capacitors in 48 V
Power Supply)
Ret
Figure 9. Effect of ESD/EFT on PSE Power Switch When There is no Protection Circuitry
In
•
•
•
•
general, the categories of protection techniques against transient voltages are:
Shielding and grounding
Filters: capacitors, inductors, ferrite beads, chokes, etc.
Nonlinear devices, including clamping diodes, TVSs, varistors, etc.
Isolation
In an actual application, where RJ-45 cables are used, cable shielding is usually not an available solution.
The following solution is proposed in order to adequately protect the PSE integrated circuit. See Figure 10.
This configuration is applicable when the AC disconnect circuitry is used. If this is not the case, then D1
and D3 are not used.
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Circuit Protection Solutions for PoE
Ethernet TX
OUT
Ethernet TX
IN
To RJ 45
Ethernet RX
OUT
Ethernet RX
IN
D3
TVS 8V
½ PSOT08C (Protek)
+48V
48V
SW
IN
D5
SMJ58
D1 Schottky
STPS1H100A
or MBRS1100 T3
FB1
220nF/
100V
C2
C1
0.1uF
D2
¼ SR70
or ES2BA
or STTH102
220uF/
100V
Ferrite beads
Fair-Rite
See Note below
2512066017Y1
FB2
10nF/
200V
10nF/
200V
P
75
ohms
N
+48V
D4
¼ SR70 (Protek &
Semtech)
or
STPS1H100A
or
STTH102
V48
Ret
Bob Smith
terminations
ESD
capacitor
75
ohms
1nF/
2kV
C4520X7R3D102K
Note:
The proposed fuse configuration is just an example of implementation.
Some systems configurations and safety requirements might also require
the fuse to be installed in series with N terminal instead of P.
Figure 10. Basic Circuit With Transient Protection
The major elements of this protection circuit are:
• Clamping diodes D2 and D4: key parameters are the forward recovery time and capability to handle
transient currents for a specific duration, as mentioned in the previous ESD, EFT, and surges sections.
The resultant forward voltage transient must be acceptable. Within the selected diodes, the SR70 has
the additional advantage of a small package.
• TVS D3: key parameters are response time and current-handling capability along with low impedance.
D3 is required only if D1 is used (for AC disconnect function).
• Note: If the application requires the consideration of more severe surges like the ones defined in the
GR-1089-CORE (intra-building lightning surge specification) standard, it is recommended to use the
STPS1H100A or STTH102 for D2 and D4 and a 1500-W TVS (SMCG8.0, for example) for D3, which
are more robust.
• Schottky diode D1: using a Schottky provides a fast protection against negative voltage transients, in
addition to improving efficiency of the PSE.
• Bob Smith terminations or line-to-GND capacitors: the initial ESD/EFT transient hits circulate through
those terminations to earth ground.
• Ferrite beads: these provide blocking impedance.
– The main function of the ferrite beads is to provide isolation at high frequency between the Bob
Smith terminations and the internal capacitor placed between P and N. Without these beads, the
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Circuit Protection Solutions for PoE
•
•
•
•
terminations might not work correctly.
– The ferrite beads also play an important role against ESD.
Fuse:
– Note that the fuse must be selected so it will withstand, without opening, the energy associated to
the normal transients. The worst case happens during a surge event applied in differential from N to
P. In this case, the I2t can reach 10 × 10-3 A2 sec within 35 µs. A good design rule is to select a
fuse with ensured capacity of at least 2 times that I2t.
– Also, some systems configurations and/or safety requirements might also require the fuse to be
installed in series with the N-terminal instead of the P-terminal.
Decoupling capacitor (100 nF) on 48-V bus and on PN: these must be low-impedance ceramic types. It
is important to locate C1 close to the clamping diodes and preferably use one such capacitor per group
of two (or perhaps four) ports. Also important is the location of C2 in close proximity to the same
circuitry.
TVS on input 48-V bus: this TVS is normally located close to the 48-V input connector, as well as the
220- µF.
All the components selected feature a surface-mount package for low parasitic inductance.
As can be seen, the protection components keep any transient current from flowing through the N-to-RTN
or the P-to-RTN of the IC, in either positive or negative polarity.
However, those transient currents may follow different paths depending on the source of the transient.
This is illustrated from Figure 11 to Figure 14.
The case of ESD or EFT, which are fast and common-mode events, is illustrated in Figure 11 and
Figure 12. The case of surges, which are much slower, is illustrated in Figure 13 and Figure 14; both
common and differential (between P and N pairs) mode surges are handled by the circuitry although only
the first (common-mode) type is illustrated.
One interesting point is that the DC voltage levels on C1 and C2 just prior to the transient event directly
effect the paths that those transient currents follow.
For example, with a negative EFT event on N while the PSE power switch is OFF, consider the following
scenarios:
• In all scenarios, at the beginning of every EFT pulse, the current circulates for a short time in the Bob
Smith termination.
• If the 56-V power supply is ON just prior to the event: the transient current only circulates through the
path of D1, C1, and C2, and does not circulate at all through the clamping diode D4.
• If the 56-V power supply is OFF but still connected and if C2 is not charged: during the first EFT pulses
of that event, the current circulates through D1, C1, and C2. The capacitor C2 accumulates some
charge, and its voltage increases from one EFT pulse to the next one.
• If the 56-V power supply is OFF but still connected and if C2 is charged to a certain level: the current
follows two paths depending on the voltage accumulated in C2, and from one EFT pulse to the next
one, the C2 path takes a higher proportion of that current.
• This is illustrated at the left in Figure 12. Simulation results are also shown in Figure 15 to Figure 17.
Simulation results in Figure 18 also show a similar behavior but with a surge, which is much slower than
EFT.
On ESD or EFT simulations, it is clear that the BS termination, along with the ferrite beads, play an
important role in ESD/EFT suppression. BS terminations are first of all used for EMC reasons. The
pair-to-pair relationship of a Cat-5 cable form transmission lines in themselves, which need BS
terminations in order to avoid multiple reflections and standing wave problems. Secondly, those
terminations clearly define the first path that an ESD or EFT strike will follow. Note that substituting BS
terminations with capacitors to chassis ground without any series matching (or damping) resistor results in
a low pair-to-pair matching impedance which might result in even stronger EMC problems.
12
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It is interesting to note that for the mentioned threat levels and based on simulation results, the maximum
possible voltage on a line-to-earth GND capacitor is approximately 1 kV; so, a 2-kV-rated capacitor is a
safe choice. Simulations indicate that with 8-kV ESD applied and with a150pF/330-Ω human/metal model,
the resultant voltage on the 1 nF of the Bob Smith termination is less than 100 V. The worst-case high
voltage on this capacitor occurs during the surge test which is at 1 kV for Class-2. Similarly, a 200-V rating
for the 10 nF is a safe choice.
Tests have been performed with the clamp diodes plus Bob Smith termination and ferrite beads. The
results have been satisfactory and demonstrate that the TPS2384 and its circuitry can tolerate some
forward voltage drop on D2 and D4 while supporting high transient currents. Examples of suggested board
layouts are shown in Figure 19 and Figure 21.
Note that the optional common mode choke can be used in situations where EFT events cause erratic
behavior of the system. In order for this choke to be effective, all signals have to pass through it, which
means the Ps, Ns, the 48 V and the GND connection.
Clearly, the following components and the connectors (power input and RJ-45) must be close together in
order to keep the area of the transient current loop (and its impedance) as small as possible: D2, D4, D3,
D1, C1, and C2.
For example, the effectiveness of the clamping diode D2 is greatly reduced if C1 is not located nearby in
ESD or EFT application.
In applications with multiple ports, it is recommended to have one such C1 per group of ports (preferably
two or four) and to place it physically close to its group of components.
It is also important to provide sufficient copper area for the suppressor device in order to facilitate
heatsinking.
Note that Ethernet interface circuitry usually also requires data line protectors for the data line driver
circuitry. However, this discussion has mainly focused on protection techniques applicable to
Power-Over-Ethernet circuitry.
SLVA233A – April 2006 – Revised August 2006
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Circuit Protection Solutions for PoE
ESD/EFT on P
ESD/EFT on N
D3
TVS 8V
½ PSOT08C (Protek)
+48V
48V
SW
D5
SMJ58
D3
TVS 8V
½ PSOT08C (Protek)
D1 Schottky
STPS1H100A
or MBRS1100 T3
220nF/
100V
C1
0.1uF
+48V
FB1
D2
¼ SR70
or ES2BA
or STTH102
220uF/100V
FB1
220nF/
100V
Fair-Rite
2512066017Y1
48V
SW
FB2
D5
SMJ58
C1
0.1uF
D2
¼ SR70
or ES2BA
or STTH102
220uF/100V
TTDLF2500
N
1nF/
2kV
D4
¼ SR70 (Protek &
Semtech)
or
STPS1H100A (ST)
or
STTH102 (ST)
V48
Fair-Rite
2512066017Y1
FB2
10nF
10nF
75
ohms
+48V
Ferrite beads
10nF
10nF
P
D1 Schottky
STPS1H100A
or MBRS1100T3
Ferrite beads
75
ohms
ESD
capacitors
P
75
ohms
N
1nF/
2kV
+48V
1nF/
2kV
D4
¼ SR70 (Protek &
Semtech)
or
STPS1H100A (ST)
or
STTH102 (ST)
C4520X7R3D102K
V48
Ret
75
ohms
ESD
capacitors
1nF/
2kV
C4520X7R3D102K
Ret
Figure 11. Current Path in Positive Polarity ESD/EFT Event Common Mode: Line-to-GND
ESD/EFT on P
ESD/EFT on N
D3
TVS 8V
½ PSOT08C (Protek)
D3
TVS 8V
½ PSOT08C (Protek)
+48V
48V
SW
D5
SMJ58
D1 Schottky
STPS1H100A
or MBRS1100 T3
220nF/
100V
C1
0.1uF
+48V
FB1
D2
¼ SR70
or ES2BA
or STTH102
220uF/100V
D1 Schottky
STPS1H100A
or MBRS1100T3
FB1
Ferrite beads
220nF/
100V
Fair-Rite
2512066017Y1
48V
SW
FB2
D5
SMJ58
C1
0.1uF
D2
¼ SR70
or ES2BA
or STTH102
220uF/100V
10nF
10nF
Ferrite beads
Fair-Rite
2512066017Y1
FB2
10nF
10nF
P
75
ohms
N
P
1nF/
2kV
+48V
D4
¼ SR70 (Protek &
Semtech)
or
STPS1H100A (ST)
or
STTH102 (ST)
V48
75
ohms
ESD
capacitors
1nF/
2kV
75
ohms
N
1nF/
2kV
+48V
D4
¼ SR70 (Protek &
Semtech)
or
STPS1H100A (ST)
or
STTH102 (ST)
C4520X7R3D102K
V48
75
ohms
ESD
capacitors
1nF/
2kV
C4520X7R3D102K
Ret
Ret
Figure 12. Current Path in Negative Polarity ESD/EFT Event Common Mode: Line-to-GND
14
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Circuit Protection Solutions for PoE
Surge on N
Surge on P
D3
TVS 8V
½ PSOT08C (Protek)
D3
TVS 8V
½ PSOT08C (Protek)
+48V
48V
SW
D1 Schottky
STPS1H100A
or MBRS1100 T3
D5
SMJ58
220nF/
100V
C1
0.1uF
+48V
FB1
Fair-Rite
2512066017Y1
D2
¼ SR70
or ES2BA
or STTH102
220uF/
100V
48V
SW
FB2
FB1
75
ohms
N
1nF/
2kV
+48V
D4
¼ SR70 (Protek &
Semtech)
or
STPS1H100A (ST )
or
STTH102 (ST)
V48
D5
SMJ58
220nF/
100V
C1
0.1uF
Ferrite beads
Fair-Rite
2512066017Y1
D2
¼ SR70
or ES2BA
or STTH102
220uF/
100V
FB2
10nF
10nF
P
D1 Schottky
STPS1H100A
or MBRS1100T3
Ferrite beads
ESD
capacitors
10nF
10nF
75
ohms
P
75
ohms
N
1nF/
2kV
+48V
1nF/
2kV
75
ohms
D4
¼ SR70 (Protek &
Semtech)
or
STPS1H100A (ST)
or
STTH102 (ST)
C4520X7R3D102K
V48
ESD
capacitors
1nF/
2kV
C4520X7R3D102K
Ret
Ret
Figure 13. Current Path in Positive Polarity Surge Event Common Mode: Line-to-GND
Surge on N
Surge on P
D3
TVS 8V
½ PSOT08C (Protek)
D3
TVS 8V
½ PSOT08C (Protek)
+48V
48V
SW
D5
SMJ58
D1 Schottky
STPS1H100A
or MBRS1100 T3
Fair-Rite
48V
SW
2512066017Y1
D2
¼ SR70
or ES2BA
or STTH102
220uF/
100V
FB1
D5
SMJ58
C1
0.1uF
Fair-Rite
2512066017Y1
D2
¼ SR70
or ES2BA
or STTH102
220uF/
100V
FB2
P
75
ohms
75
ohms
N
1nF/
2kV
+48V
1nF/
2kV
+48V
D4
¼ SR70 (Protek &
Semtech)
or
STPS1H100A (ST)
or
STTH102 (ST)
V48
ESD
capacitors
10nF
10nF
10nF
75
ohms
N
Ferrite beads
220nF/
100V
FB2
10nF
P
D1 Schottky
STPS1H100A
or MBRS1100 T3
Ferrite beads
220nF/
100V
C1
0.1uF
+48V
FB1
D4
¼ SR70 (Protek &
Semtech)
or
STPS1H100A (ST)
or
STTH102 (ST)
1nF/
2kV
V48
C4520X7R3D102K
75
ohms
ESD
capacitors
1nF/
2kV
C4520X7R3D102K
Ret
Ret
Figure 14. Current Path in Negative Polarity Surge Event Common Mode: Line-to-GND
20A
10A
Negative EFT with 56V present : the current circulates at first in BS termination
and then in the schottky diode (not at all in the parallel SR70)
(11.012n,-9.2771)
The series ferrite bead also plays an important role
0A
-10A
(16.140n,-16.146)
SEL>>
-20A
1 58V 2 400V
56V
-I(D15)
I(R30)
I(V13)
I(V29)
0V
(11.012n,-658.583)
54V
-400V
(26.220n,54.394)
52V
>>
-800V
0s
1
10ns
V(D15:2) 2
20ns
V(L1:1)
30ns
40ns
50ns
60ns
70ns
80ns
90ns
100ns
Time
NOTE: Upper graph: BS termination current (blue), upper SR70 diode current (green), Schottky diode current
(yellow)
Lower graph: N (drain) terminal voltage of PSE power switch (green), BS termination voltage (red)
Figure 15. Negative EFT Simulation on N Terminal With 56V Power Supply ON
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Circuit Protection Solutions for PoE
20A
10A
Negative EFT on N and 56V OFF (but connected) : the current circulates at first in BS termination
and then mainly in the schottky diode (a little bit in the parallel SR70)
(11.012n,-9.2771)
The series ferrite bead also plays an important role
0A
(24.300n,-1.8923)
-10A
SEL>>
-20A
1 5.0V 2 400V
(16.260n,-14.796)
-I(D15)
I(R30)
I(V13)
I(V29)
From one EFT pulse to the next one, the 0.22uF is gradually charged and the current will be
gradually shared between the parallel SR70 and the schottky
Note also that the delta V on the 0.22uF during an EFT pulse will decrease
as its initial voltage increases so that a lot of cycles are required before all current circulates in the SR70 only
0V
0V
(91.140n,740.152m)
-400V
(11.100n,-713.398)
-5.0V
>>
-800V
0s
1
10ns
20ns
V(D15:2) V(C19:2,L1:2) 2
(25.060n,-1.4844)
30ns
V(L1:1)
40ns
50ns
60ns
70ns
80ns
90ns
100ns
Time
NOTE: Upper graph: BS termination current (blue), upper SR70 diode current (green), Schottky diode current
(yellow)
Lower graph: voltage on N (drain) terminal of PSE power switch (green), voltage on capacitor C2 (across P
and N) (red), BS termination voltage (blue).
Figure 16. Negative EFT Simulation on N Terminal With 56V Power Supply OFF
20A
Negative EFT on N and 56V OFF (but connected) : the current circulates at first in BS termination
and then mainly in the schottky diode (a little bit in the parallel SR70)
(11.012n,-9.2771)
(15.740n,-6.9017)
The series ferrite bead also plays an important role
0A
(21.780n,-9.2046)
SEL>>
-20A
1 5.0V 2 400V
-I(D15)
I(R30) I(V13)
(0.000,3.0000)
I(V29)
From one EFT pulse to the next one, the 0.22uF is gradually charged and the current will be
(85.500n,3.2107)
gradually shared between the parallel SR70 and the schottky
0V
0V
Note also that the delta V on the 0.22uF during an EFT pulse will decrease
as its initial voltage increases so that a lot of cycles are required before
-400V
(11.100n,-713.398)
all current circulates in the SR70 only
(19.340n,-3.9544)
Vinitial of 0.22uF : 3V
-5.0V
>>
-800V
0s
1
10ns
20ns
V(D15:2) V(C19:2,L1:2)2
30ns
V(L1:1)
40ns
50ns
60ns
70ns
80ns
90ns
100ns
Time
NOTE: Upper graph: BS termination current (blue), upper SR70 diode current (green), Schottky diode current
(yellow)
Lower graph: voltage on N (drain) terminal of PSE power switch (green), voltage on capacitor C2 (across P
and N) (red), BS termination voltage (blue)
Figure 17. Negative EFT Simulation on N Terminal With 56V Power Supply OFF and With 3V Initially on
C2
16
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40A
(3.9619u,22.638)
Negative Surge test on PSE with complete protection except CM choke : 0.1uF = C22 = C25
The current circulates at first through the schottky for a while and then through the parallel SR70
since the 0.22 uF gets recharged (the behaviour will be different if the 56V is not present)
0A
(3.2692u,-19.973)
-40A
60V
I(D15) I(V13)
I(C36) I(V16)
40V
The SR70 is not a perfect low impedance but it is enough
20V
(3.9219u,-8.2581)
0V
SEL>>
-10V
0s
V(R32:2)
5us
10us
15us
20us
25us
30us
35us
40us
45us
50us
Time
Upper graph: lower SR70 diode current (green), Schottky diode current (yellow)
Lower graph: voltage on N (drain) terminal of PSE power switch (green)
Figure 18. Negative Surge Simulation on N Terminal With 56 V Power Supply ON
SLVA233A – April 2006 – Revised August 2006
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Circuit Protection Solutions for PoE
Bob Smith
terminations
FB1
1 per
port
Ferrite beads
FB2
D3
TVS 8V
½ PSOT08C
Earth GND
POE
transformers
2 TX & 2 RX
GND
plane
48V-GND
planes
Fuses +
ferrite
beads
Diodes and
caps
CM
TPS2384
Fuses +
ferrite
beads
BST
D1 Schottky
POE
transformers
2 TX & 2 RX
L1
D4
¼ SR70
RJ45
out
48V IN
48V
N1
D4
¼ SR70
0.1uF
Earth
GND
RJ45
out
Earth GND
+48V
RJ45
in
48V
suppressor
D5
SMJ58
N1
GND
P1
+48V
BST
P1,P2
N1,N2
GND,48V
P1
RJ45
in
220uF
/100V
Lx
Optional common
mode choke
Figure 19. Layout for a Dual Port PSE
To
Sensitive
Circuit
{
To
Sensitive
Circuit
BAD
{
GOOD
Figure 20. Interconnection to Clamping Devices
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References
FB1
1 per
port
Bob Smith
terminations
Ferrite beads
FB2
Earth GND
POE
transformers
2 TX & 2 RX
BST
RJ45
in
RJ45
out
D3
TVS 8V
½ PSOT08C
Earth GND
POE
transformers
2 TX & 2 RX
GND
plane
48V-GND
planes
P3, P4
N3,N4
GND
TPS2384
P1
GND
CM
Diodes and
caps
CM
Diodes and
caps
Fuses + Fuses +
ferrite
ferrite
beads
beads
L1
BST
N1
POE
transformers
2 TX & 2 RX
Lx
Optional common
mode choke
P1
+48V
D1 Schottky
BST
Fuses + Fuses +
ferrite
ferrite
beads
beads
P1,P2
N1,N2
GND,48V
RJ45
in
BST
RJ45
out
D4
¼ SR70
48V IN
N1
D4
¼ SR70
0.1uF
Earth
GND
48V
RJ45
out
Earth GND
RJ45
in
+48V
48V
suppressor
D5
SMJ58
220uF
/100V
RJ45
Earth GND
out
Earth GND
POE
transformers
2 TX & 2 RX
RJ45
in
Figure 21. Layout for a Quad Port PSE
7
References
1.
2.
3.
4.
5.
6.
7.
Protection of Electronic Circuits from Overvoltages, Ronald B. Standler, Dover Publications inc., 2002
IEC 61000-4-2, 2001-04
IEC 61000-4-4, 2004-7
IEC 61000-4-5, 2001-4
ITU-T recommendations K.20, K.21, K.44, and K.45
GR-1089-CORE, Issue 4.
Design in Transient Protection for Power-Bus and Data Lines, David W. Hutchins, Electronic Design,
July 1990
8. Electrical-Transient Immunity: a Growing Imperative for System Design, O. Melville Clark and Donald
E. Neill, Electronic Design, January 1992
9. TVS Diode Application Note, Semtech AN96-07, Revision 02/4/2002
10. Method to Enhance the Performance of Category 5 Cable in the Electromagnetic Environment, Bob
Smith, January 25th, 1993
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19
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