EE241
EE241 - Spring 2001
Advanced Digital Integrated Circuits
Lecture 12
Low Power Design
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Self-Resetting Logic
Signals are pulses, not levels
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Self-Resetting Logic
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Sense-Amplifying Logic
Matsui,
JSSC 12/94
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SA-F/F
Falling edge
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Rising edge
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Dynamic Logic with SA-F/F
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Example
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4-Bit Adder
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20-Bit Carry-Skip Adder
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GHz Logic with Sense Amplifiers
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Takahashi, JSSC 5/99
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Read-out scheme
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Implemented Macros
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Rotator (ROT)
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Incrementer (INC)
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Low Power, Low Energy
Circuit Design
Architectures, Circuits and
Technology
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Literature
• Chapter 4, Low-Voltage Technologies, by Kuroda
and Sakurai
• Chapter 3, Techniques for Leakage Power
Reduction, by De, et al.
• A. Chandrakasan and R. Brodersen, “Low Power
CMOS Design”, Kluwer Academic Publishers, 1995.
• J. Rabaey and M. Pedram, Ed., “Low Power Design
Methodologies”, Kluwer Academic Publishers, 1995.
• Proceedings of the IEEE, Special Issue on Low
Power, April 1995.
• A. Chandrakasan and R. Brodersen, “Low-Power
CMOS Design”, IEEE Press, 1998 (Reprint Volume)
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Power vs. Energy
l
Power in high performance systems
» Peak power - power delivery, removal
l
Energy in portable systems
» Battery life
l
l
Constant throughput vs. burst-mode
computation
Active vs. standby consumption
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Principles of Power Reduction
(
)
P ~ α ⋅ C L ⋅ Vswing + I SC ⋅ ∆t SC ⋅ VDD ⋅ f
+ (I DC + I Leak )VDD
l
l
l
l
α - switching
probability
CL – load capacitance
Vswing – voltage swing
f - frequency
Dominant:
l
l
l
l
Isc – mean value of
switching transient current
∆tsc – short current time
IDC – static current
Ileak – leakage current
P ~ α ⋅ C L ⋅ Vswing ⋅ VDD ⋅ f
Kuroda, Sakurai, IEICE 4/95
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Active Power Reduction
P ~ α ⋅ C L ⋅ Vswing ⋅ VDD ⋅ f
E ~ α ⋅ C L ⋅ Vswing ⋅ VDD
Reducing switching probability (α)
» Architectures
» Power simulators/estimators (time consuming)
» Glitching power reduction (15-20%)
Reducing load capacitance
» Technology scaling
» Gate sizing, minimization, interconnect, CAD
» Circuit techniques (PTL, …)
Reducing supply voltage
» Quadratic impact on power
» Impact on delay – how to maintain throughput?
Reducing frequency
l
l
l
l
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Trends in Power Dissipation
1
0.1
0.01
80
MPU
DSP
85
90
Year
(a) Power dissipation vs. year.
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3
κ
s
ear
3y
/
x4
0.7
100
∝
Power Dissipation (W)
10
∝κ
1000
Power Density (mW/mm2 )
ears
x1.4 / 3 y
100
10
1
1
Scaling Factor κ
•inormalized by 4µm design rule•j
(b) Power density vs. scaling factor.
From Kuroda
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Processor Power
100
Max Power (Watts)
Pentium II (R)
Pentium Pro
(R)
Pentium(R)
Pentium(R)
MMX
10
486
486
1
386
386
1.5µ
?
1µ
0.8µ
0.6µ
0.35µ 0.25µ 0.18µ 0.13µ
Lead processor power increases every generation
Compactions provide higher performance at lower power
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Power will be a problem
100000
18KW
5KW
1.5KW
500W
Power (Watts)
10000
1000
100
Pentium® proc
286 486
8086 386
8085
8080
8008
1 4004
10
S. Borkar
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power delivery and dissipation will be prohibitive
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Nominal Capacity (Watt-hours / lb)
Portability
BATTERY
(40+ lbs)
50
Rechargable Lithium
40
Ni-Metal Hydride
30
20
Nickel-Cadium
10
0
65
70
75
80
85
90
95
Year
Multimedia Terminals
Expected Battery Lifetime increase
over next 5 years: 30-40%
Laptop Computers
Digital Cellular Telephony
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Shannon Beats Moore’s Law
Algorithmic Complexity
(Shannon’s Law)
10000000
3G
1000000
Processor Performance
(~Moore’s Law)
100000
10000
2G
1000
100
10
Battery Capacity
1G
19
80
19
84
19
88
19
92
19
96
20
00
20
04
20
08
20
12
20
16
20
20
1
Source: Data compiled from multiple sources
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Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Leakage
Leaking transistors and diodes
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
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Dynamic Power Consumption
Vdd
E0->1 = C LVdd2
PMOS
A1
AN
isupply
NETWORK
Vout
NMOS
CL
NETWORK
E
E
Vdd
T
T
= ∫ P ( t ) dt = V ∫ i
t ) dt = V
C dV
= C •V 2
(
0→1
dd supply
dd ∫
L out
L
dd
0
0
0
cap
T
T
Vdd
1
2
= ∫P
t dt = ∫ V
i
t
= ∫ C V
dV
= --- C • V
cap ( )
out cap( )dt
L out out
dd
2 L
0
0
0
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Circuits with Reduced Swing
Vdd
Vdd
Vdd -Vt
CL
E 0 → 1 = C L • V dd • ( V dd – Vt )
Can exploit reduced sw ing to lower power
(e.g., reduced bit-line swing in memory)
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Dynamic Power Consumption Revisited
Power = Energy/transition * transition rate
= CL * Vdd2 * f0→1
= CL * Vdd 2 * P0→1* f
= CEFF * Vdd2 * f
Power Dissipation is Data Dependent
Function of Switching Activity
CEFF = Effective Capacitance = CL * P0→1
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Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
E N = CL • V dd2 • n (N )
EN : the energy consumed for N clock cycles
n(N): the number o f 0->1 transition in N clock cycles
P
avg
=
EN
2
n (N )
lim -------- • f
=  lim ------------  • C • V
• f clk
clk
dd


N
N
N→∞
N→∞
L
α0 → 1 =
n( N )
lim -----------N→∞ N
P avg = α0
• C • V dd 2 • f clk
→1
L
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Type of Logic Function:
NOR vs. XOR
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Type of Logic Function:
NOR vs. XOR
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Transition Probabilities
P0->1(NOR,NAND) = (2N-1)/22N P0->1(XOR) = 1/4
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Transition Probabilities for Basic
Gates
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Transition Probability of
2-input NOR Gate
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How about Dynamic Circuits?
VDD
φ
Mp
Out
In1
In2
In3
PDN
φ
Me
Power is Only Dissipated when Out=0!
CEFF = P(Out=0).CL
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2-input NAND Gate
Example: Dynamic 2 Input NOR Gate
Assume:
P(A=1) = 1/2
P(B=1) = 1/2
Then:
P(Out=0) = 3/4
CEFF = 3/4 * CL
Switching Activity Is Always Higher in Dynamic Circuits
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Type of Logic Style:
Static vs. Dynamic
Vdd
Vdd
CLK
A
A
B
A
B
CL
B
CLK
CL
Power is only dissipated when Out=0!
STATIC NOR
DYNAMIC NOR
α0->1 = 3/16
α0
→1
N0
3
= ------- = --N
4
2
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Transition Probabilities for Dynamic
Gates
Switching Activity for Precharged Dynamic Gates
P0→1 = P0
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Another Logic Style: Dynamic
DCVSL
Vdd
Vdd
OUTB
OUT
I
IN
INB
I
Guaranteed transition for every operation!
α0->1 = 1
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Problem: Reconvergent
Fanout
A
X
B
Z
Reconvergence
P(Z=1) = P(B=1) . P(X=1 | B=1)
Becomes complex and intractable real fast
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Glitching in Static CMOS
also called: dynamic hazards
X
A
B
Z
C
ABC
101
000
X
Z
Unit Delay
Observe: No glitching in dynamic circuits
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Example 1: Chain of NOR Gates
out1
out2
out3
out4
out5
1
...
V (Volt)
6.0
4.0
out2
2.0
out1
out4
out3
out6
out8
out5
out7
0.0
0
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1
t (nsec)
2
3
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Example 2: Adder Circuit
Add0
Cin
Add1
Sum Output Voltage, Volts
S0
Add2
Add14
S2
S14
S1
4.0
Add15
S15
4
S15
6
2.0
3
S10
Cin
5
S1
2
0.0
0
5
10
Time, ns
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How to Cope with Glitching?
0
F1
0
1
F2
0
0
2
F3
0
0
F1
1
F3
0
0
F2
1
Equalize Lengths of Timing Paths Through Design
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Example: Carry Ripple versus Carry Lookahead
F
A0
A1
A2
A3
A4
A5
A6
A7
Ripple
A0
A1
A2
A3
A4
A5
F
Lookahead
A6
A7
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