COMON:
SOI Multigate Devices Modeling
Alexander Kloes, Michael Graef, Franziska Hain, Thomas Holtij, Mike Schwarz
Technische Hochschule Mittelhessen, Germany
NanoP - Competence Center Nanotechnology and Photonics
Research Group Nanoelectronics / Device Modeling
12. April 2013
Spring MOS-AK/GSA Workshop 2013 - Alexander Kloes
1
Outline
1. Introduction
1.1 Current Flow in MuG-FETs
1.2 Challenges to Compact Modeling
1.3 Conformal Mapping
2. Conventional MuG-FETs
2.1 Undoped / Doped Junction-based DG-FET
2.2 Junctionless DG-FET
2.3 Trigate-FET
3. Tunneling Devices
3.1 Schottky Barrier DG-FET
3.2 Tunnel FET
4. Conclusions
12. April 2013
Spring MOS-AK/GSA Workshop 2013 - Alexander Kloes
2
Outline
1. Introduction
1.1 Current Flow in MuG-FETs
1.2 Challenges to Compact Modeling
1.3 Conformal Mapping
2. Conventional MuG-FETs
2.1 Undoped / Doped Junction-based DG-FET
2.2 Junctionless DG-FET
2.3 Trigate-FET
3. Tunneling Devices
3.1 Schottky Barrier DG-FET
3.2 Tunnel FET
4. Conclusions
12. April 2013
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1.1 Current Flow in MuG-FETs
Current flow in Trigate FETs: in fact a 3D problem!
Most leaky path in lightly doped device:
 below VT: channel center (most DIBL)
 above VT: channel surface
 Device first switches on in corners (max. gate control)
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Oxide
Drain
Gate
Drain
Gate
Oxide
SOI
Drain
Gate
Oxide
Source
Source
Gate
below VT
above VT
Spring MOS-AK/GSA Workshop 2013 - Alexander Kloes
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1.1 Current Flow in MuG-FETs
TCAD: Transfer Characteristics and Transconductance
Hch=50nm
Tch=20nm
 Below VT:
center current dominates
 Above VT:
surface current dominates
[1] A. Kloes, M. Weidemann, M. Schwarz: Analytical Current Equation for Short-Channel SOI Multigate FETs Including 3D
Effects, in Solid-State Electronics, Vol. 54, No. 11, 2010.
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1.1 Current Flow in MuG-FETs
Lightly-doped short-channel Trigate FET
Position of most leaky path along channel (above VT)
Drain
Gate
Oxide
Source
Source
Gate
SOI
channel length
shortening
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1.2 Challenges to Compact Modeling
Challenges to compact modeling:
 2D or 3D potential problem
 Compact models require analytical (closed form) solution
 Minimum fitting parameters for scalability and predictive ability
This work:
 DC modeling only
Simplifications:




(Mostly) neglect quantum confinement (Tch > 10nm)
No fringing fields in BOX
Neglect back gate
Drift-diffusion transport
But…
 Inherently include 2D/3D effects without the need of any fitting parameters!
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1.3 Conformal Mapping
Approach to solve 2D potential problem:
∆Φ ( x, y ) = −
Qdep + qinv
ε Si
Poisson‘s equation
 Map area of interest in complex plane Z upon
simplified geometry in complex plane W
(Schwarz-Christoffel transformation)
 Solve potential problem in plane W
(e.g. by Poisson‘s integral)
 Re-map solution to plane Z
 Prefer 2D Laplacian instead of
Poisson equation
(to avoid mapping of space charge)
[2] Kloes, A., Kostka, A.: A new analytical method of solving 2D Poisson´s equation in MOS devices applied to threshold voltage
and subthreshold modeling, Solid-State Electron., Vol. 39, No. 12, pp. 1761–1775, 1996
[3] E. Weber, Electromagnetic fields, Vol. I., Mapping of fields. John Wiley, New York, 1950
12. April 2013
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Outline
1. Introduction
1.1 Current Flow in MuG-FETs
1.2 Challenges to Compact Modeling
1.3 Conformal Mapping
2. Conventional MuG-FETs
2.1 Undoped / Doped Junction-based DG-FET
2.2 Junctionless DG-FET
2.3 Trigate-FET
3. Tunneling Devices
3.1 Schottky Barrier DG-FET
3.2 Tunnel FET
4. Conclusions
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2.1 Undoped / Doped Junction-based DG-FET
Double-Gate FET:
 Undoped / doped channel
 Analytical 2D potential solution for Poisson equation
 Neglect mobile charge (subthreshold)
 Closed form solution by conformal mapping technique
 Extend solution to strong inversion
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2.1 Undoped / Doped Junction-based DG-FET
Definition of Model Structure
 2D potential problem:
 Scaled oxide thickness introduced
 Source/drain regions are cut out for simplicity
NA
NA
Complete DG-FET structure (a), and simplified structure (b)
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2.1 Undoped / Doped Junction-based DG-FET
Two-dimensional solution of Poisson's equation
 2D Poisson’s equation:
y
NA
 Solution is decomposed into
1D particular solution φp(y)
and 2D Laplace solution ϕ(x,y)
[4] Holtij, M. Schwarz, A. Kloes, B. Iniguez: Threshold Voltage, and 2D Potential Modeling Within Short-Channel Junctionless DG
MOSFETs in Subthreshold Region, Solid State Electron (2013).
12. April 2013
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2.1 Undoped / Doped Junction-based DG-FET
Decomposition of 4-corner structure
 Two 2-corner structures
 Source related case and drain related case
[5] M. Schwarz, T. Holtij, A. Kloes, B. Iniguez: Analytical Compact Modeling Framework for the 2D Electrostatics in Lightly Doped
Double-Gate MOSFETs, Solid-State Electronics, Vol. 69, No. 1, March 2012
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2.1 Undoped / Doped Junction-based DG-FET
 2D Laplacian is solved by conformal mapping of 2-corner structure:
Mapping from z-plane (a) upon upper half of w-plane (b) with analytical function
 Poisson's integral in w-plane results in closed form solutions for potential and
electric field
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2.1 Undoped / Doped Junction-based DG-FET
Potential along center line of DG-FET
(L = 22 nm, Tch = 10 nm, NA = 5∙1018 cm-3, Vg = -0.4 V…0.3 V, Vd = 1 V)
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2.1 Undoped / Doped Junction-based DG-FET
Current calculation

Mobile charge at source end of channel derived from 1D solution with Boltzmann
statistics and volume inversion:

Parameter α accounts for slope degradation by short-channel effects:

Reference charge in sth region (from 2D calculations):

Total current calculated by

Structural confinement included by band gap widening

Standard expressions for field-dependent mobility
center
surface
[6] A. Kloes, M. Schwarz, T. Holtij, A. Navas: Quantum Confinement and Volume Inversion in MOS3 Model for
Short-Channel Tri-Gate MOSFETs, submitted to IEEE Trans. Electron Devices
12. April 2013
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2.1 Undoped / Doped Junction-based DG-FET
Model compared to TCAD (symbols)
Oxide
Gate
Drain
(lightly doped FinFET)
Oxide
Gate
Drain
Center current
Total current
Surface current
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Outline
1. Introduction
1.1 Current Flow in MuG-FETs
1.2 Challenges to Compact Modeling
1.3 Conformal Mapping
2. Conventional MuG-FETs
2.1 Undoped / Doped Junction-based DG-FET
2.2 Junctionless DG-FET
2.3 Trigate-FET
3. Tunneling Devices
3.1 Schottky Barrier DG-FET
3.2 Tunnel FET
4. Conclusions
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2.2 Junctionless DG-FET
Motivation for junctionless MOSFET:
 Inversion mode MOSFET at nanometer scale
require steep s/d junction profile
 Fabrication difficulties
Junctionless transistors (JLTs):
 Simplified processing
 Better electrical properties
(reduced SCEs)
 Full CMOS compatibility
[7] J.-P. Colinge et al.: Nanowire transistors without junctions, Nat Nano, Vol 5, no. 3, 2010, pp. 225 – 229
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2.2 Junctionless DG-FET
Operation Modes of JL DG-FET
 (a) Subthreshold region => channel fully depleted (off-state)
 (b) Bulk current mode => channel region partially depleted
 (c) Flat-band mode => complete channel region neutral (on-state)
 (d) Accumulation mode => charges accumulated at Si-SiO2 interface
In contrast to conventional inversion mode devices
 On-state @ bulk current mode; only majority carriers carry current
 Transition depletion / accumulation results in two dQi /dVg slopes
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2.2 Junctionless DG-FET
Modeling of JL DG-FET
 Same approach as for doped junction-based DG MOSFETs
 Difference between junction-based and junctionless DG MOSFET
simply by reversed sign of depletion charge
 Extend mobile charge model to volume / surface conduction mode
[8] T. Holtij, M. Schwarz, M. Graef, F. Hain, A. Kloes, B. Iniguez: 2D Current Model for Junctionless DG MOSFETs,
Proceedings EuroSOI 2013, Paris, 2013
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2.2 Junctionless DG-FET
Threshold voltage vs. channel length
Tch = 10 nm
tox = 2 nm
εox = 7
→ Strong dependence of VT on doping implies large variability
[9] T. Holtij, M. Schwarz, A. Kloes, B. Iniguez: Threshold voltage, and 2D potential modeling within short-channel junctionless
DG MOSFETs in subthreshold region, accepted for publication in Solid-State Electronics, 2013
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2.2 Junctionless DG-FET
Threshold voltage vs. channel doping
Tch = 10 nm
tox = 2 nm
εox = 7
→ VT strongly degraded for doping concentrations above ND = 1019 cm-3
[9] T. Holtij, M. Schwarz, A. Kloes, B. Iniguez: Threshold voltage, and 2D potential modeling within short-channel junctionless
DG MOSFETs in subthreshold region, accepted for publication in Solid-State Electronics, 2013
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2.2 Junctionless DG-FET
Transfer and Output Characteristics
(LG = 22 nm, Tch = 10 nm, tox = 2nm, channel doping ND = 1019cm-3)
[10] T. Holtij, M. Schwarz, M. Graef, F. Hain, A. Kloes, B. Iñíguez: Model for Investigation of Ion/Ioff Ratios in ShortChannel Junctionless Double Gate MOSFETs, Proceedings ULIS 2013, Warwick, 2013
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2.2 Junctionless DG-FET
Junction-based vs. junctionless DG MOSFET
(LG = 22 nm, Tch = 10 nm, tox = 2nm, channel doping NA/D = ±1018cm-3)
[11] T. Holtij, M. Schwarz, A. Kloes, B. Iniguez: Analytical 2D Modeling of Junctionless and Junction-Based Short-Channel Multigate
MOSFETs, ESSDERC Fringe, 2012
12. April 2013
Spring MOS-AK/GSA Workshop 2013 - Alexander Kloes
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Outline
1. Introduction
1.1 Current Flow in MuG-FETs
1.2 Challenges to Compact Modeling
1.3 Conformal Mapping
2. Conventional MuG-FETs
2.1 Undoped / Doped Junction-based DG-FET
2.2 Junctionless DG-FET
2.3 Trigate-FET
3. Tunneling Devices
3.1 Schottky Barrier DG-FET
3.2 Tunnel FET
4. Conclusions
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2.3 Trigate-FET
Modeling of lightly doped Trigate-FET
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Drain
Gate
Oxide
Gate
Source
Source
 Solve 3D Poisson below VT
at potential barrier only
 Decompose potential problem
into 2-corner structures
 Calculate mobile charge below VT
for center channel current
 Apply DG-FET current model
including volume inversion
SOI
27
2.3 Trigate-FET
3D Laplacian solved by conformal mapping
Step 1:
Source related case
Vg
Vg
Vbi
source related
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2.3 Trigate-FET
Step 2:
Drain related case
drain related
Vbi+Vds-Vg
0
0
Φ DG(z)
source related
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2.3 Trigate-FET
Vg-Φ DG (z)
Step 3:
Top gate related case
Vg- Φ DG(z)
0
Vbi+Vds-Vg
Φ DG(z)
Vg
Vbi
drain related
0
0
0
Vg
z
top gate related
Result:
Explicit model for
potential at barrier
source related
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Gate

Integral channel charge at virtual source
(Boltzmann statistics) below VT:

Channel charge above VT by applying Lambert-W function using
degraded slope from 3D potential solution
(→ DG-FET)

Total current:
Oxide
Current Calculation:
Drain
2.3 Trigate-FET
[12] Kloes et al., “MOS3: A New Physics-Based Explicit Compact Model for Lightly-Doped Short-Channel TripleGate SOI MOSFETs,” IEEE Trans. Electron Devices, Vol. 59, No. 2, February 2012
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2.3 Trigate-FET
Trigate Model Compared to Measurements
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2.3 Trigate-FET
Trigate Model Compared to Measurements
Hch=60nm / L=53nm /Tch=30nm
x 10-5
7
10 -5
6
Vds=1V
4
10 -7
3
Vds=0.05V
10 -8
gm/Ids [1/V]
10 -6
Ids [A]
Ids [A]
5
10 -9
1
0
0.2
0.4
0.6
Vds=0.05V
10 -10
1
0.8
10-1
0
Vgs [V]
Hch=60nm / L=53nm /Tch=30nm
x 10-4
1
3.5
Vgs=0.4/0.6/0.8/1.0/1.2V
0.2
x 10-4
0.4
0.6
0.8
Vgs [V]
Hch=60nm / L=53nm /Tch=30nm
1
3
0.8
2.5
gds [ A/ V]
Ids [A]
Vds=1V
101
100
2
0
Hch=60nm / L=53nm /Tch=30nm
102
0.6
0.4
2
1.5
Vgs=0.4/0.6/0.8/1/1.2V
1
0.2
0
0.5
0
0
0.2
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0.4
0.6
Vds [V]
0.8
1
1.2
0
0.2
0.4
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0.6
Vds [V]
0.8
1
1.2
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2.3 Trigate-FET
Trigate Model Compared to TCAD With NEGF / Ballistic:
(Multigate nanowire FET simulation tool / nanohub.org [14])
[13] A. Kloes, M. Schwarz, T. Holtij, A. Navas: Quantum Confinement and Volume Inversion in MOS3 Model for
Short-Channel Tri-Gate MOSFETs, submitted to IEEE Trans. Electron Devices
[14] M. Shin: ”Efficient simulation of silicon nanowire field effect transistors and their scaling behavior,”
J. Appl. Phys. 101, 2007
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Outline
1. Introduction
1.1 Current Flow in MuG-FETs
1.2 Challenges to Compact Modeling
1.3 Conformal Mapping
2. Conventional MuG-FETs
2.1 Undoped / Doped Junction-based DG-FET
2.2 Junctionless DG-FET
2.3 Trigate-FET
3. Tunneling Devices
3.1 Schottky Barrier DG-FET
3.2 Tunnel FET
4. Conclusions
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3.1 Schottky-Barrier DG-FET
Schottky Barrier MOSFET
 Metallic / silicide source/drain
 Advantages:
− reduction of parasitic resistances
− higher drive current
− no channel doping needed
 Modeling approach:
− Closed form solution for potential and electric field from DG-FET model
(modified s/d boundaries)
− Analytical model for current from tunneling and thermionic emission
− 2D effects must be included
[15] Bing-Yue Tsui, Chi-Pei Lu: Current Transport Mechanisms of Schottky Barrier and Modified Schottky Barrier
MOSFETs, in Proceedings ESSDERC 2007, pp. 307-310
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3.1 Schottky-Barrier DG-FET
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3.1 Schottky-Barrier DG-FET
2D Modeling of Tunneling Current (1)
 WKB (Wentzel-Kramers-Brillouin)
approximation is applied
 Calculation for each slice
from gate to gate
 Quasi-2D effects and potential
profile are captured by individual
triangular shape at each position
of carrier generation
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3/ 2
Tunneling probability: 

(
)
−
4
2
(
,
)
⋅
m
E
x
y
x


T ( E , x, y ) = exp


3q E ( x, y )


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3.1 Schottky-Barrier DG-FET
2D Modeling of Tunneling Current (2)
 Tunneling current density in one slice:
 Integrate from gate to gate:
 Analytical approximations result
in closed form model equations
[16] M. Schwarz, T. Holtij, A. Kloes, B. Iniguez: Compact Modeling Solutions for Short-Channel SOI Schottky
Barrier MOSFETs, Solid-State Electronics, Vol. 82, pp. 86-98, April 2013
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3.1 Schottky-Barrier DG-FET
2D Modeling of Thermionic Current
 Calculate barrier height within each slice
 Thermionic emission current density in each slice:
 Integrate from gate to gate:
[16] M. Schwarz, T. Holtij, A. Kloes, B. Iniguez: Compact Modeling Solutions for Short-Channel SOI Schottky
Barrier MOSFETs, Solid-State Electronics, Vol. 82, pp. 86-98, April 2013
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3.1 Schottky-Barrier DG-FET
Combine Tunneling and Thermionic Current:
[16] M. Schwarz, T. Holtij, A. Kloes, B. Iniguez: Compact Modeling Solutions for Short-Channel SOI Schottky
Barrier MOSFETs, Solid-State Electronics, Vol. 82, pp. 86-98, April 2013
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3.1 Schottky-Barrier DG-FET
Model vs. TCAD
Transfer Characteristics for various barrier heights
LG = 22 nm, Tch = 10nm, tox = 2 nm,
Symbols: TCAD Sentaurus with non-local band-to-band tunneling model
φBn=0.28eV
φBn=0.1eV
[16] M. Schwarz, T. Holtij, A. Kloes, B. Iniguez: Compact Modeling Solutions for Short-Channel SOI Schottky
Barrier MOSFETs, Solid-State Electronics, Vol. 82, pp. 86-98, April 2013
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3.1 Schottky-Barrier DG-FET
Model vs. Measurements (UTB SB-MOSFET)
(LG = 80 nm, dopant segregated modified Schottky barrier)
[16] M. Schwarz, T. Holtij, A. Kloes, B. Iniguez: Compact Modeling Solutions for Short-Channel SOI Schottky
Barrier MOSFETs, Solid-State Electronics, Vol. 82, pp. 86-98, April 2013
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Outline
1. Introduction
1.1 Current Flow in MuG-FETs
1.2 Challenges to Compact Modeling
1.3 Conformal Mapping
2. Conventional MuG-FETs
2.1 Undoped / Doped Junction-based DG-FET
2.2 Junctionless DG-FET
2.3 Trigate-FET
3. Tunneling Devices
3.1 Schottky Barrier DG-FET
3.2 Tunnel FET
4. Conclusions
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3.2 Tunnel-FET
Tunnel-FET:
 Steep switching behavior
(expected slope < 60mV/dec)
 Carrier transport based on
band-to-band tunneling
 Candidate for quasi-ideal switch
[17] A. M. Ionescu, H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,”
Nature 479, 2011, pp. 329-337
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3.2 Tunnel-FET
Working Principle

Highly doped source/drain regions and intrinsic channel

„Band pass“ filtering of carriers w.r.t. energy
On State
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Off State
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Ambipolar State
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3.2 Tunnel-FET
Modeling of DG-Tunnel-FET:
 Analytical solution of Poisson equation in
channel area without source and drain
 Neglect mobile channel charge
 2D WKB approach for all points in channel
region where tunneling can happen
 Integrate tunneling current densities
within each channel slice
[18] M. Graef, M. Schwarz, T. Holtij, F. Hain, A. Kloes, B. Iñíguez: Two-dimensional Bias Dependent Model for
the Screening Length in Double-Gate Tunnel-FETs, ULIS 2013
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3.2 Tunnel-FET
Transfer characteristics (Si TFET) for various channel thickness
TCAD:

Non-local
band-to-band
tunneling model

Trap assisted
tunneling and
quantum
confinement
neglected
[18] M. Graef, M. Schwarz, T. Holtij, F. Hain, A. Kloes, B. Iñíguez: Two-dimensional Bias Dependent Model for
the Screening Length in Double-Gate Tunnel-FETs, ULIS 2013
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3.2 Tunnel-FET
Transfer characteristics (Si TFET) for various tox
TCAD:

Non-local
band-to-band
tunneling model

Trap assisted
tunneling and
quantum
confinement
neglected
[18] M. Graef, M. Schwarz, T. Holtij, F. Hain, A. Kloes, B. Iñíguez: Two-dimensional Bias Dependent Model for
the Screening Length in Double-Gate Tunnel-FETs, ULIS 2013
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Outline
1. Introduction
1.1 Current Flow in MuG-FETs
1.2 Challenges to Compact Modeling
1.3 Conformal Mapping
2. Conventional MuG-FETs
2.1 Undoped / Doped Junction-based DG-FET
2.2 Junctionless DG-FET
2.3 Trigate-FET
3. Tunneling Devices
3.1 Schottky Barrier DG-FET
3.2 Tunnel FET
4. Conclusions
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4. Conclusions





Analytical closed form solutions for potential in SOI multigate FETs
2D effects inherently included without fitting parameters
Unified current model for inversion mode and junctionless DG-FETs
Compact DC model for triple-gate SOI MOSFETs inherently including 3D
effects without fitting parameters (Verilog-A implementation)
TCAD confirms high accuracy down to L = 22 nm


Potential solution has been extended to SB and Tunnel FETs
Analytical current models for SB DG-FET and DG-TFET
(closed form for SB)

Due to their high scalability the models allow for performance
evaluation of circuits with novel device concepts
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Acknowledgements
 German Research Foundation (DFG) under
Grant KL 1042/3-1
 German Federal Ministry of Education and
Research contract No. 1779X09
 European Commission under the FP7
Project "COMON" (IAPP-218255)
 AdMOS GmbH
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