A Direct-Conversion Mixer With DC-offset
Cancellation for IEEE 802.1 la WLAN Receiver
Qiming Xu, Xueqing Hu, Peng Gao, Jun Yan, Shi Yin
Foster F. Dai, Richard C. Jaeger
Department of Electrical & Computer Engineering
Auburn University
Auburn, Alabama, USA
Institute of Semiconductors
Chinese Academy of Sciences
Beijing, China
daifaOlgauburn.edu
qmxugsemi.ac.cn, yshigred.semi.ac.cn
Abstract-A DC-offset cancellation scheme in the 5GHz directconversion receiver compliant with IEEE 802.11a wireless
LAN standard is described in this paper. It uses the analog
feedback loop to eliminate the DC-offset at the output of the
double-balanced mixer. The mixer has a simulation voltage A
conversion gain of 13dB at 5.2GHz, noise figure of 9.67dB,
IIP3 of 7.6dBm. The solution provides 39.1dB reduction
according to the leakage value at LO and mixer load resistors,
the additional noise figure added to mixer is less than 0.9dB,
the added power dissipation is 0.1mW and was fabricated in
60GHz 0.35,um SiGe BiCMOS technology.
I. INTRODUCTION
Wireless communications will evolve towards high data
rate applications in the next a few years, one of which
primary application is WLAN (IEEE 802.1 la.b.g). In order
to get more features and less cost at RF front sections, the
choice of a suitable receiver implementation requires a
careful study of the system specifications. Superheterodyne
architecture is a traditional receiver patented in 1917 by
Edwin Armstrong [1], which offers the best performance in
most wireless system applications. Nevertheless, the
architecture requires passive filter components mostly
because of the intermediate-frequency (IF) and image-reject,
which have to be high quality factors and often employ
surface acoustic wave (SAW) filter at off-chip [2].
Direct-conversion receivers shown in Fig. 1 have attracted
a great deal of attention over the past a few years. In actual
direct conversion systems, the LO frequency is in the middle
of the RF spectrum under consideration. The higher
frequency components at the output can be easily removed
by active or passive low-pass filter at the baseband. By
eliminating IF stages and the image-reject requirement of the
front-end filters, direct-conversion architecture can
significantly improve on-chip integration of the receiver.
However, this architecture creates additional performance
criteria such as second order intermodulations (IM2), DCoffsets, in-band local oscillator (LO) radiation and flicker
noise that are not presented in a heterodyne counterpart. One
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band
Figure 1. Direct-Conversion Receiver
of the most challenges of these performance criteria is the
effective cancellation of DC-offsets [3].
As shown in Fig. 1, LO leakage exists from the LO port
to the LNA input, mixer input, the antenna and a finite
amount of feedthrough because of substrate coupling and
bond wire coupling [3]. This LO leakage produces a DC
component at mixer output, which is called "LO selfmixing". The DC-offset of a mixer can be separated into two
components: a constant and a time-varying offset. The
constant DC-offset is attributed to the mismatch between the
mixer components and the time-varying DC-offset is
generated by the self-mixing of the LO [4]. The former can
be minimized with the help of specific layout techniques, but
the latter will never be absolutely eliminated. This paper
describes a solution of DC-offset cancellation in a 5GHz
direct-conversion receiver.
In direct-conversion receiver, the down-converted
spectrum is centered at 0Hz. If information contains DCoffset, the SNR will be degraded. In fact, the offset may be
larger than the signal and much larger than thermal or flicker
noise. A down-converted signal may have an amplitude of a
few hundred microvolts while the DC-offset may be in the
range of millivolts, which will degrade the following stages
[5]
There are two common DC-offset cancellation solutions:
5696
*
AC coupling (high pass filter) [6].
ISCAS 2006
* Digital cancellation with DAC sampling [7].
By the means of AC coupling, a very low corner
frequency of the high pass filter is required, indicating large
capacitors, which is not suitable for integration. Digital
solution including DAC will complicate the design and
increase the power dissipation.
The work of this paper focuses on eliminating DC-offset
by analog feedback loops mentioned in [5]. Section II
presents analysis of the mechanism of DC-offset for
mismatch and circuit topology. Section III shows the
simulation results of the mixer and DC-offset cancellation
circuit. Section IV summarized the work.
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CIRCUIT TOPOLOGY AND ANALYSIS
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A. Topology preview
A full direct-conversion receiver topology is illustrated in
Fig. 1. In this solution, DC-offset circuit occurs in the
baseband section following the mixer.
i71
B. Mixer design
The circuit schematic of the mixer is shown in Fig.2,
which is a typical Gilbert cell with single-ended input and
differential output. Inductor Le is used as emitter
degeneration to increase the linearity of the mixer while
consuming little voltage headroom. As mentioned in [8],
when LO is ideal square wave, mixer's voltage gain
2
RL
V T Ire + i)Le
1
where RL is the load resistance and re is the emitter resistance
of Q5 or Q6. Since mixer's IIP3 is proportional to (DGmLe, Le
should be carefully chosen to compromise between the gain
and IIP3.
Noise matching is achieved by sizing Le, selecting
transistors size and operating the RF transistors at the current
density required for minimum noise figure. Combining with
the matching network, Le also achieves simultaneous noise
and power matching [8].
is
S
Since the current in the quad switching transistors
pa
decided by RF transistors below, the current density for peak
achieved by sizing the transistors. In this design, they
are 1/6 of the RF transistors. LO signals are applied to the
base of the quad transistors through buffers, so that their
amplitude can be kept large enough for completely switching.
Lfp)and Cfp)are tuned on the LO+RF frequency to get rid
of the unwanted sideband. The LC tank tuned on the second
RF harmonic, acts as an ac current source in the emitter of
the input transistor pair [7].
fTar#S
C. DC-offset AnalysIs
- se naysls
The bipolar transistors Qs~and Q6 in Fig.2 are simply
modelled as a voltages-controlled current source (VCCS),
and the transistors Q1Q are regarded as ideal switches. The
Figure 2. Schematic of double balanced mixer
dominant nonlinearity source in bipolar transistors Q5 and Q6
is assumedtobetheinputgm-stage.
The nonlinear VCCS is given by
iR
(t)0=
gl11
[v1n (t) + k2vm (t) + k3vm
(t) +
]
(2)
where k is n-order nonlinear coefficient. And therefore, the
output current of mixer can be written as:
'out (t) = iRF (t)gLo (t)
where gLo is the gate function of LO signals denoted as the
Taylors series. The interest is the fundamental and DC
components of iot. (4) shows DC component in mixer output:
VDC = 7hnom RL (IT + gmk2APY )(A 7
+ AR)
(4)
"(4)" is the ideal DC-offset behavioral model of doublebalanced mixer [10], where 1tnom is the duty cycle (typically
A1 is the mismatch in the duty cycle in the transistors
of LO input, IT is the mixer static current which is a half of
the tail current, JR is dominant mismatch in practical process
and ARF is the amplitude of RF signal in the mixer input.
500o%),
According to "(4)" the DC term in IF depends on the
collector resistor mismatch, the value of tail current and the
amplitude modulation component.
D. DC-offset cancellation circuit
Parallelled with the resistor loads RL, a pair of PFETs are
employed to shunt the output current of the mixer under the
~~~~~~~~controlof feedback loop, as shown in Fig.2. The feedback
network consists of common mode (CM) and differential
mode (DM) feedback loops. The output voltage is adjusted
by the shunted current, which must have enough tolerance to
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the amplifier is about
45dB.
H
2
2
(7 ±
4 ie
S_
-
Figure 3. DM feedback loop with Miller Multiplier
severely restricted DC-offset voltage. This current is set at
about 20% of total mixer's collector current in this design.
In the common-mode feedback loop, the common-mode
output voltage is compared with a reference voltage. The
comparison voltage controls the gate of the PFETs in order
to stabilize the common-mode voltage at the mixer output.
The common-mode DC-offset voltage is reduced by this way.
The similar schematic topology is utilized in [5].
In the Gilbert-cell based mixer, differential-mode DCoffset is predominant at the output. The DM feedback loop
circuit is restricted not only by the baseband signal spectral,
but also the noise contributing to the whole receiver.
Therefore, the DM DC-offset correction loop amplifier must
fulfill 3 requirements:
* The loop must have sufficient gain at DC to provide
adequate DC-offset reduction.
* The equivalent output noise of the circuit must be
low enough to avoid degrading the mixer noise
figure remarkably.
* The loop must have gain low enough near the lower
corner frequency of the sub channel (at frequencies
above 150kHz in this case) where the desired signal
is not attenuated significantly.
Following these requests, the differential-mode loop is a
low pass filter with high gain and low cut off frequency. The
schematic of the loop is shown in Fig.3.
The first stage illustrated in Fig.3 utilizes bipolar
transistors in the feedback amplifier, which have higher gain
and lower noise than MOSFETs. However, in the second
stage, a pair of MOSFETs is placed, which generates a
Miller Multiplication with high input impedance. The two
stages loop amplifiers are loaded by PMOS current sources.
The total impedance seen at the output is equal to rol0rO2,
and the gain is given by:
Gain = -gl1
('oi // ro2 )
gain is
CM-l/er=GainsecCu1
1 12
J i
and the second stage
The second stage gain is similar to the first stage, which
allows the Miller effect to generate an effective capacitance
at the inter-stage of amplifier. The Miller effective
tacapacitance is mostly equal to the product of the
compensation capacitance and the second stage gain.
t
C;
M
If+
-f
ia
7MHz,
(6)
,The configuration is a Miller Integrator with 2pF
capacitor which is small enough to be integrated on chip, and
the actual effective input capacitance is about lnF. It is hard
to fabricate a capacitor of lnF since the capacitor is an areaconsuming component. The curve illustrated in Fig.4 shows
the AC response of the differential feedback-loop, which is
close to the ideal model of former requests. With the Miller
capacitor, the feedback loop has gain low enough at 150
KHz, which offers corner frequency enough low for 802.1 la
standard. In Fig.3, the R1 and R2 are a couple pair with
emitter degeneration to adjust the gain.
feedback Amp
+ Gain Of D loop
AC anaIsis
40 3dB
4fl
l00Hzo :73dB
30s
E
,, 20
(5)e5
The gain of first stage is 40.3dB at 0Hz, the phase margin
is equal to 1300. Without the Miller capacitor, bandwidth of
5698
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--l
1. o01. 102
1
04
1
105
ra
1
freq (Hz)
108
7
1°9
Figure 4. Gain of DM loop ac response
DC-offset-tran
pn
RF=-4OdBm
12ns, 25.4nV
25
I
I
201
111
>
10I
5t
_
0
.500
Fgr .D
I
_
1.0
I
1.5
_____
I
2.0
C fstaalssi ixrwt O
fstaayi nmxrwt O
.2.3us
129uV_
I
2.5
3.0
Figure 6. Package model parameter
III. RiESULT
The circuit is simulated in 25(Clbwith the package model
included as shown in Fig.6. A 5.19GHz, -4OdBm sine wave
is applied in RF port and 5.2GHz sine waves is applied in
LO ports. Unlike RF input port, where bondwire parasitic
components can be cancelled by matching network, LO ports
and mixer ground suffer more interference. The mixer with
DC-offset cancellation circuit, without two buffers,
consumes 12.5mA current. It achieves 13dB conversion
voltage gain with 11P3 7.6dBm (1dB compression point 1 .7dBm) and NF 9.7dB.
In the DC-offset simulation, with a 500 mismatch in the
mixer collector resistors (RL), open-loop DC-offset voltage is
44mV, which is reduced to O.23mV by the cancellation
solution. It also shows that large mismatch deteriorates DCoffset.
DC-offset transient analysis is illustrated in Fig.5. With
DC-offset cancellation circuit at the IF ports of the mixer, the
differential DC-offset voltage between positive terminal and
negative terminal is stabilized at 129 V. Table. 1 shows the
simulated result of DC-offset reduction with different input
power level. The value of DC-offset voltage is proportional
to the input power in the RF port, which accords with "(4)".
Fi*5
TABLE I.
Leakage
-4OdBm
|-3OdBm
-2OdBm
DC-offset
ancellati
Figure 7. Die photograph of the ful receiver chip
of this solution is easy for realization, and has little influence
on the performance of the receiver.
ACKNOWLEDGMENT
The authors would like to thank Wei Mao, Desheng Ma,
Gu and Hua Xu for their valuable assistance with
Ming
simulation support, layout support.
REFERENCES
[1] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits,
Cambridge University: London, 1998, ch.l.
[2]
W. Veit, J. Fenk, S. Ganser, K. Hadjizada, S. Heinen, H. Herrmann,
and P. Sehrig, "A 2.7V 800MHz-2.1 GHz transceiver chipset for
mobile radio applications in 25 GHz ft Si-Bipolar,"IEEE
[3]
B. Razavi, "Design Considerations for Direct-Conversion
Receivers," IEEE Transactions on Circuits and Systems-II: Analog
and Digital Processing, vol. 44, no. 6, pp. 428-435, June 1997.
B. Matinpour, S. Chakraborty, J. Laskar, "Novel DC-Offset
Cancellation Techniques for Even-Harmonic Direct Conversion
Receivers," IEEE Transactions on Microwave Theory and
THE DC-OFFSET OF DIFFERENT LEAKAGE
DC-offset
DC-offset DOC
DC-offset
24mV
85mV
220mV
0. 129mV
1.67mV
6.82mV
45.3dB
34.2dB
31.3dB
without DOC
Mixer
Bipolar/BiCMOS Techn.Meet, pp.175-178, October 1994.
reduction
[4]
From the LO leakage and mismatch assumed, the DC-offset
Techniques, vol. 48, no. 12, pp. 2554-2559, December 2000
voltage is reduced by 39.1dB in average with the DC-offset
[5] P. Laferriere, D. Rahn, C. Plett, J. Rogers, "A 5 GHz directconversion receiver with DC offset correction," Circuits and Systems,
cancellation. The noise figure is degraded by 0.87dB with
2004. ISCAS '04, vol.4, pp.23-26, May 2004
this additional part. The feedback loop circuit total current is
[6] W. Namgoong, "Performance of a Direct-Conversion Receiver with
0.3mA. The area occupied is less than 0.1mm2, which is
AC Coupling," IEEE Trans. on Circuits and Systems II, vol.47,
3o
area
O
area
only 0 ofthe full
oftotal receiver.
pp.1556-1559, Dec. 2000.
M.
Faulkner, "DC offset and IM2 removal in direct conversion
[7]
IV. CONCLUSION
receivers", Proc. ISSCC, pp. 372-373,1997.
A direct-conversion mixer with DC-offset cancellation
[8] John Rogers, Calvin Plett, Radio Frequency Integrated Circuits
circuit is presented in this paper. It was implemented in
Design, Artech House Norwood, MA, 2003, ch.7.
Chartered O.35ptm SiGe BiCMOS technology. A die photo of
[9] S. P. Voingescu, M. C. Maliepaard, "5.8GHz and 12.6GHz Si
Bipolar MMICs," IEEE Transactions on Circuits and Systems-II:
the chip is shown in Fig.7. It draws 12.5mA current with
3.3-V supply and provides a conversion gain of 13dB. This
Analog and Digital Processing, vol. 44, no. 6, pp. 428-435, June
DC-offset cancellation has reduced the DC-offset voltage by
3.1B th
nois figue
fiur ade
[10] Kalle Kivekas, ofIP2
Aarnoand DC-offsets
Parssinen, inKari
A. I. Halonen,
39.1aBadiioa
tneacl1t1oal no1e
auclcl to mixer
lxer is1 less.
leSS"Characterization
transconductance
Mixer,"
than 0.9dB; and the power dissipation is 0. 1mW. The circuit
IEEE Transactions on Circuits and Systems-II: Analog and Digital
Processing, vol.48, no.12, pp.1028-1038, November 2001.
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