Package Trends for Today’s and
Future mm-Wave Applications
Maciej Wojnowski, Klaus Pressel, Grit Sommer, Mario Engl
Outline
Introduction
Package Overview
Thin Small Leadless Package (TSLP)
Embedded Wafer-Level Ball Grid Arry (eWLB)
Through Silicon Vias (TSV)
Experimental Results
Conclusion
Page 2
Outline
Introduction
Package Overview
Thin Small Leadless Package (TSLP)
Embedded Wafer-Level Ball Grid Arry (eWLB)
Through Silicon Vias (TSV)
Experimental Results
Conclusion
Page 3
Introduction
Increasing industrial demands
Functionality
(System Integration)
Size
Speed
Cost &
Time to
Market
Low/High
Power
Thermal
Performance
Reliability &
Failure Analysis
Page 4
Package Evolution
Until Today and Towards Tomorrow
22 mm
Functionality
Functionality
Ele
Th ctric
erm al P
e
al
Pe rform
Pin rfo
Co rma ance
un
nc
t
e
P-DIP
Package Downsizing
13 mm
P-TQFP
9,34 mm
BGA
Modules
(SoB)
P-TSOP I/II
Chip
Chip Scale
Scale
Package
Package
Flip-Chip
Flip-Chip
Packing
Packing
Size
Size
- in Package
- on Board
1st
Evolution
2nd
Evolution
THT
SMD
SMD
(Peripheral)
Grid Array
(Area)
3rd
Evolution
System
System Integration
Integration
System in Package
SiP/SoP
3D-Packaging
4th
Evolution
Technology
High performance
Stacked Chips /3D Packaging
Wafer Level Packaging
Page 5
Packaging – Growing Challenges
IC Chip – Peripheral Pad Pitch
(100
Frontend
Waferfab
30 µm)
RFPerformance
Package as Interposer
Bridging the
Electrical
interface
Thermal
interface
Size of
component
Interconnect
Gap
Cost
Backend
Production
Shielding
Interconnect Gap
Customer Board
(1000
Environmental
protection
Reliability &
Signal interface Failure Analysis
(Sensors)
500 µm)
in special cases
400µm, but high
board cost!!
Customer
Page 6
Semiconductor Development
Impact on Packaging
Wireless
Automotive
Analog/RF
Medical
More than Moore: Diversification
Analog/RF
Baseline CMOS: CPU, Memory, Logic
More Moore: Miniaturization
2008
Logic
DRAM
Flash
Co
90nm
m
bi
n
65nm
32nm
22nm
.
.
.
V
Sensors
Actuators
Biochips
Interacting with people and
environment
130nm
45nm
HV
Power
Passives
Information
Processing
Digital content
System-on-chip
(SoC)
in
g
So
Non-digital content
System-in-package
(SiP)
C
an
d
Si
P:
Hi
gh
er
V
al
u
e
Sy
st
em
s
Beyond CMOS
Page 7
Technology for System in Package:
Infineon’s Technology Tree for BGA type
MCM
side-by-side
passive
integration
Modules
FC/ WB
>1 die
>2 dies
F2F
stacked
die
stacked
embedded
stacked
package
µ-FlipChip
Si thru hole
Increasing integration density
WB/WB
Pack. on Pack.
Pack. on SiP
eWLB
Page 8
Trends in Packaging: System-in-Package
Laminate based
BGA
Form Factor
Interconnect Size, Cost
Today
Tomorrow
L
C
Embedded Wafer Level BGA
impedance-matched low loss TLs, integrated
passives (L, C)
Page 9
Outline
Introduction
Package Overview
Thin Small Leadless Package (TSLP)
Embedded Wafer-Level Ball Grid Arry (eWLB)
Through Silicon Vias (TSV)
Experimental Results
Conclusion
Page 10
Package Overview/Evolution
THD through hole
DIP, TO 220
SMD gull wing
SO, QFP
Dual Inline Plastic Package
Small Outline
Quad Flat Package
Pitch: 2.54mm
SMD solder balls
BGA
Ball Grid Array
DSO-Pitch: 1.27mm
Pitch:
SSOP-Pitch:
1.5...1.27...1.0mm
0.65...0.5mm
0.8…0.65...0.5mm
QFP-Pitch.
[0.4…0,3]
0.8...0.65...0.5...0.4mm
SMD leadless
VQFN, TSLP
Very thin Quad Flat No Lead
Thin Small Leadless Package
Pitch:
0.8, 0.65, 0.5 mm
[0,4; staggered lands]
Page 11
Technology Development & Package
Development
Processes
Thinning and Dicing
Die attach
Wire bonding
Flip chip in Package
Molding
Thin film technology
WLP processes
…
Materials&Substrates
Green
Laminate substrates
(xBGA)
Leadframes (TSLP,
UFLGA, VQFN, ...)
Physics of Package
Signal Integrity
RF capability
Heat dissipation
Reliability Physics
FA incl. adhesion
Miniaturisation
Power
Methods/CCN
Leadframe
Packages
Package
Package
Platforms
Platforms
Integration
enabler
System in
Package
QFP
DSO
TSSOP
Leadless
Package
s
QFN
Laminate
WLB
BGA/SGA/LGA
RF-Modules
SG-WLB
PG-eWLB
Co-design
Simulation&Modeling
BDR
Test
KGD
Standards
Page 12
Outline
Introduction
Package Overview
Thin Small Leadless Package (TSLP)
Embedded Wafer-Level Ball Grid Arry (eWLB)
Through Silicon Vias (TSV)
Experimental Results
Conclusion
Page 13
The Leadless Package Concept TSLP
TSLP – Thin Small Leadless Package
Leadless package based on a leadframe concept
Low to medium pin count (< 80 I/Os)
Green package
Wirebond and Flip-Chip capabilities
Main advantages
Small dimensions (few mm)
Short interconnects
Excellent RF capabilities
Improved thermal
performance
Page 14
The Leadless Package Concept TSLP
Die
Au - Layer
Cu Leadframe
NiAu Contact
2a. Flip-Chip Bonding
Ni - Bump
50 µm
1. Die Bonding
2b. Wirebonding
3. Molding
5. Singulation
4. Copper Removal
and Final Plating
6. Electrical TestPage 15
The Leadless Package Concept TSLP
Flexible leadframe concept
Typical padsizes range from 100 µm to 300 µm
Nearly arbitrary pad geometries
¬ Circular
¬ Rectangular
¬ …
Improved thermal performance
Power / GND supply
Page 16
Wirebond Interconnects – Wire Length
Variation
0
-5
-10
-20
-25
-30
0
-35
l = 1000 µm
l = 600 µm
l = 300 µm
-40
-45
-1
-50
0
10
20
Frequency [GHz]
30
-2
40
S21 [dB]
S11 [dB]
-15
-3
-4
l = 1000 µm
l = 600 µm
l = 300 µm
-5
-6
0
10
20
30
40
Frequency [GHz]
Page 17
Wirebond Interconnects – Padsize Variation
0
-20
-30
0
w = 100 µm
w = 200 µm
w = 300 µm
-40
-50
0
20
40
Frequency [GHz]
60
80
-2
S21 [dB]
S11 [dB]
-10
-4
w = 100 µm
w = 200 µm
w = 300 µm
-6
0
20
40
60
80
Frequency [GHz]
Page 18
Flip-Chip Interconnects – Padsize Variation
0
-10
-30
-40
0
w = 300 µm
w = 200 µm
w = 100 µm
-50
-60
0
20
40
Frequency [GHz]
60
-1
80
S21 [dB]
S11 [dB]
-20
-2
w = 300 µm
w = 200 µm
w = 100 µm
-3
0
20
40
60
80
Frequency [GHz]
Page 19
Outline
Introduction
Package Overview
Thin Small Leadless Package (TSLP)
Embedded Wafer-Level Ball Grid Arry (eWLB)
Through Silicon Vias (TSV)
Experimental Results
Conclusion
Page 20
WLB Basic Platforms
Fan-In / Fan-Out
WLB Fan-In
restricted to chip size
WLB Fan-Out (eWLB)
offers fan-out possibility
SG-UFWLB-49
eWLB Test Vehicle
WLB without
WLB with
redistribution layer
WLBs Fan-In are chip size packages
All balls must fit UNDER chip shadow
• Number and pitch of Interconnects
must be adapted to the chip size
• Fan-in WLBs are available on
market
Package design of Fan-Out Package
is INDEPENDENT from chip size:
• Fan-out area adaptable to needs
• No restrictions for ball pitch
• Fan-Out WLB actually strongly in
the focus of the market
: Chip size
: Package size
Page 21
Schematic Process Flow for eWLB Package
M. Brunnbauer, et al., “Embedded Wafer Level
Ball Grid Array (eWLB),” 8th EPTC, Dec. 2006.
Page 22
Transmission Lines in eWLB Techology
CPW
W/S = 87/20 µm
Re Z0 = 49.2 Ω (Mold)
Re Z0 = 42.8 Ω (Si 1-100 Ωcm)
Mold (eWLB)/Si 1-100 Ωcm
TFMSL
W/T = 20/3 µm
H = 10 µm
BCB
Re Z0 = 49.2 Ω (BCB)
MSL
Si 1-100 Ωcm
W/T = 317/35 µm
H = 130 µm
Re Z0 = 46.9 Ω (RO3003)
RO3003
Page 23
Transmission Lines cont.
Measured performance
eWLB
eWLB
Excellent performance of TMLs manufactured in eWLB
Insertion loss 0.1 dB/mm @ 10GHz, 0.25 dB/mm @ 60GHz
Page 24
Transmission Lines cont.
Determination of charactersitic
impedance of the CPW
R ~ √f
Line Parameters RLCG
G ~ ωCtanδ
tanδ = 0.017
(data-sheet = 0.026)
Page 25
Transmission Lines cont.
Separation of the electrical effects of the conductors and dielectrics
where
αC/αD = 90%
αC/αD = 70%
Further improvement of the performance of the
transmission lines by applying low-loss thin-film dielectrics
Page 26
Single-Layer Spiral Inductors
Layout parameters
Measured performance
Page 27
Single-Layer Spiral Inductors cont.
Measured performance
Inductors in eWLB offer significantly better performance
compared to inductors in standard on-chip technologies
Page 28
MIM/Interdigital Inductors
MIM capacitors
Interdigital capacitors
Page 29
MIM/Interdigital Inductors cont.
Measured Performance
Further improvement of the quality factor of the
integrated capacitors by using low-loss thin-film dielectrics
Page 30
Outline
Introduction
Package Overview
Thin Small Leadless Package (TSLP)
Embedded Wafer-Level Ball Grid Arry (eWLB)
Through Silicon Vias (TSV)
Experimental Results
Conclusion
Page 31
More fan out WLBs : Silicon Carrier Concept
Silicon IC Die
µFC interconnect
Metal layer
(Cu)
Via hole
Standard Solder Ball
Dielectric
layer
Macro porous silicon
Passive Si carrier with regular grid of TSV
High integration density (Wafer technology for RDL)
Passive integration of L and C
High reliability interconnects IC and carrier (CTE match)
Low cost concept
(Standard circuit dies, cost optimized carrier concept)
Page 32
Embedded Passives in Si Low Cost Technology
Inductor
Capacitor
Planar L using of
RDL for loops
Si through hole via
for inductor loops
L = 0.5 − 35 nH
Q = 20 − 25
Fres = 1 − 35 GHz
MIM Caps using
RDL for plates
Trench Caps using
Si – trough holes
C = 35pF/mm2
Q = 500 – 2000
Fres= 1-20 GHz
C = 3000pF/mm2
Q < 1000
Fres < 10 GHz
Resistor
No Resistor component in focus due to costs (missing specific material)
Page 33
Coplanar Waveguide (CPW) over TSVs
Measurement
Grounded TSVs
Floating TSVs
HFSS Model
Gnd
Page 34
TFMSL and CPW over Floating TSVs
Influence
of TSVs
Influence of TSVs
Excellent performance of TMLs manufactured in SC
Insertion loss 0.1 dB/mm @ 10GHz, 0.25 dB/mm @ 60GHz
Page 35
Single/Double-Layer Spiral Inductors
Single-layer inductors over floating TSVs
Double-layer inductors over floating TSVs
The inductors in SC offer significantly better performance
compared to inductors in standard on-chip technologies
Page 36
Influence of Floating/Grounded Configuration
Single/double-layer inductors over floating TSVs vs. grounded TSVs
Influence
of TSVs
∆Q = 12
Grounding
of TSVs
Single-layer spiral inductor of L = 2.0 nH
Page 37
3D Spiral Inductor
The low quality factor is caused by the losses for the
currents induced in TSVs distributed around the windings
Page 38
Influence of Floating/Grounded Configuration
3D inductors over floating TSVs vs. grounded TSVs
Influence
of TSVs
∆Q = 15
Grounding
of TSVs
3D spiral inductor of L = 5.6 nH
Page 39
Outline
Introduction
Package Overview
Thin Small Leadless Package (TSLP)
Embedded Wafer-Level Ball Grid Arry (eWLB)
Through Silicon Vias (TSV)
Experimental Results
Conclusion
Page 40
17 GHz WLAN Receiver
Fully assembled in TSLP-24
Package dimensions 3.5 mm x 3.5 mm
Package height 400 µm
Wirebond interconnect technology
Au wirebonds
500 µm wirelength at critical RF output
Approx. 400 pH parasitic inductance
Inductance of the wirebonds used as external impedance
matching network
Page 41
17 GHz WLAN Receiver
Polished cut image
Mold Compound
Chip
Ni-Pad
400 µm
300 µm
Rogers RO4003 Substrate
Evaluation board
Page 42
17 GHz WLAN Receiver
Measured gain
Two-tone measurement
Page 43
80 GHz Voltage Controlled Oscillator
Fully assembled in TSLP-24
Package dimensions 3.5 mm x 3.5 mm
Package height 400 µm
Total power consumption of 2 W
Flip-Chip interconnect technology not possible
Wirebond technology and die-attach to leadframe for
efficient thermal management
Wirebond interconnect technology
Au wirebonds
300 µm wirelength at critical RF output
250 pH parasitic inductance
Page 44
80 GHz Voltage Controlled Oscillator
Page 45
80 GHz Voltage Controlled Oscillator
2.4
2.4 GHz
GHz Output
Output
19.125
19.125 GHz
GHz Output
Output
80
80 GHz
GHz Output
Output
Page 46
80 GHz Voltage Controlled Oscillator
Vss = 5.7 V
Vss = 6 V
(Core temp ≈ 100°C)
(Core temp ≈ 100°C)
VTUNE
fVCO
Output Power
VTUNE
fVCO
Output Power
0V
75.07 GHz
5.45 dBm
0V
74.656 GHz
5.99 dBm
1V
79.136 GHz
5.75 dBm
1V
78.848 GHz
6.11 dBm
2V
80.384 GHz
6.67 dBm
2V
80.128 GHz
6.92 dBm
3V
81.088 GHz
6.4 dBm
3V
80.85 GHz
6.92 dBm
4V
81.536 GHz
5.83 dBm
4V
81.31 GHz
6.47 dBm
5V
81.888 GHz
5.6 dBm
5V
81.664 GHz
6.11 dBm
Page 47
77 GHz SiGe Mixer
Chip size 550 × 550 µm2
Gain G = 21.4 dB @ 77 GHz
Noise Figure NFSSB = 11.8 @ 77 GHz
Page 48
Package Design for 77 GHz SiGe Mixer
Manufactured package family
Package size 2.5 × 1.5 mm²
and 2.0 × 1.5 mm²
Full surface capability
Standard pitch 0.5 mm
Package P1X
extremely short RF and LO
signal paths (about 100 µm)
Package P2X
longer signal paths (about
360 µm)
Three different RDL
metallization profiles
Page 49
77 GHz SiGe Mixer
Gain and Noise Figure Measurements
Page 50
TSV - RF Demonstrator on RF Test Board
Fully functional & fully programmable
RX & TX chain fully functional
VCO locks on all channels
Key RF parameters within spec limit
Spurious performance need improvement
Remark:
No design of application optimization
was done for the Si Carrier Demonstrator
Page 51
TSV - RF Demonstrator : Cross Section
Dimensions: 7,5mm x 8,0 mm
Transceiver
2 Layer RDL
Si Carrier
µ-Bump 50 µm
2st Cu RDL Layer
1st Cu RDL Layer
RDL VIA
Dielectric
Silicon
Cu-Alloy Si-Through
Contacts
Copper
FC Ball 250 µm
Page 52
Outline
Introduction
Package Overview
Thin Small Leadless Package (TSLP)
Embedded Wafer-Level Ball Grid Arry (eWLB)
Through Silicon Vias (TSV)
Experimental Results
Conclusion
Page 53
Conclusion
Thin Small Leadless Package
Low cost solution based on leadframe concept
Suited for low pin count applications
Good RF performance for dedicated applications
Embedded Wafer-Level Ball Grid Array
Excellent RF capabilities
High pin count
Passive device integration capabilities
Through Silicon Vias
High interconnect density
Passive device integration capabilities
Page 54