FET Amplifiers
20v
20v
6.6kΩ
6.6kΩ
vgs
VGS = 5v
+
VDS+vds
0
IDS (mA)
VT0=1.0V
Kp=2e-5 [A/V2]
W=100 microns
L=10 microns
VGS = 5v
10
VDS
+
VDS
-
20
3
VGS=5.0V
2
VGS=4.0V
1
VGS=3.0V
0
VGS=2.0V
VGS=1.0V
Lecture 21-1
FET Amplifiers
20v
RD=6.6kΩ
vgs
VGS = 5v
• A 200mv peak ac input voltage will cause
more than a 1v peak ac output voltage
• What would we change to make the
voltage gain even larger?
0
10
VDS
20
3
VGS=5.2V
IDS (mA)
VGS=5.0V
VGS=4.8V
2
1
v DS = V DD – R D i D
0
~2V
Lecture 21-2
dc Solution of FET Amplifier
• Set the ac source to zero and analyze the dc bias point
• Solution should agree with that from load line approximation
RC
6.6k
IDS1
1.919 mA
VD
L=10E-6
W=100E-6
VGS1
5V
+
-
7.335 V
+
VDD
20V
-+
Lecture 21-3
dc Solution of FET Amplifier
• Response for a 5kHz, 0.2v peak ac input signal
0
2
4
6
8
time
10 e-4s
9
Vout
8
7
6
Vin
5
4
Lecture 21-4
dc Solution of FET Amplifier
• The output signal is somewhat distorted for a 0.4v peak ac input
0
2
4
6
8
time
10 e-4s
10
Vout
9
8
7
6
Vin
5
4
Lecture 21-5
Small Signal Assumption
• The distortion is due to the nonlinear effects when the ac vgs is too large:
bias point equations:
I D = K ( V GS – V t )
ac & dc equations:
v GS = V GS + v gs
2
V D = V DD – R D I D
i D = K ( v GS – V t )
2
Lecture 21-6
Transconductance -- Gain
• The transconductance, gm, for a MOSFET is much smaller than that for a BJT
which uses the same silicon area (BJT approx. 100 times better)
vGS
0
2
4
6
8
10
20
iDS (mA)
gm =
∂i D
∂ v GS
v GS = V GS
10
0
Lecture 21-7
Transconductance -- Gain
• BJT gm’s are independent of area dimensions
• FET gm’s are dependent on channel W and L dimensions
gm =
∂i D
∂ v GS
W
= 2K ( V GS – V t ) = µ n C ox ----- ( V GS – V t )
L
v GS = V GS
Lecture 21-8
Small Signal Voltage Gain
v D = V DD – R D i D = V DD – R D ( I D + i d )
• Under the small signal assumption:
v d = – R D i d = – g m R D v gs
vd
------- = – g m R D
v gs
Lecture 21-9
Small Signal Model
• The small signal model is very similar to that for the BJT amplifier:
D
G
g m v gs
i ds
ro
S
• ro is the drain-source voltage change with change in ids due to channel length
modulation.
Lecture 21-10
Channel Length Modulation
• Given lambda and the bias point, we can calculate ro
• For our example, we can estimate ro from an enlarged view of IDS vs. VDS at
the bias point (with VGS=5v)
VDS
7.0
7.2
7.4
7.6
7.8
8.0
1950
uA
1940
1930
1920
1910
1900
IDS
Lecture 21-11
Small Signal Model
• Short the dc supplies and analyze the small signal equivalent ckt:
20v
G
6.6kΩ
VGS = 5v
vgs
i ds
D
vgs
S
g m v gs
28k
6.6k
Lecture 21-12
Biasing
• Since ID determines gm we’d like to bias the transistor so that the small signal
gain remains as stable as possible with variations in temperature and process
VDD
R G2
V GG = V DD ---------------------------R G1 + R G2
RG1
VGS
0
2
4
6
8
10
20
RG2
IDS
mA
Kp=2e-5
10
Kp=1.6e-5
0
Lecture 21-13
Negative Feedback Resistor
• RS provides negative feedback for unwanted changes in IDS due to process
variations or temperature fluctuations
VDD
RG1
V GG
RG2
RS
Lecture 21-14
Negative Feedback Resistor
• We can get a similar negative feedback effect with a drain to gate bias resistor
• This resistor guarantees that the transistor is biased in the saturation region --
- why?
Find the RD which establishes a 1mA ID
K=0.25mA/V2 VDD=20V
VDD
Vt = 2V
RD
RG
+
_Vin
+
VDS
_
Lecture 21-15
No negative Feedback Resistor
• What is the change in ID for the circuit below if the threshold voltage changes
from 2V to 3V?
20v
16kΩ
VGS = 4v
Lecture 21-16
Negative Feedback Resistor
• But this change is much less with negative feedback control
VDD
RD
RG
+
_Vin
+
VDS
_
Lecture 21-17