VND810-E
DOUBLE CHANNEL HIGH SIDE DRIVER
Table 1. General Features
Type
VND810-E
Figure 1. Package
RDS(on)
Iout
VCC
160 mΩ (*)
3.5A (*)
36 V
)
s
(
ct
(*) Per each channel
CMOS COMPATIBLE INPUTS
■ OPEN DRAIN STATUS OUTPUTS
■ ON STATE OPEN LOAD DETECTION
■ OFF STATE OPEN LOAD DETECTION
■ SHORTED LOAD PROTECTION
■ UNDERVOLTAGE AND OVERVOLTAGE
SHUTDOWN
■ PROTECTION AGAINST LOSS OF GROUND
■ VERY LOW STAND-BY CURRENT
■
REVERSE BATTERY PROTECTION (**)
■ IN COMPLIANCE WITH THE 2002/95/EC
EUROPEAN DIRECTIVE
■
)
(s
u
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s
b
O
t
c
u
DESCRIPTION
The VND810-E is a monolithic device designed in
STMicroelectronics VIPower M0-3 Technology,
intended for driving any kind of load with one side
connected to ground.
Active V CC pin voltage clamp protects the device
against low energy spikes (see ISO7637 transient
compatibility table).
od
r
P
e
SO-16
Active current limitation combined with thermal
shutdown and automatic restart protects the
device against overload. The device detects open
load condition both in on and off state. Output
shorted to VCC is detected in the off state. Device
automatically turns off in case of ground pin
disconnection.
t
e
l
o
s
b
O
Table 2. Order Codes
Package
SO-16
Tube
VND810-E
Tape and Reel
VND810TR-E
Note: (**) See application schematic at page 9
Rev. 1
October 2004
1/20
VND810-E
Figure 2. Block Diagram
Vcc
Vcc
CLAMP
OVERVOLTAGE
UNDERVOLTAGE
GND
CLAMP 1
OUTPUT1
INPUT1
DRIVER 1
CLAMP 2
STATUS1
CURRENT LIMITER 1
)
s
(
ct
DRIVER 2
LOGIC
OVERTEMP. 1
OUTPUT2
OPENLOAD ON 1
u
d
o
CURRENT LIMITER 2
INPUT2
OPENLOAD OFF 1
OPENLOAD ON 2
r
P
e
STATUS2
OPENLOAD OFF 2
t
e
l
o
OVERTEMP. 2
Table 3. Absolute Maximum Ratings
Symbol
)-
s
(
t
c
DC Supply Voltage
VCC
Value
Unit
41
V
- VCC
Reverse DC Supply Voltage
- 0.3
V
- IGND
DC Reverse Ground Pin Current
- 200
mA
Pr
Internally Limited
A
-6
A
DC Input Current
+/- 10
mA
DC Status Current
+/- 10
mA
4000
V
4000
V
5000
V
5000
V
(L=1.5mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC;
IL=5A)
26
mJ
Power Dissipation TC=25°C
8.3
W
Internally Limited
°C
u
d
o
IOUT
DC Output Current
- IOUT
Istat
o
s
b
VESD
Reverse DC Output Current
e
t
e
l
IIN
O
Parameter
s
b
O
Electrostatic Discharge
R=1.5KΩ; C=100pF)
(Human
Body
Model:
- INPUT
- STATUS
- OUTPUT
- VCC
Maximum Switching Energy
EMAX
Ptot
Tj
Junction Operating Temperature
Tc
Case Operating Temperature
- 40 to 150
°C
Storage Temperature
- 55 to 150
°C
Tstg
2/20
VND810-E
Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins
VCC
1
VCC
16
VCC
N.C.
GND
OUTPUT 1
INPUT 1
OUTPUT 1
STATUS 1
STATUS 2
OUTPUT 2
OUTPUT 2
VCC
INPUT 2
VCC
8
Connection / Pin Status
Floating
X
To Ground
VCC
9
N.C.
X
X
Output
X
Input
X
Through 10KΩ resistor
u
d
o
r
P
e
Figure 4. Current and Voltage Conventions
t
e
l
o
IIN1
)
(s
INPUT 1
ISTAT1
VIN1
s
b
O
STATUS 1
IIN2
VSTAT1
ct
du
o
r
P
e
t
e
l
VF1 (*)
VCC
IOUT1
OUTPUT 1
VOUT1
IOUT2
OUTPUT 2
VSTAT2
IS
VCC
INPUT 2
VIN2 ISTAT2
STATUS 2
)
s
(
ct
VOUT2
GND
IGND
o
s
b
O
(*) VFn = VCCn - VOUTn during reverse battery condition
Table 4. Thermal Data
Symbol
Rthj-lead
Rthj-amb
Parameter
Thermal Resistance Junction-lead
Thermal Resistance Junction-ambient
Value
15
77 (1)
57 (2)
Unit
°C/W
°C/W
Note: 1. When mounted on a standard single-sided FR-4 board with 0.5cm 2 of Cu (at least 35µm thick) connected to all V CC pins. Horizontal
mounting and no artificial air flow.
Note: 2. When mounted on a standard single-sided FR-4 board with 4cm2 of Cu (at least 35µm thick) connected to all VCC pins. Horizontal
mounting and no artificial air flow.
3/20
VND810-E
ELECTRICAL CHARACTERISTICS
(8V<VCC<36V; -40°C < Tj <150°C, unless otherwise specified)
(Per each channel)
Table 5. Power Output
Symbol
Parameter
VCC (**)
Test Conditions
Min.
Typ.
Max.
Unit
Operating Supply Voltage
5.5
13
36
V
VUSD (**)
Undervoltage Shut-down
3
4
5.5
V
VOV (**)
Overvoltage Shut-down
36
On State Resistance
RON
IS (**)
Supply Current
V
IOUT=1A; Tj=25°C
160
IOUT=1A; VCC>8V
320
mΩ
40
ct
µA
25
µA
7
mA
50
µA
0
µA
5
µA
3
µA
Off State; VCC=13V; VIN=VOUT=0V
12
Off State; VCC=13V; VIN=VOUT=0V;
Tj=25°C
12
IL(off1)
Off State Output Current
VIN=VOUT=0V
IL(off2)
Off State Output Current
VIN=0V; VOUT =3.5V
IL(off3)
Off State Output Current
VIN=VOUT=0V; VCC=13V; Tj =125°C
IL(off4)
Off State Output Current
VIN=VOUT=0V; VCC=13V; Tj =25°C
Note: (**) Per device.
)
(s
Table 6. Protection (see note 1)
Symbol
Parameter
TTSD
Shut-down Temperature
Thyst
Thermal Hysteresis
tSDL
Status Delay in Overload
Conditions
Ilim
o
s
b
e
t
e
l
Vdemag
O
o
r
P
Current limitation
Turn-off Output Clamp
Voltage
P
e
t
e
l
o
-75
s
b
O
ct
du
Reset Temperature
5
0
Test Conditions
TR
du
ro
On State; VCC=13V; VIN=5V; IOUT=0A
(s)
Min.
Typ.
Max.
Unit
150
175
200
°C
135
7
°C
15
Tj>TTSD
3.5
5
5.5V<VCC<36V
IOUT =1A; L=6mH
mΩ
VCC41
VCC-48
°C
20
µs
7.5
A
7.5
A
VCC55
V
Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be
used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration
and number of activation cycles
Table 7. VCC - Output Diode
Symbol
VF
4/20
Parameter
Forward on Voltage
Test Conditions
-IOUT =0.5A; Tj=150°C
Min
Typ
Max
0.6
Unit
V
VND810-E
ELECTRICAL CHARACTERISTICS (continued)
Table 8. Status Pin
Symbol
VSTAT
ILSTAT
CSTAT
Parameter
Test Conditions
Status Low Output Voltage ISTAT = 1.6 mA
Status Leakage Current
Normal Operation; VSTAT= 5V
Status Pin Input
Normal Operation; VSTAT= 5V
Capacitance
ISTAT = 1mA
Status Clamp Voltage
ISTAT = - 1mA
VSCL
Min
6
Typ
6.8
Max
0.5
10
Unit
V
µA
100
pF
8
-0.7
Table 9. Switching (V CC=13V)
Symbol
Parameter
td(on)
Turn-on Delay Time
td(off)
Turn-off Delay Time
Test Conditions
RL=13Ω from VIN rising edge to
VOUT =1.3V
RL=13Ω from VIN falling edge to
VOUT =11.7V
dVOUT /dt(on) Turn-on Voltage Slope
RL=13Ω from VOUT=1.3V to
VOUT =10.4V
dVOUT /dt(off) Turn-off Voltage Slope
RL=13Ω from VOUT=11.7V to
VOUT =1.3V
Table 10. Openload Detection
Symbol
IOL
Parameter
Openload ON State
Detection Threshold
Openload ON State
VOL
Detection Delay
Openload OFF State
Voltage Detection
Threshold
Openload Detection Delay
at Turn Off
e
t
e
l
tDOL(off)
o
s
b
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r
P
s
b
O
Test Conditions
s
(
t
c
du
tDOL(on)
)-
e
t
e
ol
VIN=5V
Min
Typ
30
o
r
P
See
relative
diagram
See
relative
diagram
Unit
µs
µs
V/µs
V/µs
Min
Typ
Max
Unit
20
40
80
mA
200
µs
3.5
V
1000
µs
Max
1.25
Unit
V
µA
V
µA
V
V
IOUT=0A
VIN=0V
)
s
(
t
Max
c
u
d
30
V
V
1.5
2.5
Table 11. Logic Input
O
Symbol
VIL
IIL
VIH
IIH
VI(hyst)
VICL
Parameter
Input Low Level
Low Level Input Current
Input High Level
High Level Input Current
Input Hysteresis Voltage
Input Clamp Voltage
Test Conditions
VIN = 1.25V
Min
Typ
1
3.25
VIN = 3.25V
IIN = 1mA
IIN = -1mA
10
0.5
6
6.8
-0.7
8
V
5/20
VND810-E
Figure 5.
OPEN LOAD STATUS TIMING (with external pull-up)
VOUT> VOL
OVERTEMP STATUS TIMING
IOUT < IOL
Tj > TTSD
VINn
VINn
VSTAT n
VSTAT n
tSDL
tDOL(off)
)
s
(
ct
tDOL(on)
Table 12. Truth Table
CONDITIONS
INPUT
OUTPUT
Normal Operation
L
H
L
H
Current Limitation
L
H
H
Overtemperature
L
H
Undervoltage
L
H
Overvoltage
Output Voltage > VOL
let
o
s
b
O
6/20
ete
u
d
o
Pr
SENSE
H
H
l
o
s
H
(Tj < TTSD) H
(Tj > TTSD) L
L
L
H
L
L
L
X
X
L
L
H
H
L
H
H
H
L
H
L
H
L
H
H
L
)
(s
t
c
u
d
o
r
P
e
Output Current < IOL
tSDL
L
H
b
O
L
X
X
VND810-E
Figure 6. Switching Time Waveforms
VOUTn
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
10%
)
s
(
t
t
VINn
td(on)
c
u
d
td(off)
e
t
e
ol
)
(s
o
r
P
t
s
b
O
Table 13. Electrical Transient Requirements On V CC Pin
ISO T/R 7637/1
1
2
3a
3b
4
5
ISO T/R 7637/1
Test Pulse
1
2
3a
3b
4
5
CLASS
C
E
od
-25 V
+25 V
-25 V
+25 V
-4 V
+26.5 V
r
P
e
t
e
l
o
s
b
O
t
c
u
I
Test Pulse
I
C
C
C
C
C
C
II
TEST LEVELS
III
IV
-50 V
+50 V
-50 V
+50 V
-5 V
+46.5 V
-75 V
+75 V
-100 V
+75 V
-6 V
+66.5 V
-100 V
+100 V
-150 V
+100 V
-7 V
+86.5 V
TEST LEVELS RESULTS
II
III
C
C
C
C
C
C
C
C
C
C
E
E
Delays and
Impedance
2 ms 10 Ω
0.2 ms 10 Ω
0.1 µs 50 Ω
0.1 µs 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
IV
C
C
C
C
C
E
CONTENTS
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device is not performed as designed after exposure and cannot be
returned to proper operation without replacing the device.
7/20
VND810-E
Figure 7. Waveforms
NORMAL OPERATION
INPUTn
OUTPUT VOLTAGEn
STATUSn
)
s
(
ct
UNDERVOLTAGE
VCC
VUSDhyst
VUSD
u
d
o
INPUTn
OUTPUT VOLTAGEn
STATUSn
t
e
l
o
OVERVOLTAGE
VCC<VOV
VCC
INPUTn
OUTPUT VOLTAGEn
STATUSn
)
(s
t
c
u
VCC>VOV
s
b
O
OPEN LOAD with external pull-up
d
o
r
INPUTn
OUTPUT VOLTAGEn
P
e
STATUSn
t
e
l
o
bs
O
VOUT>VOL
VOL
OPEN LOAD without external pull-up
INPUTn
OUTPUT VOLTAGEn
STATUSn
OVERTEMPERATURE
Tj
TTSD
TR
INPUTn
OUTPUT CURRENTn
STATUSn
8/20
r
P
e
undefined
VND810-E
Figure 8. Application Schematic
+5V +5V
+5V
VCC
Rprot
STATUS1
Dld
µC
Rprot
INPUT1
)
s
(
ct
OUTPUT1
Rprot
STATUS2
Rprot
u
d
o
r
P
e
INPUT2
let
GND
o
s
b
RGND
VGND
OUTPUT2
DGND
O
)
GND PROTECTION
REVERSE BATTERY
u
d
o
s
(
t
c
NETWORK
r
P
e
AGAINST
Solution 1: Resistor in the ground line (RGND only). This
can be used with any type of load.
The following is an indication on how to dimension the
RGND resistor.
1) RGND ≤ 600mV / IS(on)max.
2) RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can
be found in the absolute maximum rating section of the
device’s datasheet.
Power Dissipation in RGND (when VCC<0: during reverse
battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
calculated with formula (1) where IS(on)max becomes the
sum of the maximum on-state currents of the different
devices.
Please note that if the microprocessor ground is not
common with the device ground then the RGND will
produce a shift (IS(on)max * RGND) in the input thresholds
and the status output values. This shift will vary
depending on how many devices are ON in the case of
several high side drivers sharing the same RGND.
s
b
O
t
e
l
o
If the calculated power dissipation leads to a large
resistor or several devices have to share the same
resistor then the ST suggests to utilize Solution 2 (see
below).
Solution 2: A diode (DGND) in the ground line.
A resistor (RGND=1kΩ) should be inserted in parallel to
DGND if the device will be driving an inductive load.
This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
the ground network will produce a shift (j600mV) in the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
Series resistor in INPUT and STATUS lines are also
required to prevent that, during battery voltage transient,
the current exceeds the Absolute Maximum Rating.
Safest configuration for unused INPUT and STATUS pin
is to leave them unconnected.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds VCC max DC rating.
The same applies if the device will be subject to
transients on the VCC line that are greater than the ones
shown in the ISO T/R 7637/1 table.
9/20
VND810-E
µC I/Os PROTECTION:
positive supply voltage (VPU) like the +5V line used to
supply the microprocessor.
The external resistor has to be selected according to the
following requirements:
1) no false open load indication when load is connected:
in this case we have to avoid VOUT to be higher than
VOlmin; this results in the following condition
VOUT=(VPU/(RL+RPU))RL<VOlmin.
2) no misdetection when load is disconnected: in this
case the VOUT has to be higher than VOLmax; this
results in the following condition RPU<(VPU–VOLmax)/
IL(off2).
Because Is(OFF) may significantly increase if Vout is
pulled high (up to several mA), the pull-up resistor RPU
should be connected to a supply that is switched OFF
when the module is in standby.
The values of VOLmin, VOLmax and IL(off2) are available in
the Electrical Characteristics section.
If a ground protection network is used and negative
transient are present on the VCC line, the control pins will
be pulled negative. ST suggests to insert a resistor (Rprot)
in line to prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between
the leakage current of µC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up
limit of µC I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 65kΩ.
Recommended Rprot value is 10kΩ.
)
s
(
ct
OPEN LOAD DETECTION IN OFF STATE
u
d
o
Off state open load detection requires an external pull-up
resistor (RPU) connected between OUTPUT pin and a
r
P
e
Figure 9. Open Load detection in off state
t
e
l
o
s
b
O
V batt.
VPU
VCC
INPUT
so
let
b
O
10/20
STATUS
RPU
t
c
u
d
o
r
P
e
)
(s
DRIVER
+
LOGIC
IL(off2)
OUT
+
R
VOL
GROUND
RL
VND810-E
Figure 13. High Level Input Current
Figure 10. Off State Output Current
IL(off1) (uA)
Iih (uA)
1.6
5
1.44
4.5
Off state
Vcc=36V
Vin=Vout=0V
1.28
1.12
Vin=3.25V
4
3.5
0.96
3
0.8
2.5
0.64
2
0.48
1.5
0.32
1
0.16
0.5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (ºC)
8
Iin=1mA
bs
7.6
0.04
7.4
7.2
)
s
(
ct
7
6.8
6.6
du
-25
0
25
e
t
e
ol
o
r
P
50
75
100
125
175
125
150
175
125
150
175
u
d
o
-O
Vstat=5V
0.03
0.02
0.01
0
150
175
-50
-25
0
25
Tc (°C)
50
75
100
Tc (°C)
Figure 12. Status Low Output Voltage
s
b
O
150
t
e
l
o
0.05
6.4
125
r
P
e
Ilstat (uA)
7.8
-50
100
Figure 14. Status Leakage Current
Vicl (V)
6
75
Tc (°C)
Figure 11. Input Clamp Voltage
6.2
50
)
s
(
ct
Figure 15. Status Clamp Voltage
Vstat (V)
Vscl (V)
0.8
8
7.8
0.7
Istat=1mA
Istat=1.6mA
7.6
0.6
7.4
0.5
7.2
0.4
7
6.8
0.3
6.6
0.2
6.4
0.1
6.2
0
6
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
-50
-25
0
25
50
75
100
Tc (°C)
11/20
VND810-E
Figure 16. On State Resistance Vs Tcase
Figure 19. On State Resistance Vs VCC
Ron (mOhm)
Ron (mOhm)
400
300
275
350
Iout=0.5A
250
Iout=0.5A
Vcc=8V; 13V & 36V
300
Tc= 150°C
225
250
200
175
200
150
150
Tc= 25°C
125
100
100
75
0
50
-50
-25
0
25
50
75
100
125
150
175
5
10
15
20
Tc (°C)
5
55
4.5
4
O
)
45
40
s
(
t
c
35
30
u
d
o
15
10
-50
-25
0
25
e
t
e
ol
Pr
50
75
100
125
40
t
e
l
o
bs
Vcc=13V
Vin=5V
20
u
d
o
35
r
P
e
Vol (V)
60
25
30
Figure 20. Openload Off State Detection
Threshold
Iol (mA)
50
25
Vcc (V)
Figure 17. Openload On State Detection
Threshold
Vin=0V
3.5
3
2.5
2
1.5
1
0.5
0
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
100
125
150
175
Tc (°C)
Figure 18. Input High Level
Figure 21. Input Low Level
s
b
O
Vih (V)
Vil (V)
3.6
2.6
3.4
2.4
3.2
2.2
3
2
2.8
1.8
2.6
1.6
2.4
1.4
2.2
1.2
2
1
-50
-25
0
25
50
75
Tc (°C)
12/20
)
s
(
ct
Tc= - 40°C
50
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
VND810-E
Figure 22. Input Hysteresis Voltage
Figure 25. Overvoltage Shutdown
Vhyst (V)
Vov (V)
1.5
50
1.4
48
1.3
46
1.2
44
1.1
42
1
40
0.9
38
0.8
36
0.7
34
0.6
32
0.5
30
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
1000
500
900
450
Vcc=13V
Rl=13Ohm
700
350
600
)-
500
s
(
t
c
400
300
du
-50
-25
0
o
r
P
25
e
t
e
ol
50
75
u
d
o
100
150
175
125
150
175
t
e
l
o
s
b
O
400
200
125
r
P
e
dVout/dt(off) (V/ms)
0
100
Figure 26. Turn-off Voltage Slope
dVout/dt(on) (V/ms)
100
75
Tc (°C)
Figure 23. Turn-on Voltage Slope
800
50
)
s
(
ct
Vcc=13V
Rl=13Ohm
300
250
200
150
100
50
0
150
175
Tc (ºC)
-50
-25
0
25
50
75
100
125
Tc (ºC)
Figure 24. ILIM Vs Tcase
s
b
O
Ilim (A)
10
9
Vcc=13V
8
7
6
5
4
3
2
1
0
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
13/20
VND810-E
Figure 27. Maximum turn off current versus load inductance
ILMAX (A)
10
A
)
s
(
ct
u
d
o
B
r
P
e
C
1
0.1
1
)
(s
t
c
u
A = Single Pulse at TJstart=150ºC
B= Repetitive pulse at T Jstart=100ºC
C= Repetitive Pulse at T Jstart=125ºC
od
r
P
e
t
e
l
o
Conditions:
VCC=13.5V
t
e
l
o
s
b
OL(mH)
10
100
Values are generated with R L=0Ω
In case of repetitive pulses, Tjstart (at beginning of
each demagnetization) of every pulse must not
exceed the temperature specified above for
curves B and C.
s
b
O
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
14/20
VND810-E
PowerSO-10™ Thermal Data
Figure 28. SO-16 PC Board
)
s
(
ct
u
d
o
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=1.6mm,
Cu thickness=35µm, Copper areas: 0.26cm2, 4cm2).
r
P
e
t
e
l
o
Figure 29. Rthj-amb Vs PCB copper area in open box free air condition
)
(s
RTH j-am b
(°C/W)
85
s
b
O
t
c
u
80
d
o
r
75
P
e
t
e
l
o
O
bs
70
65
60
55
50
45
40
0
1
2
3
4
5
PCB Cu heatsink area (cm^2)
15/20
VND810-E
Figure 30. SO-16 Thermal Impedance Junction Ambient Single Pulse
ZTH (°C/W)
1000
100
0.26 cm2
4 cm2
)
s
(
ct
10
u
d
o
1
r
P
e
t
e
l
o
0.1
0.01
0.0001
0.001
)-
0.01
0.1
1
Time (s)
s
(
t
c
u
d
o
Figure 31. Thermal fitting model of a double
channel HSD in SO-16
e
t
e
l
so
b
O
Tj_1
Pr
C2
C3
C4
C5
C6
R1
R2
R3
R4
R5
R6
C2
R1
R2
Pd2
T_amb
16/20
100
1000
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
δ = tp ⁄ T
Table 14. Thermal Parameter
C1
C1
10
Pulse calculation formula
where
Pd1
Tj_2
s
b
O
R1
R2
R3
R4
R5
R6
C1
C2
C3
C4
C5
C6
Area/island (cm2)
(°C/W)
(°C/W)
( °C/W)
(°C/W)
(°C/W)
(°C/W)
(W.s/°C)
(W.s/°C)
(W.s/°C)
(W.s/°C)
(W.s/°C)
(W.s/°C)
0.5
0.35
1.8
4.5
10
16
48
0.0001
7.00E-04
6.00E-03
0.2
0.7
2
4
25
4
VND810-E
PACKAGE MECHANICAL
Table 15. SO-16 Mechanical Data
millimeters
Symbol
Min
A
a1
a2
b
b1
C
c1
D
E
e
e3
F
G
L
M
S
Typ
Max
1.75
0.2
1.65
0.46
0..25
0.1
0.35
0.19
0.5
45° (typ.)
)
s
(
ct
9.8
5.8
10
6.2
1.27
8.89
3.8
4.6
0.5
8° (max.)
4.0
5.3
1.27
0.62
t
e
l
o
Figure 32. SO-16 Package Dimensions
)
(s
r
P
e
u
d
o
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
17/20
VND810-E
Figure 33. SO-16 Suggested Pad Layout And Tube Shipment (no suffix)
B
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
A
50
1000
532
3.2
6
0.6
All dimensions are in mm.
)
s
(
ct
u
d
o
Figure 34. Tape And Reel Shipment (suffix “TR”)
r
P
e
REEL DIMENSIONS
.All dimensions are in mm.
let
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
o
s
b
O
)
s
(
t
c
u
d
o
r
P
e
TAPE DIMENSIONS
1000
1000
330
1.5
13
20.2
16.4
60
22.4
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
t
e
l
o
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
s
b
O
W
P0 (± 0.1)
P
D (± 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
16
4
8
1.5
1.5
7.5
6.5
2
End
All dimensions are in mm.
Start
Top
No components
Components
No components
cover
tape
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
18/20
500mm min
VND810-E
REVISION HISTORY
Date
Oct. 2004
Revision
1
- First Issue
Description of Changes
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
19/20
VND810-E
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
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20/20