Xilinx XTP067 - SP605 Schematics
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4 3 DDR3 2 FMC LPC Expansion Connector Page 9 Disclaimer: 10/100/1000 Ethernet GMII Page 10 1 THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS")ARE SUBJECT TO THE Page 11 AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE D OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED D ON THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY OR PROPER OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Differential Clock Clock Socket SMA Clock Page 14 System ACE CF Page 20 12V PWR Jack Spartan-6 LEDs Power Supply Parallel Flash C Page 14 C Linear Regulator 5.0V@1.5A max Page 19 XC6SLX45T Linear Regulator 3.0V@500mA max DIP Switches U1 SSPI Header Page 14 Page 18 Power Controller 1 Switching Module VCCINT@10A max Push Buttons SPI X4 or External Config Page 14 Switching Module 2.5V@10A max Page 18 SFP Module Linear Regulator 1.8V@500mA max PCIe Finger Page 12 Page 12 Switching Module VCCAUX@10A max B B Linear Regulator 1.2V @ 3A max Power Controller 2 IIC EEPROM and Header MODE DIP Switch USB UART Page 18 Page 15 USB JTAG Connector Switching Module 1.5V@20A max Page 32 Page 15 Switching Module 3.3V@20A max Sink/Source DDR Regulator 0.75V VTT / VREF @ 3A max JTAG Chain J19 3.3V IIC Addressing 2.5V J4 USB HDR FMC LPC A BUFFER TDI System ACE CF TDO TSTTDI CFGTDO FPGA TDI U17 U1 CFGTDI TDO 0b1010100 EEPROM: 0b1010010 J2 TSTTDO U4 J2 Title: Other Devices: 0bXXXXX10 SP605 Block Diagram SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM Sheet Size: B Sheet 4 3 2 1 of 0431534 0381305 TSS0123 1280473 A 9-25-2009_10:32 Date: PCB P/N: SCH P/N: Test P/N: ART P/N: Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 D D DUT BANK 0 6slx45tfg484 IO_L66N_SCP0_0_C18 IO_L66P_SCP1_0_D17 IO_L65N_SCP2_0_A20 IO_L65P_SCP3_0_B20 IO_L64N_SCP4_0_A19 IO_L64P_SCP5_0_C19 IO_L63N_SCP6_0_A18 IO_L63P_SCP7_0_B18 IO_L62N_VREF_0_D19 IO_L62P_0_D18 IO_L51N_0_F17 IO_L51P_0_G16 IO_L50N_0_A17 IO_L50P_0_C17 IO_L49N_0_G15 IO_L49P_0_H14 IO_L38N_VREF_0_G13 IO_L38P_0_H13 IO_L37N_GCLK12_0_F16 IO_L37P_GCLK13_0_E16 IO_L36N_GCLK14_0_F15 IO_L36P_GCLK15_0_F14 IO_L35N_GCLK16_0_G11 IO_L35P_GCLK17_0_H12 IO_L34N_GCLK18_0_F10 IO_L34P_GCLK19_0_G9 IO_L33N_0_H11 IO_L33P_0_H10 IO_L32N_0_F9 IO_L32P_0_G8 IO_L8N_VREF_0_A5 IO_L8P_0_C5 IO_L7N_0_F8 IO_L7P_0_F7 IO_L6N_0_A4 IO_L6P_0_C4 IO_L5N_0_A3 IO_L5P_0_B3 IO_L4N_0_E6 IO_L4P_0_E5 IO_L3N_0_A2 IO_L3P_0_B2 IO_L2N_0_D5 IO_L2P_0_D4 IO_L1N_VREF_0_D3 IO_L1P_HSWAPEN_0_C3 C VCC2V5_FPGA G14 G10 F6 E17 B4 B19 B VCCO_0_G14 VCCO_0_G10 VCCO_0_F6 VCCO_0_E17 VCCO_0_B4 VCCO_0_B19 C18 D17 A20 B20 A19 C19 A18 B18 D19 D18 F17 G16 A17 C17 G15 H14 G13 H13 F16 E16 F15 F14 G11 H12 F10 G9 H11 H10 F9 G8 A5 C5 F8 F7 A4 C4 A3 B3 E6 E5 A2 B2 D5 D4 D3 C3 GPIO_SWITCH_0 GPIO_LED_0 FMC_LA08_N FMC_LA08_P FMC_LA04_N FMC_LA04_P FMC_LA03_N FMC_LA03_P FMC_LA15_N FMC_LA15_P FMC_LA13_N FMC_LA13_P FMC_LA14_N FMC_LA14_P FMC_LA11_N FMC_LA11_P FMC_LA12_N FMC_LA12_P FMC_CLK1_M2C_N FMC_CLK1_M2C_P FMC_LA01_CC_N FMC_LA01_CC_P FMC_CLK0_M2C_N FMC_CLK0_M2C_P FMC_LA00_CC_N FMC_LA00_CC_P FMC_LA10_N FMC_LA10_P FMC_LA02_N FMC_LA02_P FMC_LA16_N FMC_LA16_P FMC_LA09_N FMC_LA09_P FMC_LA05_N FMC_LA05_P USER_SMA_GPIO_N USER_SMA_GPIO_P IIC_SDA_SFP IIC_SCL_SFP FMC_LA07_N FMC_LA07_P FMC_LA06_N FMC_LA06_P PMBUS_ALERT FPGA_HSWAPEN 14 14 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 13 13 12 12 10 10 10 10 21,26 C B 1 2 R125 100 5% 1/16W U1 FPGA Bank 0 Title: A FPGA Bank 0 SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM Sheet Size: B Sheet 4 3 2 2 of 0431534 0381305 TSS0123 1280473 A 9-18-2009_15:04 Date: PCB P/N: SCH P/N: Test P/N: ART P/N: Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 DUT BANK 1 6slx45tfg484 IO_L74N_DOUT_BUSY_1_V20 IO_L74P_AWAKE_1_V19 IO_L73N_1_T18 IO_L73P_1_T19 IO_L72N_1_T17 IO_L72P_1_R17 IO_L71N_1_P18 IO_L71P_1_P17 IO_L70N_1_R16 IO_L70P_1_R15 IO_L61N_1_M18 IO_L61P_1_M17 IO_L60N_1_P16 IO_L60P_1_N16 IO_L59N_1_T20 IO_L59P_1_U19 IO_L58N_1_N15 IO_L58P_1_M16 IO_L53N_VREF_1_R19 IO_L53P_1_P19 IO_L52N_M1DQ15_1_Y22 IO_L52P_M1DQ14_1_Y21 IO_L51N_M1DQ13_1_W22 IO_L51P_M1DQ12_1_W20 IO_L50N_M1UDQSN_1_V22 IO_L50P_M1UDQS_1_V21 IO_L49N_M1DQ11_1_U22 IO_L49P_M1DQ10_1_U20 IO_L48N_M1DQ9_1_T22 IO_L48P_HDC_M1DQ8_1_T21 IO_L47N_LDC_M1DQ1_1_R22 IO_L47P_FWE_B_M1DQ0_1_R20 IO_L46N_FOE_B_M1DQ3_1_P22 IO_L46P_FCS_B_M1DQ2_1_P21 IO_L45N_A0_M1LDQSN_1_N22 IO_L45P_A1_M1LDQS_1_N20 IO_L44N_A2_M1DQ7_1_M22 IO_L44P_A3_M1DQ6_1_M21 IO_L43N_GCLK4_M1DQ5_1_L22 IO_L43P_GCLK5_M1DQ4_1_L20 IO_L42N_GCLK6_M1LDM_1_N19 IO_L42P_GCLK7_M1UDM_1_P20 IO_L41N_GCLK8_M1CASN_1_K22 IO_L41P_GCLK9_M1RASN_1_K21 IO_L40N_GCLK10_M1A6_1_M19 IO_L40P_GCLK11_M1A5_1_M20 IO_L39N_M1ODT_1_J22 IO_L39P_M1A3_1_J20 IO_L38N_A4_M1CLKN_1_L19 IO_L38P_A5_M1CLK_1_K20 IO_L37N_A6_M1A1_1_H22 IO_L37P_A7_M1A0_1_H21 IO_L36N_A8_M1BA1_1_L17 IO_L36P_A9_M1BA0_1_K17 IO_L35N_A10_M1A2_1_G22 IO_L35P_A11_M1A7_1_G20 IO_L34N_A12_M1BA2_1_K18 IO_L34P_A13_M1WE_1_K19 IO_L33N_A14_M1A4_1_H20 IO_L33P_A15_M1A10_1_J19 IO_L32N_A16_M1A9_1_E22 IO_L32P_A17_M1A8_1_E20 IO_L31N_A18_M1A12_1_F22 IO_L31P_A19_M1CKE_1_F21 IO_L30N_A20_M1A11_1_H19 IO_L30P_A21_M1RESET_1_H18 IO_L29N_A22_M1A14_1_F20 IO_L29P_A23_M1A13_1_G19 IO_L28N_VREF_1_D22 IO_L28P_1_D21 IO_L21N_1_K16 IO_L21P_1_L15 IO_L20N_1_C22 IO_L20P_1_C20 IO_L19N_1_J17 IO_L19P_1_J16 IO_L10N_1_B22 IO_L10P_1_B21 IO_L9N_1_H17 IO_L9P_1_H16 IO_L1N_A24_VREF_1_F19 IO_L1P_A25_1_F18 D C B VCC2V5_FPGA W21 U18 R21 N18 L21 L16 J18 G21 E19 C21 VCCO_1_W21 VCCO_1_U18 VCCO_1_R21 VCCO_1_N18 VCCO_1_L21 VCCO_1_L16 VCCO_1_J18 VCCO_1_G21 VCCO_1_E19 VCCO_1_C21 V20 V19 T18 T19 T17 R17 P18 P17 R16 R15 M18 M17 P16 N16 T20 U19 N15 M16 R19 P19 Y22 Y21 W22 W20 V22 V21 U22 U20 T22 T21 R22 R20 P22 P21 N22 N20 M22 M21 L22 L20 N19 P20 K22 K21 M19 M20 J22 J20 L19 K20 H22 H21 L17 K17 G22 G20 K18 K19 H20 J19 E22 E20 F22 F21 H19 H18 F20 G19 D22 D21 K16 L15 C22 C20 J17 J16 B22 B21 H17 H16 F19 F18 PHY_MDIO FPGA_AWAKE FLASH_WAIT FLASH_ADV_B SFP_LOS DVI_D11 DVI_D10 DVI_D9 DVI_D8 DVI_D7 DVI_D6 DVI_D5 DVI_D4 DVI_D3 DVI_D2 DVI_D1 PHY_CRS PHY_COL PHY_MDC PHY_RXD0 PHY_RXD1 PHY_RXD2 PHY_RXD3 PHY_RXD4 PHY_RXD5 PHY_RXD6 PHY_RXD7 PHY_RXER PHY_RXCTL_RXDV IIC_SCL_MAIN IIC_SDA_MAIN FLASH_WE_B FLASH_OE_B FLASH_CE_B FLASH_A0 FLASH_A1 FLASH_A2 FLASH_A3 NC PHY_TXCLK CLK_33MHZ_SYSACE PHY_RXCLK SYSCLK_N SYSCLK_P USER_SMA_CLOCK_N USER_SMA_CLOCK_P PHY_RESET PHY_INT FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_A22 FLASH_A23 DVI_GPIO1 GPIO_LED_2 DVI_D0 DVI_RESET_B DVI_XCLK_N DVI_XCLK_P DVI_DE DVI_H DVI_V USB_1_RX USB_1_TX PMBUS_CTRL USB_1_RTS USB_1_CTS 11 18 19 19 12 17 17 17 17 17 17 17 17 17 17 17 11 11 11 11 11 11 11 11 11 11 11 11 11 10,15 10,15 19 19 19 19 19 19 19 11 20 11 14 14 13 13 11 11 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 17 14 17 17 17 17 17 17 17 15 15 21,26 15 15 D C B FPGA Bank 1 Title: A FPGA Bank 1 SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM Sheet Size: B Sheet U1 4 3 2 3 of 0431534 0381305 TSS0123 1280473 A 9-18-2009_15:04 Date: PCB P/N: SCH P/N: Test P/N: ART P/N: Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 DUT BANK 2 6slx45tfg484 IO_L65N_CSO_B_2_AA3 IO_L65P_INIT_B_2_Y4 IO_L64N_D9_2_U6 IO_L64P_D8_2_T7 IO_L63N_2_AB4 IO_L63P_2_AA4 IO_L62N_D6_2_AB5 IO_L62P_D5_2_Y5 IO_L60N_2_Y6 IO_L60P_2_W6 IO_L59N_2_R8 IO_L59P_2_R9 IO_L58N_2_W8 IO_L58P_2_V7 IO_L57N_2_U8 IO_L57P_2_T8 IO_L50N_2_V9 IO_L50P_2_U9 IO_L49N_D4_2_AB6 IO_L49P_D3_2_AA6 IO_L48N_RDWR_B_VREF_2_Y8 IO_L48P_D7_2_W9 IO_L47N_2_AB7 IO_L47P_2_Y7 IO_L46N_2_U10 IO_L46P_2_T10 IO_L45N_2_AB8 IO_L45P_2_AA8 IO_L44N_2_Y10 IO_L44P_2_W10 IO_L43N_2_AB9 IO_L43P_2_Y9 IO_L42N_2_W11 IO_L42P_2_V11 IO_L41N_VREF_2_AB10 IO_L41P_2_AA10 IO_L40N_2_Y12 IO_L40P_2_W12 IO_L32N_GCLK28_2_AB11 IO_L32P_GCLK29_2_Y11 IO_L31N_GCLK30_D15_2_AB12 IO_L31P_GCLK31_D14_2_AA12 IO_L30N_GCLK0_USERCCLK_2_AB13 IO_L30P_GCLK1_D13_2_Y13 IO_L29N_GCLK2_2_U12 IO_L29P_GCLK3_2_T12 IO_L23N_2_U15 IO_L23P_2_T15 IO_L22N_2_T11 IO_L22P_2_R11 IO_L21N_2_AB15 IO_L21P_2_Y15 IO_L20N_2_Y14 IO_L20P_2_W14 IO_L19N_2_AB16 IO_L19P_2_AA16 IO_L18N_2_W13 IO_L18P_2_V13 IO_L17N_2_W15 IO_L17P_2_Y16 IO_L16N_VREF_2_U13 IO_L16P_2_U14 IO_L15N_2_AB17 IO_L15P_2_Y17 IO_L14N_D12_2_AB18 IO_L14P_D11_2_AA18 IO_L13N_D10_2_AB19 IO_L13P_M1_2_Y19 IO_L12N_D2_MISO3_2_T14 IO_L12P_D1_MISO2_2_R13 IO_L6N_2_AB14 IO_L6P_2_AA14 IO_L5N_2_Y18 IO_L5P_2_W17 IO_L4N_VREF_2_V15 IO_L4P_2_U16 IO_L3N_MOSI_CSI_B_MISO0_2_AB20 IO_L3P_D0_DIN_MISO1_2_AA20 IO_L2N_CMPMOSI_2_W18 IO_L2P_CMPCLK_2_V17 IO_L1N_M0_CMPMISO_2_AA21 IO_L1P_CCLK_2_Y20 D C B VCC2V5_FPGA W5 V8 V16 V12 T9 T13 AB3 AA7 AA19 AA15 AA11 VCCO_2_W5 VCCO_2_V8 VCCO_2_V16 VCCO_2_V12 VCCO_2_T9 VCCO_2_T13 VCCO_2_AB3 VCCO_2_AA7 VCCO_2_AA19 VCCO_2_AA15 VCCO_2_AA11 AA3 Y4 U6 T7 AB4 AA4 AB5 Y5 Y6 W6 R8 R9 W8 V7 U8 T8 V9 U9 AB6 AA6 Y8 W9 AB7 Y7 U10 T10 AB8 AA8 Y10 W10 AB9 Y9 W11 V11 AB10 AA10 Y12 W12 AB11 Y11 AB12 AA12 AB13 Y13 U12 T12 U15 T15 T11 R11 AB15 Y15 Y14 W14 AB16 AA16 W13 V13 W15 Y16 U13 U14 AB17 Y17 AB18 AA18 AB19 Y19 T14 R13 AB14 AA14 Y18 W17 V15 U16 AB20 AA20 W18 V17 AA21 Y20 SPI_CS_B FPGA_INIT_B FLASH_D9 FLASH_D8 GPIO_LED_1 IIC_SDA_DVI FLASH_D6 FLASH_D5 GPIO_SWITCH_1 GPIO_SWITCH_2 FMC_LA20_N FMC_LA20_P FMC_LA22_N FMC_LA22_P PHY_TXER PHY_TXCTL_TXEN FMC_LA23_N FMC_LA23_P FLASH_D4 FLASH_D3 SFP_TX_DISABLE_FPGA FLASH_D7 PHY_TXC_GTXCLK NC PHY_TXD0 PHY_TXD1 PHY_TXD2 PHY_TXD3 PMBUS_DATA PMBUS_CLK PHY_TXD4 PHY_TXD5 FMC_LA21_N FMC_LA21_P FMC_LA27_N FMC_LA27_P PHY_TXD6 PHY_TXD7 FMC_LA17_CC_N FMC_LA17_CC_P FLASH_D15 FLASH_D14 USER_CLOCK FLASH_D13 FMC_LA18_CC_N FMC_LA18_CC_P FMC_LA29_N FMC_LA29_P FMC_LA19_N FMC_LA19_P FMC_LA30_N FMC_LA30_P FMC_LA25_N FMC_LA25_P FMC_LA28_N FMC_LA28_P IIC_SCL_DVI FMC_PWR_GOOD_FLASH_RST_B GPIO_LED_3 FMC_PRSNT_M2C_L FMC_LA26_N FMC_LA26_P FMC_LA33_N FMC_LA33_P FLASH_D12 FLASH_D11 FLASH_D10 FPGA_M1 FPGA_D2_MISO3 FPGA_D1_MISO2 FMC_LA24_N FMC_LA24_P FMC_LA32_N FMC_LA32_P FMC_LA31_N FMC_LA31_P FPGA_MOSI_CSI_B_MISO0 FPGA_D0_DIN_MISO_MISO1 FPGA_CMP_MOSI FPGA_CMP_CLK FPGA_M0_CMP_MISO FPGA_CCLK 18 14,20 19 19 14 16,17 19 19 14 14 10 10 10 10 11 11 10 10 19 19 12 19 11 D 11 11 11 11 21,26 21,26 11 11 10 10 10 10 11 11 10 10 19 19 14 19 10 10 10 10 10 10 10 10 10 VCC2V5 10 10 10 1 R10 16,17 4.7K 7,10,19 5% 14 2 1/16W C B 10 10 10 10 10 19 19 19 18 18,19 18,19 10 10 10 10 10 10 18 18,19 18 18 18 18 FPGA Bank 2 Title: A 1 2 R285 140 1% 1/16W FPGA Bank 2 SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM 1 C260 NPO 2 50V 120PF U1 4 3 Sheet Size: B Sheet 2 4 of 0431534 0381305 TSS0123 1280473 A 9-18-2009_15:04 Date: PCB P/N: SCH P/N: Test P/N: ART P/N: Ver: D Rev: 04 Drawn By 35 BF 1 3 2 1 IO_L83N_VREF_3_B1 IO_L83P_3_C1 IO_L82N_3_G6 IO_L82P_3_F5 IO_L81N_3_H8 IO_L81P_3_J7 IO_L80N_3_G7 IO_L80P_3_H6 IO_L60N_3_E4 IO_L60P_3_F3 IO_L59N_3_D1 IO_L59P_3_D2 IO_L58N_3_G4 IO_L58P_3_H4 IO_L57N_VREF_3_K8 IO_L57P_3_K7 IO_L55N_M3A14_3_H5 IO_L55P_M3A13_3_J6 IO_L54N_M3A11_3_E1 IO_L54P_M3RESET_3_E3 IO_L53N_M3A12_3_F1 IO_L53P_M3CKE_3_F2 IO_L52N_M3A9_3_G1 IO_L52P_M3A8_3_G3 IO_L51N_M3A4_3_H3 IO_L51P_M3A10_3_J4 IO_L50N_M3BA2_3_H1 IO_L50P_M3WE_3_H2 IO_L49N_M3A2_3_K5 IO_L49P_M3A7_3_K6 IO_L48N_M3BA1_3_J1 IO_L48P_M3BA0_3_J3 IO_L47N_M3A1_3_K1 IO_L47P_M3A0_3_K2 IO_L46N_M3CLKN_3_K3 IO_L46P_M3CLK_3_K4 IO_L45N_M3ODT_3_L6 IO_L45P_M3A3_3_M6 IO_L44N_GCLK20_M3A6_3_L4 IO_L44P_GCLK21_M3A5_3_M3 IO_L43N_GCLK22_M3CASN_3_M4 IO_L43P_GCLK23_M3RASN_3_M5 IO_L42N_GCLK24_M3LDM_3_N4 IO_L42P_GCLK25_M3UDM_3_P3 IO_L41N_GCLK26_M3DQ5_3_L1 IO_L41P_GCLK27_M3DQ4_3_L3 IO_L40N_M3DQ7_3_M1 IO_L40P_M3DQ6_3_M2 IO_L39N_M3LDQSN_3_N1 IO_L39P_M3LDQS_3_N3 IO_L38N_M3DQ3_3_P1 IO_L38P_M3DQ2_3_P2 IO_L37N_M3DQ1_3_R1 IO_L37P_M3DQ0_3_R3 IO_L36N_M3DQ9_3_T1 IO_L36P_M3DQ8_3_T2 IO_L35N_M3DQ11_3_U1 IO_L35P_M3DQ10_3_U3 IO_L34N_M3UDQSN_3_V1 IO_L34P_M3UDQS_3_V2 IO_L33N_M3DQ13_3_W1 IO_L33P_M3DQ12_3_W3 IO_L32N_M3DQ15_3_Y1 IO_L32P_M3DQ14_3_Y2 IO_L31N_VREF_3_M8 IO_L31P_3_M7 IO_L26N_3_R4 IO_L26P_3_T3 IO_L25N_3_P7 IO_L25P_3_P6 IO_L24N_3_T4 IO_L24P_3_U4 IO_L23N_3_N7 IO_L23P_3_N6 IO_L10N_3_AA1 IO_L10P_3_AA2 IO_L9N_3_P4 IO_L9P_3_P5 IO_L8N_3_V3 IO_L8P_3_V5 IO_L7N_3_T5 IO_L7P_3_T6 IO_L2N_3_Y3 IO_L2P_3_W4 IO_L1N_VREF_3_P8 IO_L1P_3_R7 D C B VCC1V5_FPGA W2 U5 R2 N5 L7 L2 J5 G2 F4 C2 A C1 VTTVREF DUT BANK 3 6slx45tfg484 VCCO_3_W2 VCCO_3_U5 VCCO_3_R2 VCCO_3_N5 VCCO_3_L7 VCCO_3_L2 VCCO_3_J5 VCCO_3_G2 VCCO_3_F4 VCCO_3_C2 B1 C1 G6 F5 H8 J7 G7 H6 E4 F3 D1 D2 G4 H4 K8 K7 H5 J6 E1 E3 F1 F2 G1 G3 H3 J4 H1 H2 K5 K6 J1 J3 K1 K2 K3 K4 L6 M6 L4 M3 M4 M5 N4 P3 L1 L3 M1 M2 N1 N3 P1 P2 R1 R3 T1 T2 U1 U3 V1 V2 W1 W3 Y1 Y2 M8 M7 R4 T3 P7 P6 T4 U4 N7 N6 AA1 AA2 P4 P5 V3 V5 T5 T6 Y3 W4 P8 R7 1 X5R 2 10V 0.1UF 4 GPIO_BUTTON3 GPIO_BUTTON1 GPIO_BUTTON2 CPU_RESET PCIE_PERST_B_LS GPIO_HEADER_0_LS GPIO_HEADER_1_LS GPIO_SWITCH_3 GPIO_BUTTON0 GPIO_HEADER_2_LS SYSACE_MPA06_LS SYSACE_MPA05_LS SYSACE_MPA04_LS 14 14 14 14 35 35 35 14 14 35 35 35 35 FPGA_ONCHIP_TERM2 MEM1_A14 MEM1_A13 MEM1_A11 MEM1_RESET_B MEM1_A12 MEM1_CKE MEM1_A9 MEM1_A8 MEM1_A4 MEM1_A10 MEM1_BA2 MEM1_WE_B MEM1_A2 MEM1_A7 MEM1_BA1 MEM1_BA0 MEM1_A1 MEM1_A0 MEM1_CLK_N MEM1_CLK_P MEM1_ODT MEM1_A3 MEM1_A6 MEM1_A5 MEM1_CAS_B MEM1_RAS_B MEM1_LDM MEM1_UDM MEM1_DQ5 MEM1_DQ4 MEM1_DQ7 MEM1_DQ6 MEM1_LDQS_N MEM1_LDQS_P MEM1_DQ3 MEM1_DQ2 MEM1_DQ1 MEM1_DQ0 MEM1_DQ9 MEM1_DQ8 MEM1_DQ11 MEM1_DQ10 MEM1_UDQS_N MEM1_UDQS_P MEM1_DQ13 MEM1_DQ12 MEM1_DQ15 MEM1_DQ14 D 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 FPGA_ONCHIP_TERM1 SYSACE_D7_LS SYSACE_D6_LS SYSACE_D5_LS SYSACE_D4_LS SYSACE_D3_LS SYSACE_D2_LS SYSACE_D1_LS SYSACE_D0_LS SYSACE_MPBRDY_LS SYSACE_MPIRQ_LS SYSACE_MPA03_LS SYSACE_MPA02_LS SYSACE_MPA01_LS SYSACE_MPA00_LS SYSACE_MPWE_LS SYSACE_MPOE_LS FPGA_VTEMP SYSACE_MPCE_LS 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 1 2 R126 100 5% 1/16W C B 1 2 R124 DNP 1% VCC1V5 1/16W 1 2 R207 150 5% 1/16W FPGA Bank 3 35 Title: GPIO_HEADER_3_LS 35 FPGA Bank 3 SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM Sheet Size: B Sheet 5 of 3 2 Ver: D Rev: 04 Drawn By 35 BF U1 4 0431534 0381305 TSS0123 1280473 A 9-18-2009_15:04 Date: PCB P/N: SCH P/N: Test P/N: ART P/N: 1 4 3 2 1 D D DUT BANK 101 6slx45tfg484 MGTTXP0_101_B6 MGTTXN0_101_A6 MGTRXP0_101_D7 MGTRXN0_101_C7 MGTTXP1_101_B8 MGTTXN1_101_A8 MGTRXP1_101_D9 MGTRXN1_101_C9 MGTREFCLK0P_101_A10 MGTREFCLK0N_101_B10 MGTREFCLK1P_101_C11 MGTREFCLK1N_101_D11 MGTAVCCPLL0_101_B9 MGTAVCCPLL1_101_D12 MGTAVCC_101_C10 MGTAVTTTX_101_A7 MGTAVTTRX_101_D8 C PCIE_TX0_P PCIE_TX0_N PCIE_RX0_P PCIE_RX0_N SMA_TX_P SMA_TX_N SMA_RX_P SMA_RX_N PCIE_250M_P PCIE_250M_N SMA_REFCLK_P SMA_REFCLK_N B6 A6 D7 C7 B8 A8 D9 C9 A10 B10 C11 D11 B9 D12 C10 A7 D8 12 12 12 12 13 13 13 13 28 28 13 13 MGT_AVCC MGT_AVCC 1 C307 X7R 2 10V 0.22UF 1 C308 X7R 2 10V 0.22UF 1 C309 X7R 2 10V 0.22UF 1 C310 X7R 2 10V 0.22UF 1 C311 X7R 2 10V 0.22UF 1 C312 X7R 2 10V 0.22UF 1 C313 X7R 2 10V 0.22UF 1 C314 X7R 2 10V 0.22UF 1 C315 X7R 2 10V 0.22UF 1 C316 X7R 2 10V 0.22UF 1 C326 X5R 2 10V 4.7UF 1 C327 X5R 2 10V 4.7UF 1 C328 X5R 2 10V 4.7UF 1 C329 X5R 2 10V 4.7UF C U1 DUT BANK 123 6slx45tfg484 MGTTXP0_123_B14 MGTTXN0_123_A14 MGTRXP0_123_D13 MGTRXN0_123_C13 MGTTXP1_123_B16 MGTTXN1_123_A16 MGTRXP1_123_D15 MGTRXN1_123_C15 MGTREFCLK0P_123_A12 MGTREFCLK0N_123_B12 MGTREFCLK1P_123_E12 MGTREFCLK1N_123_F12 MGTAVCCPLL0_123_B13 MGTAVCCPLL1_123_E13 MGTAVCC_123_E10 MGTAVTTTX_123_A15 MGTAVTTRX_123_D14 B B14 A14 D13 C13 B16 A16 D15 C15 A12 B12 E12 F12 B13 E13 E10 A15 D14 SFP_TX_P SFP_TX_N SFP_RX_P SFP_RX_N FMC_DP0_C2M_P FMC_DP0_C2M_N FMC_DP0_M2C_P FMC_DP0_M2C_N SFPCLK_QO_P SFPCLK_QO_N FMC_GBTCLK0_M2C_C_P FMC_GBTCLK0_M2C_C_N 12 12 12 12 10 10 10 10 28 28 6 6 MGT_AVCC MGT Banks C400 1 X5R X5R 2 10V 2 10V 0.1UF 0.1UF B A 10 FMC_GBTCLK0_M2C_P Title: FMC_GBTCLK0_M2C_C_P 6 10 FMC_GBTCLK0_M2C_N 1 C401 U1 FMC_GBTCLK0_M2C_C_N 6 Sheet Size: B 3 2 6 of PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 A 9-18-2009_15:04 Date: Sheet 4 MGT Banks SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 GND_W7 GND_W19 GND_W16 GND_V4 GND_V14 GND_V10 GND_U7 GND_U21 GND_U2 GND_R5 GND_R18 GND_P14 GND_P12 GND_P10 GND_N9 GND_N21 GND_N2 GND_N17 GND_N13 GND_N11 GND_M14 GND_M12 GND_M10 GND_L9 GND_L5 GND_L18 GND_L13 GND_L11 GND_K14 GND_K12 GND_K10 GND_J9 GND_J21 GND_J2 GND_J15 GND_J13 GND_J11 GND_H7 GND_G5 GND_G18 GND_F13 GND_E7 GND_E21 GND_E2 GND_E15 GND_E14 GND_E11 GND_D6 GND_D16 GND_D10 GND_C8 GND_C6 GND_C16 GND_C14 GND_C12 GND_B7 GND_B5 GND_B17 GND_B15 GND_B11 GND_AB22 GND_AB1 GND_AA9 GND_AA5 GND_AA17 GND_AA13 GND_A9 GND_A22 GND_A13 GND_A11 GND_A1 C B W7 W19 W16 V4 V14 V10 U7 U21 U2 R5 R18 P14 P12 P10 N9 N21 N2 N17 N13 N11 M14 M12 M10 L9 L5 L18 L13 L11 K14 K12 K10 J9 J21 J2 J15 J13 J11 H7 G5 G18 F13 E7 E21 E2 E15 E14 E11 D6 D16 D10 C8 C6 C16 C14 C12 B7 B5 B17 B15 B11 AB22 AB1 AA9 AA5 AA17 AA13 A9 A22 A13 A11 A1 DUT BANK VCCAUX 6slx45tfg484 VCCAUX_V6 VCCAUX_U11 VCCAUX_R6 VCCAUX_R12 VCCAUX_R10 VCCAUX_N8 VCCAUX_M15 VCCAUX_L8 VCCAUX_K15 VCCAUX_H9 VCCAUX_H15 VCCAUX_G12 VCCAUX_F11 DUT BANK DED 6slx45tfg484 VCCAUX V6 U11 R6 R12 R10 N8 M15 L8 K15 H9 H15 G12 F11 1 J58 H-1X2 J59 1 Pins not connected in LX45T NC_P15 NC_T16 NC_U17 MGTAVTTRCAL_101_E8 MGTRREF_101_E9 PROGRAM_B_2_AB2 DONE_2_AB21 CMPCS_B_2_V18 SUSPEND_AA22 TDO_G17 TMS_D20 TDI_E18 TCK_A21 FMC_PWR_GOOD_FLASH_RST_B 2 P15 T16 U17 E8 E9 AB2 AB21 V18 AA22 G17 D20 E18 A21 MGT_AVCC R260 DNP 1% 1/16W FPGA_VBATT 1/16W 1% 49.9 R127 15 D 2 VCC2V5 1 1 FPGA_PROG_B FPGA_DONE 14,18,20 14 2 R11 4.7K 5% 1/16W FPGA_CMP_CS_B FPGA_SUSPEND SYSACE_CFGTDI FPGA_TMS FPGA_TDI FPGA_TCK 18 18 20 20 20 20 Trace length from the resistor C U1 pins to the FPGA pins MGTRREF and MGTV U1 must be equal in length. VCC3V3 R172 10K 5% 1/16W DUT BANK VCCINT 6slx45tfg484 VCCINT_R14 VCCINT_P9 VCCINT_P13 VCCINT_P11 VCCINT_N14 VCCINT_N12 VCCINT_N10 VCCINT_M9 VCCINT_M13 VCCINT_M11 VCCINT_L14 VCCINT_L12 VCCINT_L10 VCCINT_K9 VCCINT_K13 VCCINT_K11 VCCINT_J8 VCCINT_J14 VCCINT_J12 VCCINT_J10 VCCINT_FPGA 32 32 JTAG_TDI JTAG_TMS 32 JTAG_TCK 1 C2 0.1UF 2 10V X5R 1 2 NC NC NC R14 P9 P13 P11 N14 N12 N10 M9 M13 M11 L14 L12 L10 K9 K13 K11 J8 J14 J12 J10 VCC3V3 U8 1 2 3 4 5 6 7 8 9 10 SN74LV541APWR VCC 20 OE1_N OE2_N 19 A1 Y1 18 A2 Y2 17 A3 Y3 16 A4 Y4 15 A5 Y5 14 A6 Y6 13 A7 Y7 12 A8 Y8 11 FMC_TDI_BUF FMC_TMS_BUF SYSACE_TMS_BUF FMC_TCK_BUF SYSACE_TCK_BUF NC NC NC 10 10 20 10 20 B GND Power, GND, and Dedicated Banks Title: A U1 U1 Power, GND, and Dedicated Banks SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM Sheet Size: B Sheet 3 2 7 of PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 A 9-24-2009_14:59 Date: 4 4,10,19 2 DUT BANK GND 6slx45tfg484 2 2 D 1 R288 DNP 1 1% 1/16W DNP VCCAUX Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 VCCINT 1.2V VCCINT_FPGA D 1 C255 470UF 2 6.3V TANT 10UF 2 6.3V X5R 1 C179 0805 10UF 2 6.3V X5R 1 C178 0805 10UF 2 6.3V X5R 1 C177 0805 10UF 2 6.3V X5R 1 C180 0805 10UF 2 6.3V X5R 1 C176 0805 D 2.2UF 2 6.3V X5R 1 C115 0402 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V X5R X5R X5R X5R X5R X5R 1 C108 1 C107 1 C106 1 C105 1 C103 1 C111 0402 0402 0402 0402 0402 0402 VCCAUX 2.5V VCCAUX 10UF 2 6.3V X5R 1 C389 0805 10UF 2 6.3V X5R 1 C390 0805 2.2UF 2 6.3V X5R 1 C121 0402 2.2UF 2 6.3V X5R 1 C122 0402 2.2UF 2.2UF 2 6.3V 2 6.3V X5R X5R 1 C123 1 C124 0402 0402 2.2UF 2 6.3V X5R 1 C125 0402 2.2UF 2 6.3V X5R 1 C127 0402 2.2UF 2 6.3V X5R 1 C128 0402 1 C257 470UF 2 6.3V TANT C 10UF 2 6.3V X5R 1 C192 0805 C VCC2V5_FPGA VCCO 2.5V 1 C254 470UF 2 6.3V TANT 10UF 2 6.3V X5R 1 C183 0805 10UF 2 6.3V X5R 1 C182 0805 10UF 2 6.3V X5R 1 C181 0805 10UF 2 6.3V X5R 1 C175 0805 10UF 2 6.3V X5R 1 C173 0805 10UF 2 6.3V X5R 1 C186 0805 10UF 2 6.3V X5R 1 C174 0805 10UF 2 6.3V X5R 1 C184 0805 10UF 2 6.3V X5R 1 C185 0805 10UF 2 6.3V X5R 1 C172 0805 10UF 2 6.3V X5R 1 C171 0805 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V X5R X5R X5R X5R X5R X5R X5R X5R 1 C113 1 C102 1 C101 1 C100 1 C99 1 C129 1 C126 1 C120 0402 0402 0402 0402 0402 0402 0402 0402 B B 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V X5R X5R X5R X5R X5R X5R X5R 1 C119 1 C112 1 C110 1 C109 1 C104 1 C98 1 C114 0402 0402 0402 0402 0402 0402 0402 VCC1V5_FPGA A VCCO Bank 3 1.5V 1 C256 470UF 2 6.3V TANT 10UF 2 6.3V X5R 1 C189 0805 10UF 2 6.3V X5R 1 C188 0805 10UF 2 6.3V X5R 1 C187 0805 FPGA Decoupling 2.2UF 2.2UF 2.2UF 2 6.3V 2 6.3V 2 6.3V X5R X5R X5R 1 C118 1 C117 1 C116 0402 0402 0402 Title: FPGA Decoupling SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM Sheet Size: B Sheet 4 3 2 8 of 0431534 0381305 TSS0123 1280473 A 9-24-2009_15:46 Date: PCB P/N: SCH P/N: Test P/N: ART P/N: Ver: D Rev: 04 Drawn By 35 BF 1 3 2 2 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 R85 1 49.9 1% 1/16W2 R82 49.9 1% 1/16W2 R84 1 49.9 1% 1/16W2 1 1 R87 49.9 1% 1/16W2 R89 1 49.9 1% 1/16W2 R86 49.9 1% 1/16W2 R88 1 49.9 1% 1/16W2 1 R91 49.9 1% 1/16W2 R93 1 49.9 1% 1/16W2 1 R90 49.9 1% 1/16W2 R92 1 49.9 1% 1/16W2 1 R95 49.9 1% 1/16W2 R97 1 49.9 1% 1/16W2 1 R94 49.9 1% 1/16W R96 1 49.9 1% 1/16W2 2 R98 49.9 1% 1/16W R199 240 5% 1/16W MEM1_ZQ R80 1 49.9 1% 1/16W2 R83 49.9 1% 1/16W2 1 MEM1_A0 MEM1_A1 MEM1_A2 MEM1_A3 MEM1_A4 MEM1_A5 MEM1_A6 MEM1_A7 MEM1_A8 MEM1_A9 MEM1_A10 MEM1_A11 MEM1_A12 MEM1_A13 MEM1_A14 MEM1_BA0 MEM1_BA1 MEM1_BA2 U42 N3A0 P7A1 P3A2 N2A3 P8A4 P2A5 R8A6 R2A7 T8A8 R3A9 L7A10/AP R7A11 N7A12/BCN T3NC/A13 T7NC/A14 M2BA0 N8BA1 M3BA2 5 5 5 MEM1_WE_B MEM1_RAS_B MEM1_CAS_B L3WE_B J3RAS_B K3CAS_B 5 5 5 MEM1_CLK_P MEM1_CLK_N MEM1_CKE J7CK_P K7CK_N K9CKE R128 100 5% 1/16W C R78 1 49.9 1% 1/16W2 R81 49.9 1% 1/16W2 1 5 MEM1_RESET_B VCC1V5 VCC1V5 D C25 X5R 2 10V 0.1UF 1 MT41J64M16LA_187E FBGA_DDR3_82P_96P FBGA 96 DDR3 SDRAM 2 R13 4.7K 5% 1/16W 1 2 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 LDQS_PF3 LDQS_NG3 MEM1_LDQS_P MEM1_LDQS_N 5 5 UDQS_PC7 UDQS_NB7 MEM1_UDQS_P MEM1_UDQS_N 5 5 MEM1_LDM MEM1_UDM 5 5 E7 D3 R129 100 5% 1/16W C NC NC NC NC NC A9VSS1 B3VSS2 E1VSS3 G8VSS4 J2VSS5 J8VSS6 M1VSS7 M9VSS8 P1VSS9 P9VSS10 T1VSS11 T9VSS12 2 R289 1 4.7K 5% 1/16W2 B1VSSQ1 B9VSSQ2 D1VSSQ3 D8VSSQ4 E2VSSQ5 E8VSSQ6 F9VSSQ7 G1VSSQ8 G9VSSQ9 2 R12 4.7K 5% 1/16W 1 MEM1_DQ2 MEM1_DQ6 MEM1_DQ3 MEM1_DQ7 MEM1_DQ1 MEM1_DQ5 MEM1_DQ0 MEM1_DQ4 MEM1_DQ11 MEM1_DQ9 MEM1_DQ13 MEM1_DQ8 MEM1_DQ15 MEM1_DQ10 MEM1_DQ14 MEM1_DQ12 NC1J1 NC2J9 NC3L1 NC4L9 NC5M7 K1ODT MEM1_CS_B L2 CS_B 1 DQ0E3 DQ1F7 DQ2F2 DQ3F8 DQ4H3 DQ5H8 DQ6G2 DQ7H7 DQ8D7 DQ9C3 DQ10C8 DQ11C2 DQ12A7 DQ13A2 DQ14B8 DQ15A3 LDM UDM T2RESET_B 5 MEM1_ODT 1 M8 FPGAB3_MEMREF VREFCA H1 VREFDQ 1 R79 49.9 1% 1/16W2 1 ZQ 2 1 L8 D 1 (16) VTTVREF B2 VDD1 D9 VDD2 G7 VDD3 K2 VDD4 K8 VDD5 N1 VDD6 N9 VDD7 R1 VDD8 R9 VDD9 (16) VTTDDR 1 A1 VDDQ1 A8 VDDQ2 C1 VDDQ3 C9 VDDQ4 D2 VDDQ5 E9 VDDQ6 F1 VDDQ7 H2 VDDQ8 H9 VDDQ9 4 B B VTTDDR C3 X5R 2 10V 0.1UF 1 C8 X5R 2 10V 0.1UF 1 1 1 C4 X5R 2 10V 0.1UF 1 C5 X5R 2 10V 0.1UF 1 C9 X5R 2 10V 0.1UF 1 C6 X5R 2 10V 0.1UF 1 C10 X5R 2 10V 0.1UF 1 C7 X5R 2 10V 0.1UF C11 X5R 2 10V 0.1UF 1 VCC1V5 C12 X5R 2 10V 0.1UF 1 C18 X5R 2 10V 0.1UF 1 C19 X5R 2 10V 0.1UF C20 X5R 2 10V 0.1UF 1 DDR3 1 C13 X5R 2 10V 0.1UF 1 C14 X5R 2 10V 0.1UF 1 C15 X5R 2 10V 0.1UF 1 C16 X5R 2 10V 0.1UF 1 C17 X5R 2 10V 0.1UF 1 C21 X5R 2 10V 0.1UF C22 X5R 2 10V 0.1UF 1 C23 X5R 2 10V 0.1UF 1 C24 X5R 2 10V 0.1UF 1 Title: A VCCOB3 remote sense pair connects from here back to (10) DDR3 SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM 0431534 0381305 TSS0123 1280473 A Date: 9-24-2009_15:00 Sheet Size: B Sheet 4 PCB P/N: SCH P/N: Test P/N: ART P/N: 3 2 9 of Ver: D Rev: 04 Drawn By 35 BF 1 4 3 J2 D 2 J2 1 J2 J2 DP0_C2M_PC2 FMC_DP0_C2M_P 6 VREF_A_M2CH1 NC PG_C2MD1 FMC_PWR_GOOD_FLASH_RST_B 4,7,10,19 CLK1_M2C_PG2 FMC_CLK1_M2C_P 2 DP0_C2M_NC3 FMC_DP0_C2M_N 6 PRSNT_M2C_LH2 FMC_PRSNT_M2C_L 4 GBTCLK0_M2C_PD4 FMC_GBTCLK0_M2C_P DP0_M2C_PC6 FMC_DP0_M2C_P 6 CLK0_M2C_PH4 FMC_CLK0_M2C_P 2 GBTCLK0_M2C_ND5 FMC_GBTCLK0_M2C_N 6 CLK1_M2C_NG3 FMC_CLK1_M2C_N 2 6 LA00_P_CCG6 FMC_LA00_CC_P 2 DP0_M2C_NC7 FMC_DP0_M2C_N 6 CLK0_M2C_NH5 FMC_CLK0_M2C_N 2 LA01_P_CCD8 FMC_LA01_CC_P 2 LA00_N_CCG7 FMC_LA00_CC_N 2 LA06_PC10 FMC_LA06_P 2 LA02_PH7 FMC_LA02_P 2 LA01_N_CCD9 LA06_NC11 FMC_LA06_N 2 LA02_NH8 FMC_LA02_N 2 LA05_PD11 FMC_LA01_CC_N 2 LA03_PG9 FMC_LA03_P 2 FMC_LA05_P 2 LA03_NG10 FMC_LA03_N 2 LA10_PC14 FMC_LA10_P 2 LA04_PH10 FMC_LA04_P 2 LA10_NC15 FMC_LA10_N 2 LA04_NH11 FMC_LA04_N 2 LA05_ND12 FMC_LA05_N 2 LA08_PG12 FMC_LA08_P 2 LA09_PD14 FMC_LA09_P 2 LA08_NG13 FMC_LA08_N 2 LA14_PC18 FMC_LA14_P 2 LA07_PH13 FMC_LA07_P 2 LA09_ND15 FMC_LA09_N 2 LA12_PG15 FMC_LA12_P 2 LA14_NC19 FMC_LA14_N 2 LA07_NH14 FMC_LA07_N 2 LA13_PD17 FMC_LA13_P 2 LA12_NG16 FMC_LA12_N 2 LA18_P_CCC22 FMC_LA18_CC_P 4 LA11_PH16 FMC_LA11_P 2 LA13_ND18 FMC_LA13_N 2 LA16_PG18 FMC_LA16_P 2 LA18_N_CCC23 FMC_LA18_CC_N 4 LA11_NH17 FMC_LA11_N 2 LA17_P_CCD20 FMC_LA17_CC_P 4 LA16_NG19 FMC_LA16_N 2 LA27_PC26 FMC_LA27_P 4 LA15_PH19 FMC_LA15_P 2 LA17_N_CCD21 FMC_LA17_CC_N 4 LA20_PG21 FMC_LA20_P 4 LA27_NC27 FMC_LA27_N 4 LA15_NH20 FMC_LA15_N 2 LA23_PD23 FMC_LA23_P 4 LA20_NG22 FMC_LA20_N 4 C D SCLC30 IIC_SCL_MAIN 3,15 LA19_PH22 FMC_LA19_P 4 LA23_ND24 FMC_LA23_N 4 LA22_PG24 FMC_LA22_P 4 SDAC31 IIC_SDA_MAIN 3,15 LA19_NH23 FMC_LA19_N 4 LA26_PD26 FMC_LA26_P 4 LA22_NG25 FMC_LA22_N 4 LA21_PH25 FMC_LA21_P 4 LA26_ND27 FMC_LA26_N 4 LA25_PG27 FMC_LA25_P 4 LA21_NH26 FMC_LA21_N 4 TCKD29 FMC_TCK_BUF 7 LA25_NG28 FMC_LA25_N 4 LA24_PH28 FMC_LA24_P 4 TDID30 FMC_TDI_BUF 7,10 LA29_PG30 FMC_LA29_P 4 LA24_NH29 FMC_LA24_N 4 TDOD31 FMC_TDO 10 LA29_NG31 FMC_LA29_N 4 LA28_PH31 FMC_LA28_P 4 3P3VAUXD32 LA31_PG33 FMC_LA31_P 4 LA28_NH32 FMC_LA28_N 4 TMSD33 LA31_NG34 FMC_LA31_N 4 LA30_PH34 FMC_LA30_P 4 TRST_LD34 LA33_PG36 FMC_LA33_P 4 LA30_NH35 FMC_LA30_N 4 GA1D35 LA33_NG37 FMC_LA33_N 4 VCC2V5 LA32_PH37 FMC_LA32_P 4 3P3V_2D36 LA32_NH38 FMC_LA32_N 4 VCC2V5 3P3V_3D38 GA0C34 VCC12_P 12P0V_1C35 12P0V_2C37 VCC3V3 3P3V_1C39 ASP_134603_01 J19 1 FMC_TDI_BUF 2 SYSACE_TDI 3 FMC_TDO 7,10 20 10 VADJ_4H40 FMC_TMS_BUF 7 NC VCC3V3 C VADJ_3G39 3P3V_4D40 ASP_134603_01 H-1X3 B ASP_134603_01 Jumper to include FMC in JTAG chain ASP_134603_01 VCC2V5 VCC3V3 VCC12_P B VCC3V3 GND_41C1 1 2 C388 1UF 50V ELEC 1 3 GND_42C4 GND_43C5 GND_44C8 GND_45C9 GND_46C12 GND_47C13 GND_48C16 GND_49C17 GND_50C20 GND_51C21 GND_52C24 GND_53C25 GND_54C28 GND_55C29 GND_56C32 GND_57C33 GND_58C36 GND_59C38 GND_60C40 GND_61D2 GND_62D3 GND_63D6 GND_64D7 GND_65D10 GND_66D13 GND_67D16 GND_68D19 1 C293 X7R 2 16V 1UF DS1 Q2 4,7,10,19 FMC_PWR_GOOD_FLASH_RST_B 1 C292 X7R 2 16V 1UF R137 200 5% 1/16W 2 GND_69D22 2 LED-GRN-SMT GND_70D25 J2 GND_71D28 1 ANSI/VITA 57.1-2008 Version 1.1 FMC LPC Connector 1 ASP_134603_01 D37GND_72 D39GND_73 G1GND_103 G4GND_104 G5GND_105 G8GND_106 G11GND_107 G14GND_108 G17GND_109 G20GND_110 G23GND_111 G26GND_112 G29GND_113 G32GND_114 G35GND_115 G38GND_116 G40GND_117 H3GND_118 H6GND_119 H9GND_120 H12GND_121 H15GND_122 H18GND_123 H21GND_124 H24GND_125 H27GND_126 H30GND_127 H33GND_128 H36GND_129 A H39GND_130 2 NDS331N Title: FMC Power Good LED FMC LPC Connector SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM Sheet Size: B Sheet 4 3 2 10 of 0431534 0381305 TSS0123 1280473 A 9-25-2009_10:32 Date: PCB P/N: SCH P/N: Test P/N: ART P/N: Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 VCC2V5 PHY_AVDD0 PHY_RXD4 PHY_RXD5 PHY_RXD6 PHY_RXD7 124RXD4 123RXD5 121RXD6 120RXD7 4 3 4 4 PHY_TXC_GTXCLK PHY_TXCLK PHY_TXER PHY_TXCTL_TXEN NC NC SCLK_P110 SCLK_N109 NC NC SIN_P113 SIN_N112 NC NC SOUT_P107 SOUT_N105 NC NC MDIP3_CAP MDIP2_CAP 1 C141 0.01UF 2 X7R 16V 1 C140 0.01UF 2 X7R 16V 4 3 2 8TD3_N MDIP1_CAP 9VCC 10GND 1 C142 0.01UF 2 X7R 16V SH1SH1 2 MDIP0_CAP RJ45 1 C143 0.01UF 2 X7R 16V VCC2V5 111 LED_LINK10 110 LED_LINK100 101 LED_LINK1000 100 LED_DUPLEX 011 LED_RX 010 LED_TX 001 GND 000 D SH2SH2 P1 LED Silkscreen 1 FERRITE-220 3 3 3 3 7TD3_P F207 3RXD0 128RXD1 126RXD2 125RXD3 HSDAC_P53 HSDAC_N54 10/100/1000 RJ45 AND MAGNETICS PHY_RXD0 PHY_RXD1 PHY_RXD2 PHY_RXD3 PHY_MDIP3_P PHY_MDIN3_N 5TD2_N 5 RP2 47 5% 3 3 3 3 MDI3_P61 MDI3_N62 4TD2_P 6 RP2 47 5% 4.7K 7RXCLK 8RXER 4RXDV 2 6 RP3 PHY_RXCLK PHY_RXER PHY_RXCTL_RXDV PHY_MDIP2_P PHY_MDIN2_N 7 RP2 47 5% R247 3 4.99K 3 1% 3 MDI2_P56 MDI2_N57 6TD1_N 1 10 5% 3 3 PHY_MDIP1_P PHY_MDIN1_N 8 RP2 47 5% 3 MDI1_P46 MDI1_N47 Bit [2:0] Pin 3TD1_P 4 PHY_INT PHY_COMA PHY_RESET PHY_RSET PHY_CRS PHY_COL 3 1 31CLK125 32INT_B 37COMA 36RESET_B 39RSET 115CRS 114COL PHY_MDIP0_P PHY_MDIN0_N 5 RP1 47 5% NC MDI0_P41 MDI0_N42 3 33MDIO 35MDC 6 RP1 47 5% PHY_MDIO PHY_MDC Pin to Constant Mapping 1TD0_P 2TD0_N 2 D 2 The PHY MDIP Pins below are Media Dependent Interface Pins (MDIP), and are all bidirectional pins. R15 4.7K 5% 1/16W 7 RP1 47 5% 3 3 1 1 2 R14 4.7K 5% 1/16W 8 RP1 47 5% 1 VCC2V5 DS11 2 150 1/16W 5% 150 PHY_LED_LINK100_R 1/16W 5% PHY_LED_LINK10_R R210 XTAL176 XTAL275 XTAL1_25MHZ_ENET XTAL2_25MHZ_ENET 11 11 11 PHY_LED_LINK10 3 4 TOP "DUP" R212 NC NC "10" C 2 BOT 2 PHY_LED_DUPLEX 1 3 11 2 NC 1 SEL_OSC77 1 C 14GTXCLK 10TXCLK 13TXER 16TXEN VCC2V5 PHY_AVDD0 0.1UF 10V VCC2V5 X5R 4 3 2 1 X5R CP2 0.1UF 10V 4 3 2 CP1 1 5 6 7 8 5 6 7 8 B 71VDDOX_71 34VDDOX_34 94VSS_94 93VSS_93 84VSS_84 83VSS_83 66VSS_66 65VSS_65 63VSS_63 60VSS_60 58VSS_58 55VSS_55 51VSS_51 48VSS_48 45VSS_45 43VSS_43 40VSS_40 38VSS_38 22VSS_22 21VSS_21 15VSS_15 9VSS_9 1VSS_1 VCCINT VCC2V5 PHY_AVDD0 0.01UF 16V X7R 4 3 2 1 CP8 0.01UF 16V X7R 4 3 2 CP7 1 5 6 7 8 5 6 7 8 VCC2V5 A 10UF 2 6.3V X5R 1 C195 0805 10UF 2 6.3V X5R 1 C196 0805 1 C225 1000PF 2 50V X7R 122VDDO_122 30VDDO_30 11VDDO_11 5VDDO_5 1 C224 1000PF 2 50V X7R R211 "100" 4 VCC2V5 DS13 11 PHY_LED_LINK10003 2 PHY_LED_RX_R 4 PHY_LED_TX_R 150 1/16W 5% 150 1/16W 5% R208 1 1 11 R213 1 BOT TOP "RX" 11 XTAL2_25MHZ_ENET 1 "1000" LED_GRN_SMALL_DUAL_STACK 1 C265 NPO 2 50V 22PF 2 11 PHY_CONFIG0 AVDD_104104 AVDD_6464 AVDD_5959 AVDD_5252 AVDD_4949 AVDD_4444 2 R47 DNP 1% 1/16W 1 C266 NPO 2 50V 22PF PHY_AVDD0 VDDOH_8989 VDDOH_9797 VDDOH_7373 VCC2V5 DVDD_118118 DVDD_117117 DVDD_9696 DVDD_9090 DVDD_8585 DVDD_7878 DVDD_2727 DVDD_2323 DVDD_1717 DVDD_1212 DVDD_66 DVDD_22 VCCINT VSS_127127 VSS_119119 VSS_116116 VSS_111111 VSS_108108 VSS_106106 VSS_103103 VSS_102102 VSS_101101 VCC2V5 Bit[2] Bit[1] Bit[0] CFG0 PHYADR[2] PHYADR[1] PHYADR[0] 111 CFG1 ENA_PAUSE PHYADR[4] PHYADR[3] 000 CFG2 ANEG[3] ANEG[2] ANEG[1] 111 CFG3 ANEG[0] ENA_XC DIS_125 111 CFG4 HWCFG_MD[2] HWCFG_MD[1] HWCFG_MD[0] 111 CFG5 DIS_FC DIS_SLEEP HWCFG_MD[3] 111 CFG6 SEL_BDT INT_POL 75/50 OHM 010 10UF 2 6.3V X5R 1 C193 0805 3 Auto-Neg en, advertise all caps; prefer slave. Auto crossover enabled. 125 CLK option disabled. GMII to Cu mode. Fiber/copper autodetect diasabled. Sleep mode disabled. MDC/MDIO selected. Active LOW interrupt 50Ohm SERDES option. 10/100/1000 PHY 1 C228 1000PF 2 50V X7R VCCINT M88E1111 U46 PHYAddr "00111". Don't advertise the PAUSE bit PHY_AVDD0 10UF 2 6.3V X5R 1 C194 0805 VSSC_7474 B Pin Title: 1 C227 1000PF 2 50V X7R 1 C226 1000PF 2 50V X7R 10/100/1000 PHY SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM Sheet Size: B 2 11 of ASSY P/N: 0431540 PCB P/N: 1280479 SCH P/N: 0381311 A 9-24-2009_15:30 Date: Sheet 4 R214 0 5% PHY_LED_RX 1 XTAL1_25MHZ_ENET 11 R1 1M 5% 1/8W PHY_LED_RX 1 11 1 X1 4 TOP LED_GRN_SMALL_DUAL_STACK 2 PHY_LED_LINK100 3 1 11 "TX" 50PPM 25.00MHZ R209 2 PHY_CONFIG0 VCC2V5 150 1/16W 5% 150 PHY_LED_DUPLEX_R 1/16W 5% PHY_LED_LINK1000_R 2 CONFIG088 CONFIG187 CONFIG286 CONFIG382 CONFIG481 CONFIG580 CONFIG679 2 BOT 2 11 11 11 1 2 PHY_LED_DUPLEX PHY_LED_RX PHY_LED_TX PHY_LED_TX 1 LED_DPLX95 LED_RX92 LED_TX91 DS12 11 2 50NC_50 11 11 11 FERRITE-220 NC VCCINT PHY_LED_LINK10 PHY_LED_LINK100 PHY_LED_LINK1000 F1 6 NC NC 67TDI 69TMS 68TRST_B 72TDO 70TCK LED_LINK10100 LED_LINK10099 LED_LINK100098 1 7 5% NC NC 4.7K 5 5% 1 4.7K RP3 5% 1 4.7K RP3 5% 4.7K RP3 1 1 6 4 25TXD4 26TXD5 28TXD6 29TXD7 3 PHY_TXD4 PHY_TXD5 PHY_TXD6 PHY_TXD7 2 4 4 4 4 5% 18TXD0 19TXD1 20TXD2 24TXD3 4.7K RP3 NC 8 PHY_TXD0 PHY_TXD1 PHY_TXD2 PHY_TXD3 5% 4 4 4 4 4.7K RP3 NC 6 RP3 4.7K RP3 5% 9 LED_GRN_SMALL_DUAL_STACK Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 SFP MODULE 0.1UF X5R 10V 4 3 CP3 2 1 TX_FAULT_22 TX_DISABLE3 MOD_DEF2_44 MOD_DEF1_55 MOD_DEF0_66 RATE_SELECT_77 LOS_88 2 1 1 2 2 2 1 SFP_TX_FAULT 2 1% 1% 1% 1 1 2 4.75K 1VEET_1 17VEET_17 20VEET_20 1% 6 6 4.75K R104 SFP_TX_P SFP_TX_N 2121_GND 2222_GND 2323_GND 2424_GND 2525_GND 2626_GND 2727_GND 2828_GND 2929_GND 3030_GND 3131_GND 5 6 7 8 1 TDP_1818 TDN_1919 VCC2V5 4.75K R105 VCC3V3 9VEER_9 10VEER_10 11VEER_11 14VEER_14 D VCC3V3 1% 1 C198 1 C31 1 C32 10UF 0.1UF 0.1UF 2 X5R 2 10V 2 10V 10V X5R X5R 6 6 4.75K R103 1 C30 0.1UF 2 10V X5R SFP_RX_N SFP_RX_P 4.75K R102 FERRITE-220 1 C197 10UF 2 X5R 10V RDN_1212 RDP_1313 1% 2 1 F208 15VCCR_15 16VCCT_16 R100 SFP_VCCR SFP_VCCT FERRITE-220 4.75K R101 VCC3V3 2 1 F4 D Silkscreen: "SFP OK" SFP_TX_DISABLE_FPGA4 1 J15 SFP_MOD_DETECT SFP_RT_SEL SFP_LOS IIC_SDA_SFP 2 IIC_SCL_SFP 2 1 J16 1 J14 VCC3V3 P2 3 J44 C 2 1 1 SFP_CONN_CASE Silkscreen: 2 J22 Silkscreen: "SFP EN" 1 3 "FULL BW" "RT_SEL" "LOW BW" C SFP_LOS 3 P4 VCC3V3 B4 B NC B5 NC B6 B7 NC B8 NC B9 NC B10 NC B11 NC B12 +12V +12V +12V +12V GND GND SMCLK JTAG2/TCK SMDAT JTAG3/TDI GND JTAG4/TDO +3.3V JTAG5/TMS JTAG1/TRST# +3.3V +3.3Vaux +3.3V WAKE# PERST KEY B13 6 PCIE_RX0_P B14 6 PCIE_RX0_N B15 B16 12 PCIE_PRSNT_B B17 B18 A A2 NC A3 NC 12 1 A4 2 A5 NC A6 NC A7 NC A8 NC A9 NC A10 NC R16 DNP 1% 1/16W > 50K pullup B PCIE_PERST_B 35 2 B3 PCIE_PRSNT_B R55 15 5% 1/16W B2 NC A1 PRSNT#1 1 NC +12V 1 2 R48 DNP 1% 1/16W A11 KEY RESERVED GND GND REFCLK+ PETp0 REFCLK- PETn0 GND GND PERp0 PRSNT#2 GND PERn0 GND A12 A13 PCIE_CLK_QO_P 28 A14 PCIE_CLK_QO_N 28 1 C27 0.1UF 2 10V X5R B1 A15 A16 PCIE_TX0_C_P PCIE_TX0_P 6 A17 PCIE_TX0_C_N PCIE_TX0_N 6 A18 1 C26 0.1UF 2 10V X5R NC PCIe 1X Card Edge, SFP Title: PCIe 1X Card Edge, SFP SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: SCH P/N: Test P/N: ART P/N: PCIE_1LANE_EDGE A 9-24-2009_15:00 Date: Sheet Size: B Sheet 4 3 2 12 of 0431534 0381305 TSS0123 1280473 Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 D D C35 1 0.1UF 10V 2 X5R MGT REFCLK SMA_REFCLK_N SMA_REFCLK_P C36 1 0.1UF 10V 2 X5R 6 6 C33 1 0.1UF 10V 2 X5R C J37 32K10K-400E3 GND1 2 GND2 3 GND3 4 SMA_REFCLK_C_P1 SIG GND4 5 GND5 6 GND6 7 GND7 8 SMA_RX_C_N J35 32K10K-400E3 GND1 2 GND2 3 GND3 4 1 SIG GND4 5 GND5 6 GND6 7 GND7 8 SMA_RX_C_P J34 32K10K-400E3 GND1 2 GND2 3 GND3 4 1 SIG GND4 5 GND5 6 GND6 7 GND7 8 SMA_RX_N SMA_RX_P C34 1 0.1UF 10V 2 X5R 6 6 J36 32K10K-400E3 GND1 2 GND2 3 GND3 4 SMA_REFCLK_C_N1 SIG GND4 5 GND5 6 GND6 7 GND7 8 SMA MGT Connectors 3 3 USER_SMA_CLOCK_N USER_SMA_CLOCK_P J41 32K10K-400E3 GND1 2 GND2 3 GND3 4 1 SIG GND4 5 GND5 6 GND6 7 GND7 8 J39 32K10K-400E3 GND1 2 GND2 3 GND3 4 1 SIG GND4 5 GND5 6 GND6 7 GND7 8 USER SMA GPIO 2 2 C USER_SMA_GPIO_N USER_SMA_GPIO_P J40 32K10K-400E3 GND1 2 GND2 3 GND3 4 1 SIG GND4 5 GND5 6 GND6 7 GND7 8 J33 32K10K-400E3 GND1 2 GND2 3 GND3 4 1 SIG GND4 5 GND5 6 GND6 7 GND7 8 B 6 6 J38 32K10K-400E3 GND1 2 GND2 3 GND3 4 1 SIG GND4 5 GND5 6 GND6 7 GND7 8 USER SMA CLOCK SMA_TX_N SMA_TX_P B J32 32K10K-400E3 GND1 2 GND2 3 GND3 4 1 SIG GND4 5 GND5 6 GND6 7 GND7 8 SMA Connectors Title: A SMA Connectors SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM Sheet Size: B Sheet 4 3 2 13 of 0431534 0381305 TSS0123 1280473 A 9-18-2009_15:04 Date: PCB P/N: SCH P/N: Test P/N: ART P/N: Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 VCC2V5 1 VCC2V5 VCC1V5_FPGA VCC1V5_FPGA S2 VCC2V5 C38 1 0.1UF 2 X5R 10V 2 4 4 5 U6 1 2 3 D OE NC GND 6 5 4 VCC OUT_B OUT SYSCLK_N SYSCLK_P 3,14 3,14 GPIO_SWITCH_0 GPIO_SWITCH_1 GPIO_SWITCH_2 GPIO_SWITCH_3 1 2 3 4 8 7 6 5 1 2 R17 4.7K 5% 1/16W Pushbutton D 200MHZ 1 SDMX-4-X 1% 2 7,18,20 FPGA_PROG_B 1 P4 P2 P3 2 P2 P3 4 3 SW4 4 3 1 R229 1/16W SW3 VCC1V5_FPGA (Alternate Package) 2 1.00K R225 1/16W R224 1/16W 2 3,14 3,14 P1 GPIO_BUTTON0 P4 1% 1 5 Pushbutton 1.00K 1.00K 1.00K SYSCLK_N SYSCLK_P 2 1 R223 1/16W 6 5 4 VCC OUT_B OUT 1.00K SI500D OE NC GND 2 1 R222 1/16W U9 1% 2 1 1 2 3 1% 1% VCC2V5 NC pins connected to line up overlayed footprints P1 VCC1V5_FPGA Pushbutton Differential System Clock 1 Pushbutton 4 1 GPIO_LED_3 3 CPU_RESET 2 P2 GPIO_LED_2 P3 3 2 1 2 1 C R228 1/16W GPIO_LED_0 P3 VCC1V5_FPGA 1.00K 2 P2 3 1% GPIO_LED_1 2 SW7 SW6 4 GPIO_BUTTON1 4 4 1.00K 5 5 P4 P4 1% C P1 P1 R230 1/16W 2 2 2 2 200 5% 1/16W GPIO_HEADER_3 200 5% 1/16W2 35 GPIO_BUTTON2 2 P4 P2 P3 4 3 SW5 2 3 1 4 R227 1/16W 2 GPIO_HEADER_2 1 35 5 2 1 2 R71 27.4 1% 1/16W GPIO_HEADER_1 P1 1.00K 2 1 GPIO_HEADER_0 35 1 HDR_1x6 J55 1 1% R72 27.4 1% 1/16W 1 1 DS6 LED-GRN-SMT 2 R73 27.4 1% 1/16W 1 1 DS5 LED-GRN-SMT 1 R74 27.4 1% 1/16W DS4 1 2 LED-GRN-SMT DS3 LED-GRN-SMT 1 35 R282 1 R280 200 200 5% 5% 2 1/16W2 1/16W R283 1 R281 Pushbutton VCC1V5_FPGA 5 6 HDR_1X6 B B VCC3V3 Pushbutton 1 5 VCC3V3 GPIO_BUTTON3 2 VCC2V5 VCC2V5 P1 P4 P2 P3 4 3 2 2 R215 0 5% 1/16W 1 1 2 2 1 R169 332 1% 1/16W 2 A 2 75.0 1% 2 R19 4.7K 5% 1/16W R69 1 4 1 OUT USER_CLOCK Clocks, LEDs, Buttons, Switches DS2 GND INIT_B = 0, LED: ON INIT_B = 1, LED: OFF 5 FPGA_DONE LED-GRN-SMT OSC 7 2 VCC VCC2V5 1 C37 1 0.1UF 2 X5R 10V 4 OE 8 DS17 1 LED-RED-SMT 2 R18 4.7K 5% 1/16W 1 R226 1/16W 1 R49 DNP 1% 1/16W Title: 1 FPGA_INIT_B X2 1 4,20 110880 2 R70 27.4 1% 1/16W Clocks, LEDs, Buttons, Switches SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM Sheet 3 2 14 of PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 A 3-17-2010_9:23 Date: Sheet Size: B Single Ended User Clock 4 1.00K 1% SW8 VCC2V5 Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 1 1 VCC3V3 2 1 2 R5 1.0K 5% 1/10W 1 NC R50 0 5% NC M6 D R6 1.0K 5% 1/10W M1 M5 1 NC D 2 VCC3V3 2 R291 0 5% 1/16W 2 1 R292 0 5% 1/16W 1 2 3 A0 A1 A2 WP 7 VCC GND 8 4 C40 1 0.1UF 2 X5R 10V NC NC M2 SCL SDA M4 6 5 M3 1 U4 3,10,15 IIC_SCL_MAIN 3,10,15 IIC_SDA_MAIN NC M24C08-WDW6TP 1 2 3,10,15 IIC_SCL_MAIN 2 H-1X2 1 Fiducials R216 DNP 1% 1/16W IIC_SDA_MAIN 3,10,15 IIC Address 0b1010100 J45 Rechargeable Battery C C VCC5 1 NC CP2103 USB Self-Powered 1 R278 1.54K 1% 2 (26mA max) NC USB_1_CTS 3 1 2 22 3 D+ USB_1_DATA_P 4 D- USB_1_DATA_N 5 VIO GPIO2 USB_1_VBUS 6 VDD GPIO3 NC 20 NC 19 NC 18 NC 17 NC 16 NC 15 NC CTR_GND 21 UART, IIC Header/EEPROM 30 NC3 NC2 1C163 X5R 2 6.3V 1UF NC4 SUSPEND REGIN NC 14 2 R20 4.7K 5% 1/16W 1C164 1 C41 X5R 0.1UF 2 6.3V 2 X5R 1UF 10V 8 1 1 C39 0.1UF 2 X5R 10V GPIO1 NC 13 7 Bridge SUSPEND_B 1 USB_MINI_B GPIO0 NC 12 2 NC9 USB to RS232 NC1 3 1 CTS_I_B 23 RTS_O_B 24 RXD_I TXD_O NC NC 4 R279 4.75K 1% 2 NC 25 26 27 GND1 VCC2V5 5 40V 200MA B NC10 NC 11 VBUS 3 (Approx 3.1V) FPGA_VBATT 2 CP2103GM NC 10 D_N USB_1_RTS 7 3 U30 RI_I_B RST_B D_P 3 2 9 SHLD1 SHLD2 SHLD3 SHLD4 ID 1 VBUS 6 7 8 9 J23 GND USB_1_RX D11 BAS40-04 B2 DSR_I_B VCC3V3 DCD_I_B SP0503BAHT CNR_GND 29 X3 225MW DTR_O_B 3 28 2 B 3 4 NC 1 USB_1_TX CP2103GM Title: A UART, IIC Header/EEPROM SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM The VIO voltage must match the appropriate bank IO voltage Sheet Size: B Sheet 4 3 2 15 of 0431534 0381305 TSS0123 1280473 A 9-24-2009_15:00 Date: PCB P/N: SCH P/N: Test P/N: ART P/N: Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 VCC5 F9 1 FERRITE-220 VCC2V5 1 D F8 3 BAS40-04 40V 6 7 3 BAS40-04 DATA2_N DATA2_P NC NC 12 13 DATA3_N DATA3_P NC NC 4 5 DATA4_N DATA4_P NC NC 20 21 DATA5_N DATA5_P DVI_CLK_P DVI_CLK_N 23 24 DVI_CONN_HPDET C42 X5R 2 10V 0.1UF 1 SHIELD_CLK SHIELD_0/5 SHIELD_1/3 SHIELD_2/4 22 19 11 3 GND0 15 CLK_P CLK_N AGND0 AGND1 C5 C6 16 HPDET SH_GND1 SH_GND2 25 26 DVI_CONN_HSYNC DVI_CONN_VSYNC C4 8 HS VS DVI_CONN_RED DVI_CONN_GREEN DVI_CONN_BLUE C1 C2 C3 RED GREEN BLUE C GND_VIDEO BAS40-04 40V VCC3V3 P3 B BAS40-04 DVI_CONN 40V 330MA 5% 1 C271 NPO 2 50V 22PF VCC3V3 BAS40-04 1 C282 NPO 2 50V 33PF 3 5% 2 1 2 1 330MA D7 1 1 C272 NPO 2 50V 22PF 1 R122 75.0 1% DVI_GREEN 2 200MA GND_VIDEO L6 82NH L5 82NH DVI_BLUE_TMP 40V DVI VIDEO CONNECTOR 5% VCC3V3 BAS40-04 330MA 2 1 C283 NPO 2 50V 33PF 2 1 2 5% 3 330MA 1 C273 NPO 2 50V 22PF D8 1 1 C274 NPO 2 50V 22PF 1 R123 2 1 DVI_BLUE 75.0 1% 17 VCC5 1 2 To Video Codec 3 1 D4 1 C269 NPO 2 50V 22PF L4 82NH DVI_GRN_TMP DVI_D2_N DVI_D2_P VCC5 14 2 To Video Codec 17 L1 82NH DATA1_N DATA1_P 3 5% 1 330MA 200MA GND_VIDEO 9 10 2 1 C281 NPO 2 50V 33PF DVI_D1_N DVI_D1_P 2 1 5% D6 330MA 17 17 3 1 D5 GND_VIDEO 2 1 75.0 1% R121 1 B 1 C270 NPO 2 50V 22PF BAS40-04 2 200MA DVI_RED 2 DATA0_N DATA0_P 40V VCC3V3 L3 82NH DVI_RED_TMP 17 18 2 GND_VIDEO 17 17 DVI_D0_N DVI_D0_P 2 17 VCC3V3 200MA 1 C268 NPO 2 50V 22PF L2 82NH 1 D3 FERRITE-220 F6 1 DVI_VSYNC 1 17 FERRITE-220 F7 1 C267 NPO 2 50V 22PF 17 17 40V 2 To Video Codec 17 DVI_HSYNC VCC5 2 C 17 17 R250 1.21K 1% 1 200MA DDC_CLK DDC_DATA 1 2 DVI_HPDET C43 X5R 2 10V 0.1UF DVI_CONN 2 200MA 17 IIC_SDA_DVI_F VCC5 D2 Q8 NDS331N 1 C284 X7R 2 50V 270PF 2 3 1 2 40V 1 D1 2 IIC_SDA_DVI 4,17 200MA FERRITE-220 3 VCC5 1 To IIC DVI Bus Q7 NDS331N 1 C285 X7R 2 50V 270PF BAS40-04 D 1 IIC_CLK_DVI_F 3 1 2 R60 2.43K 1% 2 2 IIC_SCL_DVI 4,17 R59 1 2.43K 1% 2 200MA A GND_VIDEO Title: DVI VIDEO CONNECTOR SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM 40V PCB P/N: SCH P/N: Test P/N: ART P/N: A 9-18-2009_15:03 Date: Sheet Size: B Sheet 4 3 2 16 of 0431534 0381305 TSS0123 1280473 Ver: D Rev: 04 Drawn By 35 BF 1 3 2 DVI_D0_N DVI_D0_P 16 16 DVI_D1_N DVI_D1_P 16 16 DVI_D2_N DVI_D2_P D 16 16 DVI_CLK_P DVI_CLK_N 16 16 DVI_HPDET 1 2 3 1 C133 X5R 2 10V 1UF 38 37 39 23 29 TGND1 TGND2 TGND3 20 26 32 AVDD 18 C47 X5R 2 10V 0.1UF C50 X5R 2 10V 0.1UF 1 C48 X5R 2 10V 0.1UF C49 X5R 2 10V 0.1UF 1 C200 X5R 2 10V 10UF 1 VDD 33 1 C201 X5R 2 10V 10UF C45 X5R 2 10V 0.1UF 19 35 U31 CH7301C-TF 34 40 2 VCC3V3 17 B 1 C202 X5R 2 10V 10UF DVI_VCCA 2 DVI_VDD 1 VCC3V3 DVI_VCCA 2 1 DVI_AVDD 1 C44 X5R 2 10V 0.1UF F69 AGND2 1 C199 X5R 2 10V 10UF 1 DVI_TVDD 1 17 GND1 GND2 DNP 2 TVDD1 TVDD2 FERRITE-220 C46 X5R 2 10V 0.1UF F192 6 11 64 1 DGND0 DGND2 DGND3 DVI_DVDD 1 FERRITE-220 1 12 49 1 DVDD1 DVDD2 DVDD3 1 GPIO1 GPIO0 AS ISET DVI_AS 7 8 10 2 1 C148 X7R 2 16V 0.01UF U10 17 2 NC SPD SPC 4 C F193 DVI_GPIO1 14 15 1 C258 NR_FB C51 X5R 2 10V 0.1UF 1 3 IIC_SDA_DVI IIC_SCL_DVI NC0 NC1 NC2 NC3 NC4 NC5 NC6 4,16 4,16 (3.3V) 16 36 41 42 43 44 46 2 VSWING B R611 R631 R64 2.43K 2.43K 2.43K 1% 1% 1% 2 2 EN 17 R107 4.75K 1 1% VCC2V5 1 DVI_VCCA GND_VIDEO F10 2 DE H V 5 45 3 1 XCLK_N XCLK_P OUT GND 2 DVDDV VREF RESET_B IN R106 4.75K 1% F11 2 2 4 5 1 R G B 48 47 HSYNC VSYNC HPDET 9 30 31 TLC_P TLC_N 27 28 TDC2_N TDC2_P 24 25 TDC1_N TDC1_P D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 2 1 R42 47.5 1% 1/16W 1 2 1 2 R41 47.5 1% 1/16W R40 47.5 1% 1/16W 1 TPS73633DBVT FERRITE-220 56 57 R130 100 5% 1/16W 13 DVI_XCLK_N DVI_XCLK_P DVI_DE DVI_H DVI_V VCC5 FERRITE-220 2 DVI_RESET_B 3 3 3 3 3 D FERRITE-220 2 1 3 TDC0_N TDC0_P 2 1 2 R35 47.5 1% 1/16W 50 51 52 53 54 55 58 59 60 61 62 63 R39 47.5 1% 1/16W 1 2 1 2 R38 47.5 1% 1/16W R37 47.5 1% 1/16W 1 2 DVI_D3 DVI_D2 DVI_D1 DVI_D0 21 22 R31 47.5 1% 1/16W R30 47.5 1% 1/16W 1 2 1 2 1 2 R34 47.5 1% 1/16W R33 47.5 1% 1/16W R32 47.5 1% 1/16W 1 R36 47.5 1% 1/16W 3 3 3 3 1 C 16 16 16 16 16 Near DVI IC VCC2V5 2 1 DVI_D7 DVI_D6 DVI_D5 DVI_D4 2 3 3 3 3 R29 47.5 1% 1/16W R28 47.5 1% 1/16W DVI_D11 DVI_D10 DVI_D9 DVI_D8 1 3 3 3 3 16 DVI_HSYNC DVI_VSYNC DVI_RED DVI_GREEN DVI_BLUE Place termination RPs near FPGA 1 To DVI Connector 4 GND_VIDEO 2 R192 140 1% 1 R62 2.43K 1% NC NC NC NC NC NC NC 1 DVI CODEC 2 GND_VIDEO Title: A IIC Address = 0x76 DVI CODEC SCHEM, ROHS COMPLIANT, SP605 EVALUATION PLATFORM PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 A Date: 9-18-2009_15:03 Sheet Size: B Sheet 4 3 2 17 of Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 VCC3V0 C52 X5R 2 10V 0.1UF 1 1 1 R7 1.0K 5% 1/10W 2 1 2 1 R51 DNP 1% 1/16W 2 4,18,19FPGA_D2_MISO3 OFF: SPI External 2 18 SPIX4_CS_B 4,18,19FPGA_D0_DIN_MISO_MISO1 1 ON: SPI X4 R132 100 5% 1/16W SPI Selection 1 16 IO3_HOLD_B CLK 2 15 VCC IO0_DIN 3 14 NC0 NC7 4 13 NC1 NC6 5 12 NC2 NC5 6 11 NC3 NC4 7 10 CS_B GND 8 9 IO1_DOUT IO2_WP_B NC NC NC NC R23 1.8K 5% 1/16W FPGA_CCLK 4,18 FPGA_MOSI_CSI_B_MISO04,18 NC NC NC NC FPGA_D1_MISO2 4,18,19 2 R25 1.8K 5% 1/16W R131 100 5% 1/16W 2 D 1 D W25Q64VSFIG U32 SPI X4 2 18 SPIX4_CS_B C 1 SPI_CS_B 4,18 J46 H-1X2 C VCC2V5 SPI Select Jumper 1/16W 5% 200 R138 4,18 FPGA_M0_CMP_MISO 4 FPGA_M1 1 2 R8 1.0K 5% 1/10W 1 2 1 4 2 3 2 1 1/16W 5% 200 R139 Silkscreen: 2 J17 1 1 2 3 4 5 6 7 8 9 TMS TDI TDO TCK GND 3V3 SW1 SDMX-2-X R9 1.0K 5% 1/10W FPGA_PROG_B 7,14,20 FPGA_D2_MISO3 4,18,19 FPGA_D1_MISO2 4,18,19 SPI_CS_B 4,18 FPGA_MOSI_CSI_B_MISO0 4,18 FPGA_D0_DIN_MISO_MISO1 4,18,19 FPGA_CCLK 4,18 VCC3V3 H-1X9 B SPI Program Header Mode pin DIP switches 3 B FPGA_AWAKE VCC2V5 2 DS7 2 FPGA_SUSPEND 1 1 LED-GRN-SMT 7 2 1 A 2 R21 H-1X2 4.7K 5% 1/16W HDR_1x6 J3 1 FPGA_M0_CMP_MISO 4,18 1 J47 2 FPGA_CMP_MOSI 4 3 FPGA_CMP_CLK 4 4 FPGA_CMP_CS_B 7 VCC3V3 SPI, CMP, Mode, and Suspend 5 R75 27.4 1% 1/16W Title: 6 SPI, CMP, Mode, and Suspend SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: SCH P/N: Test P/N: ART P/N: DNP Suspend Jumper Sheet Size: B Sheet 4 A 9-24-2009_15:00 Date: 3 2 18 of 0431534 0381305 TSS0123 1280473 Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 Silkscreen: "Strata FLASH" "256 MBit" D D VCC1V8 FLASH_A0 FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_A22 FLASH_A23 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 VCC2V5 2 1 2 1/16W 1.00K 1/16W 1.00K 1/16W 1.00K 1/16W 1.00K 1 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 FLASH_ADV_B FLASH_WAIT 3 3 B 1 C203 X5R 2 10V 10UF C57 X5R 2 10V 0.1UF 1 VCC2V5 VCCQ38 VPP43 VSS012 VSS128 31 1 C204 X5R 2 10V 10UF C56 1 C55 X5R X5R 2 10V 2 10V 0.1UF 0.1UF 1 C54 1 C53 X5R X5R 2 10V 2 10V 0.1UF 0.1UF 1 VSS2 A24 C 44 RST_B 45 CLK 14 WE_B 32 OE_B 27 RFU 30 CE_B 15 WP_B 46 ADV_B 56 WAIT B 1% JS28F256P30T95 U25 R113 1 VCC013 VCC133 FPGA_D0_DIN_MISO_MISO1 34 DQ0 FPGA_D1_MISO2 36 DQ1 FPGA_D2_MISO3 39 DQ2 FLASH_D3 41 DQ3 FLASH_D4 47 DQ4 FLASH_D5 49 DQ5 FLASH_D6 51 DQ6 FLASH_D7 53 DQ7 FLASH_D8 35 DQ8 FLASH_D9 37 DQ9 FLASH_D10 40 DQ10 FLASH_D11 42 DQ11 FLASH_D12 48 DQ12 FLASH_D13 50 DQ13 FLASH_D14 52 DQ14 FLASH_D15 54 DQ15 FMC_PWR_GOOD_FLASH_RST_B FLASH_CLK FLASH_WE_B FLASH_OE_B NC FLASH_CE_B 4,7,10 Synchronous mode not supported 1% 2 1 R112 R111 1% 2 1 1/16W 1.00K R110 1% 2 1 1% R109 1% 4,18 4,18 4,18 R108 C 29 A1 25 A2 24 A3 23 A4 22 A5 21 A6 20 A7 19 A8 8 A9 7 A10 6 A11 5 A12 4 A13 3 A14 2 A15 1 A16 55 A17 18 A18 17 A19 16 A20 11 A21 10 A22 9 A23 26 1/16W 1.00K 2 ASYNC. SRAM FLASH Title: A ASYNC. SRAM FLASH SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 A Date: 9-18-2009_15:03 Sheet Size: B Sheet 4 3 2 19 of Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 VCC2V5 VCC3V3 SYSACE_RESET_B 20 1 Silkscreen: "SYSACE RESET" Pushbutton SysACE Failsafe Mode Jumpers 108 74 72 R116 POR_BYPASS POR_TEST POR_RESET R115 SYSACE_CFA07 SYSACE_CFWE SYSACE_CFA08 SYSACE_CFA09 SYSACE_CFDE SYSACE_CFA10 SYSACE_CFCE2 SYSACE_CFCE1 SYSACE_CFD15 SYSACE_CFD07 SYSACE_CFD14 SYSACE_CFD06 SYSACE_CFD13 SYSACE_CFD05 SYSACE_CFD12 SYSACE_CFD04 SYSACE_CFD11 SYSACE_CFD03 SYSACE_CFCD1 35_IOWR 34_IORD 35 34 46_BVD1 45_BVD2 40_VS2 33_VS1 24_WP 43_INPACK 46 45 40 33 24 43 39_CSEL 41_RESET 39 41 1% 1 R118 1 1% 4.75K 38 13 38_VCC 13_VCC 4.75K 25_CD2 49_D10 48_D09 23_D02 47_D08 22_D01 21_D00 20_A00 44_REG 19_A01 18_A02 42_WAIT 17_A03 16_A04 15_A05 14_A06 37_RDY/BSY 12_A07 36_WE 11_A08 10_A09 9_OEI 8_A10 32_CE2 7_CE1I 31_D15 6_D07 30_D14 5_D06 29_D13 4_D05 28_D12 3_D04 27_D11 2_D03 26_CD1 2 2 C NC NC NC NC NC NC 1% NC 25 49 48 23 47 22 21 20 44 19 18 42 17 16 15 14 37 12 36 11 10 9 8 32 7 31 6 30 5 29 4 28 3 27 2 26 R117 SYSACE_CFCD2 SYSACE_CFD10 SYSACE_CFD09 SYSACE_CFD02 SYSACE_CFD08 SYSACE_CFD01 SYSACE_CFD00 SYSACE_CFA00 SYSACE_CFREG SYSACE_CFA01 SYSACE_CFA02 SYSACE_CFWAIT SYSACE_CFA03 SYSACE_CFA04 SYSACE_CFA05 SYSACE_CFA06 SYSACE_CFRDBSY 1% U17 13 12 11 8 7 6 5 4 3 142 141 140 139 137 135 134 133 132 131 130 125 123 121 138 119 118 117 116 115 114 113 107 106 105 104 103 1 1 2 2 50 1 50_GND 1_GND U37 1 1 1 NC 8 7 6 5 2 2 2 2 1/16W 2 1 R136 1/16W 2 1 200 1 2 5% 2 1 R135 1/16W 1% Combined FPGA & CPU PC4 Connector 1 2 3 4 1 200 SYSACE_CFGADDR0 SYSACE_CFGADDR1 SYSACE_CFGADDR2 SYSACE_CFGMODEPIN 5% 20 20 20 20 B 5% 78 79 82 85 80 81 86 87 88 89 93 95 96 98 101 97 102 VCC2V5 R218 1/16W SYSACE_CFGMODEPIN SDMX-4-X System ACE CF CLK_33MHZ_SYSACE VCC 4 OUT 3 DS8 GND 1 SA_STAT_RES LED-GRN-SMT 1 C58 0.1UF 2 10V X5R 33.000MHZ 50PPM Silkscreen "System ACE" "Error LED" DS18 2 1 SA_ERR_RES LED-RED-SMT Disable SysACE Error LED 2 1 SYSACE_ERR_LED H-1X2 4 SYSACE_TDI JTAG_TDO SYSACE_TCK_BUF SYSACE_TMS_BUF SYSACE_STAT_LED 2 TRI 2 2 10 32 7 7 PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 A 3-17-2010_9:23 Sheet Size: B Sheet 20 J60 3 SYSTEM ACE CF SCHEM, ROHS COMPLIANT, SP605 EVALUATION PLATFORM Date: 2 1 Title: R193 180 5% 1/16W U29 R194 180 5% 1/16W A Silkscreen "System ACE" "Status LED" VCC3V3 1 VCC2V5 1 3 1% 4.75K 1 17 37 55 92 73 109 128 33 RESET_B VCCL_10 VCCL_15 VCCL_25 VCCL_57 VCCL_84 VCCL_94 VCCL_99 VCCL_126 PARTS=1 LEVEL=STD XCCACE-TQ144I SYSACE_CFGADDR0 SYSACE_CFGADDR1 SYSACE_CFGADDR2 20 NC SYSTEMACE TQFP144 (DIE DOWN) CFCD2 CFD10 CFD09 CFD02 CFD08 CFD01 CFD00 CFA00 CFREG CFA01 CFA02 CFWAIT CFA03 CFA04 CFA05 CFA06 CFGRSVD CFA07 CFWE CFA08 CFA09 CFOE CFA10 CFCE2 CFCE1 CFD15 CFD07 CFD14 CFD06 CFD13 CFD05 CFD12 CFD04 CFD11 CFD03 CFCD1 R133 SYSACE_CFGTDI 20 VCC3V3 2 R134 1/16W 7 1 SYSACE_ERR_LED 1 1.00K R221 1%1.00K 1/16W R220 1%1.00K 1/16W R219 1%1.00K 1/16W FPGA_TDI FPGA_TMS FPGA_TCK 20 J48 H-1X2 S1 7 7 7 20 20 20 2 J49 FPGA_PROG_B VCC3V3 200 FPGA_INIT_B 1 SYSACE_RESET_B N7E50-7516PG-20 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC25 2 SYSACE_ERR_LED 200 4,14 1 D H-1X2 2 2 7,14,18 Failsafe Mode Enabled 5% R119 B 1% 4.75K VCC2V5 34 36 38 40 71 90 122 124 127 143 SW9 = OR 1 1.21K NC NC NC NC NC NC NC NC NC NC 3 1.21K R252 SYSACE_D7 SYSACE_D6 SYSACE_D5 SYSACE_D4 SYSACE_D3 SYSACE_D2 SYSACE_D1 SYSACE_D0 SYSACE_MPA03 SYSACE_MPA02 SYSACE_MPA01 SYSACE_MPA00 SYSACE_MPWE SYSACE_MPOE P3 R251 35 35 35 35 35 35 35 35 35 35 35 35 35 35 MPBRDY MPIRQ MPCE MPA06 MPA05 MPA04 MPD15 MPD14 MPD13 MPD12 MPD11 MPD10 MPD09 MPD08 MPD07 MPD06 MPD05 MPD04 MPD03 MPD02 MPD01 MPD00 MPA03 MPA02 MPA01 MPA00 MPWE MPOE P2 35_GND 26_GND 18_GND 9_GND 144_GND 136_GND 129_GND 120_GND 111_GND 46_GND 54_GND 64_GND 83_GND 75_GND 91_GND 100_GND 112_GND 110_GND C 39 41 42 43 44 45 47 48 49 50 51 52 53 56 58 59 60 61 62 63 65 66 67 68 69 70 76 77 P4 35 26 18 9 144 136 129 120 111 46 54 64 83 75 91 100 112 110 NC NC NC NC NC NC NC NC NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 VCCH_1 VCCH_17 VCCH_37 VCCH_55 VCCH_92 VCCH_73 VCCH_109 VCCH_128 10 15 25 57 84 94 99 126 SYSACE_MPBRDY SYSACE_MPIRQ SYSACE_MPCE SYSACE_MPA06 SYSACE_MPA05 SYSACE_MPA04 2 14 16 19 20 21 22 23 24 27 28 29 30 31 32 CFGINIT CFGPROG CFGTDO CFGTMS CFGTCK CFGTDI CFGADDR0 CFGADDR1 CFGADDR2 CFGMODEPIN CLK STATLED ERRLED TSTTMS TSTTCK TSTTDO TSTTDI 0.1UF X5R 10V NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 4 3 CP6 2 1 0.1UF X5R 10V 4 3 2 1 CP5 0.1UF X5R 10V 4 3 CP4 2 1 5 6 7 8 5 6 7 8 5 6 7 8 35 35 35 35 35 35 2 P1 4 1% 1 D VCC2V5 NC 4.75K VCC3V3 2 20 of Ver: D Rev: 04 Drawn By 35 BF 1 2 R154 10.0K 1% 1/16W 2 R150 10.0K 1% 1/16W NC 6 13 TI_RESET_B 2 J5 1 2 3 4 1 1 C287 X5R 2 10V 4.7UF J9 TI_TCK TI_TMS TI_TDI TI_TDO DNP 44 47 46 45 NC 14 48 TRST_B /RESET 2 DNP J7 DNP J8 1 1 1 2 R99 27.4K 1% 1/16W 1 2 R170 1 27.4K 1% 1/16W2 R146 1 10.0K 1% 1/16W 2 R151 10.0K 1 1% 1/16W 2 C60 X5R 10V 0.1UF C62 1 X5R 2 10V 2 0.1UF 1 TCK TMS TDI TDO TRCK /TRST C152 X7R 16V 0.01UF 1 AGND1 9240 TI_V3P3 1 2 PWR_INH J10 A Z1 22,23,24,29,30 25 26 NC 38 52 NC 29 41 66 67 3 74 VCC3A_PWM 0603_SHORT R231 1.00K 1% 1/16W 2 2 23 24 VCC3A_SRE 24 VCC3A_FLT 24 VCC3B_FLT 24 26 24 AGND1 9240 VCC3_EA_P VCC3_EA_N NC NC NC NC NC 1 1 C220 X5R 2 10V 0.068UF VCC3A_CS NC 1 NC 2 3 24 21 TEMP 16 A6 A2 15 TEMP3 A A1 14 TEMP2 23 TEMP1 22 NC 4 A7 A0 13 NC 5 A5 A3 12 NC 6 E_B S0 11 TMUX0 21 TMUX1 21 TMUX2 21 1 C217 X5R 2 10V 0.068UF VCC4B_FLT 26 PWRGOOD DIAG-LED 49 10 NC AGND1 9240 7 VEE S1 10 8 GND S2 9 FAN_PWM FAN_TACH 25 25 TI_PWRGOOD 25 AGND1 9240 VCC12_P 1 C250 X7R 2 16V 0.1UF AGND1 UCD9240PFC 9240 B VCC5 U5 TL1963AKTTR 1 AGND1 9240 24 VCC A4 CD74HC4051 31 NC 30 NC 53 32 Z3 C U2 1 C219 X5R 2 10V 0.068UF NC NC X5R 2 10V 0.1UF 1 R287 1.00K 1% 1/16W Do not use PMBus Addresses 0, 1, 2, 3, 12, 126 or 127 VCC2A_CS 1 2 1 VCC2_EA_P VCC2_EA_N Note: VCC3V3A SYNC-IN SYNC-OUT FAN-PWM FAN-TACH 2 1 SHDN_B 2 IN SNS_ADJ 5 OUT 4 1/16W 1% 2.15K R77 2 5V @ 1.5A 2 1 C294 X5R 2 10V 0.47UF 1 0603_SHORT AGND1 9240 R22 4.7K 5% 1/16W 2 DGND1 9240 DPWM-3A DPWM-3B SRE-3A SRE-3B FAULT-3A FAULT-3B EAP3 EAN3 CS-3A CS-3B 27 DPWM-4A 28 DPWM-4B 33 SRE-4A 50 SRE-4B 42 FAULT-4A 43 FAULT-4B 68 EAP4 EAN4 69 2 CS-4A 73 CS-4B 77 76 ADDRSEN0 ADDRSEN1 72 71 AUX-IN_AD13 1 AUX-IN_AD14 59 ADC_REF BPCAP B 2 VTRACK 23 VCC2B_FLT 23 26 23 AGND1 9240 2 R147 1 10.0K 1% 1/16W 2 VCC2A_FLT 1 C218 X5R 2 10V 0.068UF R76 6.81K 1% 1/16W 2 R152 1 10.0K 1% 1/16W 2 23 1 2 R149 1 10.0K 1% 1/16W 2 23 VCC2A_SRE 22 210k 158k 115k 84.5k 63.4k 47.5k 36.5k 27.4k 21.5k 16.9k 13.0k 10.2k - GND GNDTAB AGND1 9240 1 R153 10.0K 1% 1/16W VCC2A_PWM VCC1A_CS Open 11 10 9 8 7 6 5 4 3 2 1 0 Short 3 6 1 39 40 TMUX0 54 TMUX1 7 TMUX2 TEMP 23 24 NC 51 37 NC 17 18 64 65 4 78 VCC1_EA_P VCC1_EA_N 22 VCC1B_FLT 22 26 22 2 2 TMUX0 TMUX1 TMUX2 TEMP DPWM-2A DPWM-2B SRE-2A SRE-2B FAULT-2A FAULT-2B EAP2 EAN2 CS-2A CS-2B VCC1A_FLT RPMBus C59 C 21 21 21 21 R246 1.0M 5% 1/16W connections at FPGA 61 60 AGND1 80 AGND2 AGND3 9 34 DGND1 55 DGND2 DGND3 1 22 ADDRSENx Value R286 1.00K 1% 1/16W TI_V3P3 VCC1A_SRE 1 35 20 PMBUS_ALERT 19 PMBUS_DATA 36 PMBUS_CLK PMBUS_CTRL pairs wired back from power plane 2 HDR_BOX_2X5 PMBUS_ALERT PMBUS_DATA PMBUS_CLK PMBUS_CTRL 22 2 DGND1 9240 2,26 4,26 4,26 3,26 VCC1A_PWM 2 2 VIN 21 22 NC 12 11 NC 15 16 62 63 75 79 R293 0 5% 1/16W 2 5 R202 2.0K 5% 1/16W DPWM-1A DPWM-1B SRE-1A SRE-1B FAULT-1A FAULT-1B EAP1 EAN1 CS-1A CS-1B 1 2 PMBus Address = (12 x 4) + 4 = 52 decimal VCCxxxx_EAP/N are remote sense R294 0 5% 1/16W NC NC Example: ADDRSEN1 R=27.4k and ADDRSEN0 R=27.4k U26 1 2 4 6 8 10 1 R201 2.0K 5% 1/16W PMBus Address = 12 × Value(ADDRSEN1) + Value(ADDRSEN0) 1 C395 X7R 2 16V 0.1UF AGND1 9240 R295 0 5% 1/16W 1 3 5 7 9 1 VCC3V3A 1 J1 R203 2.0K 5% 1/16W 1 C393 Y5V 2 16V 4.7UF R296 0 5% 1/16W 1 DGND1 9240 8 V33DIO156 V33DIO257 V33D58 V33A 1 D12 AGND1 9240 DGND1 9240 70 V33FB C63 X5R 2 10V 0.1UF 2 PMBus Connector C61 X5R 2 10V 0.1UF 1 D 1 TI_V3P3 1 C286 X5R 2 10V 4.7UF 1 C397 X5R 2 10V 0.1UF R148 10.0K 1% 1/16W 5.1V 500MW 1 D 1 2 1 1 BZT52C5V1-TP 1 C153 X7R 2 16V 0.1UF 2 1 C130 X5R 2 16V 10UF R141 2.0K 5% 1/16W 1 C249 X7R 2 16V 0.1UF PMBus Address is calculated as follows: 3 1 2 1 FERRITE-220 2 1 FERRITE-220 NC NC NC TI_V3P3 Q11 VCC12_P 2 F268 3 F273 4 DGND1 9240 FPGA UCD9240 PMBus Controller AGND should be a copper island underneath the 9240 and every associated module FPGA PMBus Regulator Shutdown (shuts off regulators) Title: TI UCD9240 Power System SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 1 A Date: 9-24-2009_15:00 Sheet Size: B Sheet 4 3 2 21 of Ver: D Rev: 04 Drawn By 35 BF 1 3 2 R234 1.00K 1% 1/16W 4 D D VCCINT_FPGA 1 C275 1 X7R 2 25V 820PF 2 21 2 VCC1_EA_P 1 21 1 R52 >1.5V = 787 ohms DNP 1% <=1.5V : DNP 1/16W VCC1_EA_N C C INH8 2 0603_SHORT B 21 TEMP1 AGND1 E2 E2 0.005R 1 C242 47UF 2 6.3V TANT 1 C229 330UF 2 10V TANT R43 4.22K 1% 1/16W Z4 E1 E1 1 1W 0.1% I2 I2 2 I1 I1 VCC1_SENSE_P 1 VCCINT @ 10A VCC1_SENSE_N FAULT9 NC VCCINT VCCINT_FPGA 3GND_1 U18 SRE10 VBIAS12 16V ELEC 1 C134 X5R 2 25V 22UF 21 21 21 21,23,24,29,30 R67 VO4 7AGND 2 C235 330UF 6IOUT 1 PTD08A010W 2GND_0 1VI 5TEMP VCC12_P PWM11 VCC1A_PWM VCC1A_SRE VCC1A_FLT PWR_INH VCC5 1RG1 RG28 2VIN_N V_P7 3VIN_P VOUT6 4V_N B VCC1A_CS 21 REF5 U38 INA333 PTD08A010W 10A Max. Power Channel Title: A PTD08A010W 10A Max. Power Channel SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 A Date: 9-18-2009_15:03 Sheet Size: B Sheet 4 3 2 22 of Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 D R240 2.2K 5% 1/16W D 1 C276 1 X7R 2 25V 820PF 2 21 R26 1.8K 5% 1/16W 2 VCC2_EA_P 1 21 VCC2V5_FPGA >1.5V = 787 ohms <=1.5V : DNP VCC2_EA_N C C INH8 0603_SHORT TEMP2 AGND2 C243 47UF 2 C230 330UF 2 10V TANT R44 4.22K 1% 1/16W 6.3V TANT 1 2 2 1 E2 E2 0.005R 1 Z5 E1 E1 VCC2_SENSE_N 1W 0.1% I2 I2 VCC2_SENSE_P FAULT9 VCC2V5 @ 10A I1 I1 VO4 1 21 VCC2V5 VCC2V5_FPGA NC B 21 21 21 21,22,24,29,30 R68 3GND_1 U19 7AGND 16V ELEC 1 C135 X5R 2 25V 22UF 6IOUT 2 C236 330UF 5TEMP 1 PTD08A010W 2GND_0 1VI SRE10 VBIAS12 VCC12_P PWM11 VCC2A_PWM VCC2A_SRE VCC2A_FLT PWR_INH VCC5 B 1RG1 RG28 2VIN_N V_P7 3VIN_P VOUT6 4V_N VCC2A_CS 21 REF5 U39 INA333 PTD08A010W 10A Max. Power Channel Title: A PTD08A010W 20A Max. Power Channel SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 A Date: 9-18-2009_15:03 Sheet Size: B Sheet 4 3 2 23 of Ver: D Rev: 04 Drawn By 35 BF 1 3 2 R235 1.00K 1% 1/16W 1 C277 1 X7R 2 25V 820PF 2 21 VCC3A_PWM VCC3A_SRE VCC3A_FLT PWR_INH INH8 21 21 21 21,22,23,29,30 C Z6 0603_SHORT TEMP3 2 E1 E1 1 E2 E2 2 6.3V TANT 1 C231 330UF 2 10V TANT R45 4.22K 1% 1/16W 0.005R C244 47UF 1 3GND_1 1W 0.1% 1 AGND3 B VCCAUX @ 10A I2 I2 2 I1 I1 VCC3_SENSE_N FAULT9 SRE10 >1.5V = 787 ohms <=1.5V : DNP VCCAUX NC 21 R54 787 1% 1/16W R65 VO4 7AGND U20 PWM11 VBIAS12 16V ELEC 1 C136 X5R 2 25V 22UF 6IOUT 2 C237 330UF 5TEMP 1 PTD08A010W 2GND_0 1VI D VCC3_EA_N C VCC12_P VCCAUX VCC3_EA_P 1 21 1 2 D VCC3_SENSE_P 4 VCC5 1RG1 RG28 2VIN_N V_P7 3VIN_P VOUT6 4V_N VCC3A_CS B 21 REF5 U40 INA333 PTD08A010W 10A Max. Power Channel Title: A PTD08A010W 10A Max. Power Channel SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 A Date: 9-24-2009_15:00 Sheet Size: B Sheet 4 3 2 24 of Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 4C VCC12_P Q1 MJD200 3E 1B D D IN_P U36 TS321IDBVR VCC3V3 R243 1.3K 5% 1/16W 5 + - IN_N 4 1 1 2 1 C253 X5R 2 16V 1UF R237 1.00K 1% 1/16W 2 3 2 1 U7 2 3 FAN_TACH 21 J42 C 1 R155 10.0K 1% 1/16W DS9 LED-GRN-SMT TI_V3P3 1 R140 200 5% 1/16W 2 1 C65 X5R 2 10V 0.1UF VCC_N VCC_P 2 3 2 FAN_PWM 1 21 2 OUT 1 R2 33.2K 1% 1/16W 1 21 TI_PWRGOOD 1 26 MGT_TI_PWRGOOD 2 N 7 G1 1 NDS331N C 2 UCD9420 Fan Circuit SN74LVC2G08DCU VCC2V5 8 1 C64 0.1UF 2 10V X5R VCC12_P J18 DPDT 1 12V 12V N/C N/C NC 6 U7 G2 NC 3 4 NC 2 SP605 Power Good 3 4 4 2 NC NC 1 5 6 5 NC 2 3 R236 1.00K 1% 1/16W SN74LVC2G08DCU 1201M2S3ABE2 B B 1 39-30-1060 DS14 SW2 6 LED-GRN-SMT COM VCC12_P_IN 5 2 COM 1 NC ATX Peripheral Cable J27 1 12V 2 COM 12V Power Jacks, 12V Fan 3 COM 4 5V NC Title: A 350211-1 TI UCD9240 Power System SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 A Date: 9-24-2009_15:00 Sheet Size: B Sheet 4 3 2 25 of Ver: D Rev: 04 Drawn By 35 BF 1 Q12 MGT_TI_V3P3 DGND2 9240 C 2 R159 1 10.0K 1% 1/16W 2 R162 1 10.0K 1% 1/16W 2 R157 1 10.0K 1% 1/16W 2 R160 10.0K 1% 1/16W 39 40 TMUX0 54 TMUX1 7 TMUX2 TEMP NC 6 13 MGT_TI_RESET_B J13 1 1 C288 X5R 2 10V 4.7UF 2 J6 1 2 3 4 MGT_TI_TCK MGT_TI_TMS MGT_TI_TDI MGT_TI_TDO DNP 44 47 46 45 NC 14 48 MGT_TRST_B 2 DNP J11 DNP J12 2 VTRACK /RESET TCK TMS TDI TDO TRCK /TRST 1 1 1 2 R27 36.5K 1% 1/16W 1 2 R171 1 27.4K 1% 1/16W2 R156 1 10.0K 1% 1/16W 2 R284 10.0K 1 1% 1/16W 2 C66 X5R 10V 0.1UF C68 1 X5R 2 10V 2 0.1UF 1 C155 X7R 16V 0.01UF 1 AGND2 9240 NC NC NC NC NC DGND2 9240 Z2 VCC1B_FLT 21 NC NC MGT_VCC1A_CS VCC2B_FLT Open 11 10 9 8 7 6 5 4 3 2 1 0 Short 210k 158k 115k 84.5k 63.4k 47.5k 36.5k 27.4k 21.5k 16.9k 13.0k 10.2k - Note: 21 NC NC Do not use PMBus Addresses 0, 1, 2, 3, 12, 126 or 127 AGND2 9240 C 29 MGT_VCC3A_SRE 29 MGT_VCC3A_FLT VCC3B_FLT MGT_VCC3_EA_P MGT_VCC3_EA_N 29 21 29 29 27 28 NC 33 50 NC 42 43 68 69 2 73 MGT_VCC4A_PWM SYNC-IN SYNC-OUT FAN-PWM FAN-TACH 31 30 53 32 PWRGOOD DIAG-LED 49 10 NC 2 27 1 C323 X7R 2 25V 6800PF MGT_VCC3A_PWM 0603_SHORT AGND2 9240 connections at FPGA 25 DPWM-3A 26 NC DPWM-3B 38 SRE-3A 52 NC SRE-3B 29 FAULT-3A 41 FAULT-3B 66 EAP3 EAN3 67 3 CS-3A 74 CS-3B DPWM-4A DPWM-4B SRE-4A SRE-4B FAULT-4A FAULT-4B EAP4 EAN4 CS-4A CS-4B 77 76 ADDRSEN0 ADDRSEN1 72 71 AUX-IN_AD13 1 AUX-IN_AD14 59 ADC_REF BPCAP B 23 24 51 37 17 18 64 65 4 78 pairs wired back from power plane RPMBus C70 2 1 R163 10.0K 1% 1/16W NC NC NC NC NC 61 60 AGND1 80 AGND2 AGND3 9 34 DGND1 55 DGND2 DGND3 1 MGT_TMUX0 MGT_TMUX1 MGT_TMUX2 MGT_TEMP XREF=26 VCCxxxx_EAP/N are remote sense 21 DPWM-1A 22 DPWM-1B 12 SRE-1A 11 SRE-1B 15 FAULT-1A 16 FAULT-1B 62 EAP1 EAN1 63 75 CS-1A 79 CS-1B DPWM-2A DPWM-2B SRE-2A SRE-2B FAULT-2A FAULT-2B EAP2 EAN2 CS-2A CS-2B MGT_TI_V3P3 26 26 26 U27 ADDRSENx Value MGT_VCC3V3A MGT_VCC3A_CS 29 X5R 2 10V 0.1UF 35 20 PMBUS_ALERT 19 PMBUS_DATA 36 PMBUS_CLK PMBUS_CTRL AGND2 9240 2 VIN MGT_VCC3V3A D 1 PMBUS_ALERT PMBUS_DATA PMBUS_CLK PMBUS_CTRL Example: ADDRSEN1 R=27.4k and ADDRSEN0 R=27.4k 2 DGND2 9240 2,21 4,21 4,21 3,21 PMBus Address = 12 × Value(ADDRSEN1) + Value(ADDRSEN0) PMBus Address = (12 x 4) + 4 = 52 decimal DGND2 9240 5 1 C396 X7R 2 16V 0.1UF R276 1.00K 1% 1/16W D10 2 AGND2 9240 1 C394 Y5V 2 16V 4.7UF 1 1 C69 X5R 2 10V 0.1UF C67 X5R 2 10V 0.1UF 1 R238 1.00K 1% 1/16W R158 10.0K 1% 1/16W 1 1 C289 X5R 2 10V 4.7UF 1 C398 X5R 2 10V 0.1UF 1 2 2 1 2 1 2 1 D R164 10.0K 1% 1/16W 8 V33DIO156 V33DIO257 V33D58 V33A 1 5.1V 500MW 1 C251 X7R 2 16V 0.1UF BZT52C5V1-TP 1 C131 X5R 2 16V 10UF R142 2.0K 5% 1/16W 1 C399 X7R 2 16V 0.1UF PMBus Address is calculated as follows: 3 1 2 1 FERRITE-220 2 1 FERRITE-220 70 V33FB VCC12_P 2 F276 3 F307 4 U3 30 MGT_VCC4A_SRE 30 MGT_VCC4A_FLT VCC4B_FLT MGT_VCC4_EA_P MGT_VCC4_EA_N 30 21 30 30 1 C259 X7R 2 25V 6800PF NC 1 A4 VCC NC 2 A6 A2 15 NC 3 A A1 14 MGT_TEMP2 30 NC 4 A7 A0 13 MGT_TEMP1 29 NC 5 A5 A3 12 NC 6 E_B S0 11 MGT_TMUX0 26 7 VEE S1 10 MGT_TMUX1 26 S2 9 MGT_TMUX2 26 26 MGT_TEMP AGND2 9240 1 C221 X5R 2 10V 0.068UF NC NC NC NC 8 MGT_TI_PWRGOOD 25 GND 16 AGND2 9240 B CD74HC4051 AGND2 9240 UCD9240PFC AGND2 9240 1 Z7 2 0603_SHORT DGND2 9240 FPGA UCD9240 PMBus Controller AGND should be a copper island underneath the 9240 and every associated module Title: A TI UCD9240 Power System SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 A Date: 9-24-2009_15:00 Sheet Size: B Sheet 4 3 2 26 of Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 D D VCC3V3 1 R273 200 5% 1/16W 2 2 DS19 1 LED-GRN-SMT 1 Q13 C B 3 E 2 3904 C C MMBT3904 TPS74401 VCC1V5 PG EN VOUT_1 VOUT_18 VOUT_19 VOUT_20 I1 I1 1 18 19 20 1 15 SS GND_12 GND_TAB NC_17 NC_14 NC_13 NC_2 NC_3 NC_4 12 21 17 14 13 2 3 4 U51 1 C322 1000PF 2 X7R 50V 2 FB 16 R271 2.49K 1% 1/16W AUX_FB 1 2 R274 4.99K 1% 1W 0.1% I2 I2 E1 E1 E2 E2 0.005R 1.2V @ 3A 1 C318 10UF 2 10V X5R 1 C297 0.1UF 2 10V X5R B 2 BIAS 11 MGT_AVCC R270 TI R259 4.22K 1% 1/16W 10 MGT_POWERGOOD 1 1 C296 0.1UF 2 10V X5R 9 MGT_VCC1_SENSE_N 1 C295 0.1UF 2 10V X5R AUX_SS 1 C302 X5R 2 10V 1UF VIN_5 VIN_6 VIN_7 VIN_8 MGT_VCC1_SENSE_P 5 6 7 8 VCC5 VCC5 1RG1 RG28 2VIN_N V_P7 3VIN_P VOUT6 4V_N MGT_VCC1A_CS 26 B REF5 U50 INA333 TPS74401 3A Max MGT Power Title: A TPS74401 3A Max MGT Power SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 A Date: 1-7-2010_17:04 Sheet Size: B Sheet 4 3 2 27 of Ver: D Rev: 04 Drawn By 35 BF 1 1 C303 0.01UF 2 16V X7R 1 C319 10UF 2 X5R 10V 1 C325 33PF 2 50V NPO 1 C304 0.01UF 2 16V X7R 2 R261 DNP 1% 1/16W VDD8 SFPCLK_XTAL_OUT 3XTAL_OUT SFPCLK_XTAL_IN 4XTAL_IN Q07 SFPCLK_QO_C_P NQ06 SFPCLK_QO_C_N OE5 U47 25.000MHZ GND_SFPCLK GND_SFPCLK SFPCLK_QO_P 6 SFPCLK_QO_N 6 D C298 1 0.1UF 10V 2 X5R 2 1 1 VDD_SFPCLK 2GND X4 1 C299 1 0.1UF 10V 2 X5R VDDA_SFPCLK ICS844021I 1VDDA 1 C324 33PF 2 50V NPO VDDA_SFPCLK R27210 5% 1 F195 1 D VDD_SFPCLK 2 2 VCC3V3 2 F194 3 FERRITE-220 FERRITE-220 4 125.00 MHz Clock SFP Clock - 125MHz GND_SFPCLK C C 2 2 19VDDO NC12 NC 18Q NC23 NC NC 17NQ NC34 16NC5 MR5 NC 15NC4 BW_SEL6 14GND F_SEL17 R268 DNP 1% 1/16W 13NCLK 12 CLK 12 PCIE_CLK_QO_N 2 R290 100 5% 1/16W 1 2 B VDDA8 F_SEL09 11 OE 1 VDD10 U48 R266 DNP 1% 1/16W 1 ICS874001 2 PCIE_CLK_QO_P VCC3V3 10UF 2 6.3V X5R 1 C320 0805 R263 1 DNP 1% 1/16W2 1/16W 5% 12 2 R262 4.7K 1 2 R256 DNP 1% 1/16W 1 1 2 2 R255 DNP 1% 1/16W 1 2 1/16W 5% 2 R267 DNP 1% 1/16W 1 PLL_SEL1 NC PCIE_250M_MGT1_C_N 1 20NC6 1 R254 4.7K 1 C300 0.1UF 2 10V X5R PCIE_250M_MGT1_C_P B R265 DNP 1% 1/16W 1/16W 5% PCIE_250M_N 2 R257 4.7K 6 PCIE_250M_P NC 1 C301 0.1UF 2 10V X5R 6 1 1/16W 5% 2 R269 1 10 5% 1/16W2 1/16W 5% 1 1/16W 5% 1 R264 4.7K R253 4.7K VCC3V3 R258 4.7K VCC3V3 1 C306 1 C305 0.01UF 0.01UF 2 X7R 2 X7R 16V 16V MGT Clocks Title: A MGT Clocks SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 A Date: 9-24-2009_15:30 Sheet Size: B Sheet 4 3 2 28 of Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 D R239 1.00K 1% 1/16W D VCC1V5_FPGA 1 C278 1 X7R 2 25V 820PF 2 26 R53 DNP 1% 1/16W 2 MGT_VCC3_EA_P 1 26 >1.5V = 787 ohms <=1.5V : DNP MGT_VCC3_EA_N C C MGT_VCC3A_PWM MGT_VCC3A_SRE MGT_VCC3A_FLT PWR_INH 26 26 26 21,22,23,24,30 INH8 0603_SHORT 26 MGT_TEMP1 2 1 E2 E2 0.005R C245 47UF 2 6.3V TANT 1 C232 330UF 2 10V TANT 2 Z8 E1 E1 R46 4.22K 1% 1/16W 1W 0.1% 1 1 VCC1V5_FPGA I2 I2 MGT_VCC3_SENSE_N 3GND_1 NC B I1 I1 MGT_VCC3_SENSE_P FAULT9 VCC1V5 @ 10A R66 VO4 7AGND U21 SRE10 VBIAS12 16V ELEC 1 C137 X5R 2 25V 22UF 6IOUT 2 C239 330UF 5TEMP 1 PTD08A010W 2GND_0 1VI PWM11 VCC1V5 VCC12_P VCC5 B AGND7 1RG1 RG28 2VIN_N V_P7 3VIN_P VOUT6 4V_N MGT_VCC3A_CS 26 REF5 U41 INA333 PTD08A010W 10A Max. Power Channel Title: A PTD08A010W 10A Max. Power Channel SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 A Date: 9-18-2009_15:03 Sheet Size: B Sheet 4 3 2 29 of Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 D R241 2.2K 5% 1/16W D 1 C279 1 X7R 2 25V 820PF 2 26 2 MGT_VCC4_EA_P 1 26 VCC3V3 R248 1.6K >1.5V = 787 ohms 5% <=1.5V : DNP 1/16W MGT_VCC4_EA_N C C U22 INH8 FAULT9 VCC3V3 3GND_1 16V ELEC 26 26 26 21,22,23,24,29 VCC3V3 @ 10A VO4 7AGND 2 1 C138 X5R 2 25V 22UF 6IOUT C240 330UF 5TEMP 1 PTD08A010W 2GND_0 1VI SRE10 VBIAS12 VCC12_P PWM11 MGT_VCC4A_PWM MGT_VCC4A_SRE MGT_VCC4A_FLT PWR_INH NC 1 1 2 Z9 C246 47UF 6.3V TANT 1 C233 330UF 2 10V TANT 2 0603_SHORT B 26 B MGT_TEMP2 AGND8 PTD08A010W 10A Max. Power Channel Title: A PTD08A010W 10A Max. Power Channel SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 A Date: 9-18-2009_15:03 Sheet Size: B Sheet 4 3 2 30 of Ver: D Rev: 04 Drawn By 35 BF 1 4 3 2 1 VCC2V5 1 DDR3 Power Good 2 R3 27.4 1% 1/16W VCC2V5 VCC1V5 2 3 4 1 C208 Y5V 2 10V 10UF 1 C209 Y5V 2 10V 10UF 1 C205 Y5V 2 10V 10UF 5 REFIN VLDOIN VO PGND VOSNS U11 2 1 2 VTTVREF 3 1 C290 X5R 2 10V 4.7UF R204 100K 5% 1/16W TL1963A-18DCQR SOT223-6 3 Q9 1 SHDN_N IN GND2 SNS_ADJ GND1 OUT VCC1V8 6 5 4 U44 1 C158 0.01UF 2 16V X7R NDS331N 2 2 1 R166 10.0K 1% 1/16W 1 2 1 TPS51200DRCT 10 VIN 9 PGOOD 8 GND 7 EN 6 REFOUT VCC1V8 @ 500mA 1 C165 1 C159 X5R 0.01UF 2 6.3V 2 16V 1UF X7R 1 VCC2V5 DS15 1 C222 X7R 2 50V 1000PF 1 1 C207 Y5V 2 10V 10UF LED-GRN-SMT VCC3V3 VTTDDR 1 C206 Y5V 2 10V 10UF D 2 R165 10.0K 1% 1/16W D PWRPAD 11 1 C166 X5R 2 6.3V 1UF C71 X5R 2 10V 0.1UF 1 C C VCCINT_FPGA, VCCAUX Power Probe Channels VCCINT_FPGA VCC2V5 VCC3V0 VCC5 1 1 U49 J51 8 J52 MGT Power Probe Channel C321 22UF 16V TANT 5 1 2 2 NC 3.0V @ 500mA OUT 1 IN SHDN ADJ 4 BYP GND3 3 1 GND6 6 GND7 7 2 R277 1 38.3 1% 1/16W 2 C317 3.3UF 25V TANT ROOMLT1763CS8 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 B MGT_AVCC 2 B CON_SMA_SCREW_ON DNP J53 3 2 1 DNP VCC2V5 1 VCCINT_FPGA J29 1 DNP R275 26.1 1% 1/16W J54 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DDR3 Termination Regulator, power prob Title: A DNP DNP DDR3 Termination Regulator SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 A Date: 9-24-2009_15:00 Sheet Size: B Sheet 4 3 2 31 of Ver: D Rev: 04 Drawn By 35 BF 1 8 7 6 5 4 3 2 The Embedded USB JTAG Download circuit on this page is for reference only! This circuit should not be designed into an end customer product or solution. Xilinx will not provide support on this embedded USB JTAG Download circuit. VCC3V3 U28 H 1 2 R178 1 10K 5% 1/16W 2 H R179 10K 5% 1/16W 2 PLACES VCC3V3 9 AVCC 86 PE0_T0OUT PORT E TARGET INTERFACE CONNNECTIONS AGND PA3_WU2 PA2_SLOE PORT A PA1_INT1 PA0_INT0 69 VREF_DETECT 68 LED_RED 67 LED_GRN FROM 33 72 BUFFER_OE 61 73 LAST_WORD 58 74 JTP_CMD3 24 34 GPIF_D00 32 35 GPIF_D01 33 36 GPIF_D02 34 37 GPIF_D03 35 44 GPIF_D04 36 45 GPIF_D05 37 46 GPIF_D06 39 47 GPIF_D07 40 VERSION TAP_STATE1 TMS_LEVEL TAP_STATE2 BUFFER_OE TAP_STATE3 LAST_WORD IDLE_FLAG EXTEND SPARE_P065 PB0_FD0 USB CONNECTOR PB1_FD1 PB2_FD2 PB3_FD3 PORT B USB TYPE B NOTE: EMBEDDED VERSION PB4_FD4 PB5_FD5 IS NOT BUS POWERED PB6_FD6 PB7_FD7 GPIF_D00 SPARE_P073 GPIF_D01 SPARE_P074 GPIF_D02 SPARE_P076 GPIF_D03 SPARE_P077 GPIF_D05 TCK_CCLK D_N D_P ID SHLD1 SHLD2 SHLD3 SHLD4 GND PD0_FD8 3 17 4 D- PD1_FD9 D+ PD2_FD10 NC PD3_FD11 PORT D 5 PD4_FD12 6 7 8 9 PD5_FD13 J4 PD6_FD14 PD7_FD15 80 GPIF_D08 41 81 GPIF_D09 42 82 GPIF_D10 43 83 GPIF_D11 44 95 GPIF_D12 46 96 GPIF_D13 49 97 GPIF_D14 50 98 GPIF_D15 52 54 BIT_CLOCK 22 GPIF_D10 TDI_DIN CTL2_FLAGC CTL3 CTL4 CTL5 GPIF_START 53 CTRL2 54 51 CTRL3 55 65 NC 71 NC 73 NC 74 NC 76 NC 77 NC 3 PLACES VCC3V3 R190 10K 5% 1/16W 1 R189 10K 5% 21/16W 1 2 R197 20K 5% 1/16W 2 FPGA_TCK USBHDR_TCK_R 66 1 JTAG_TCK 7 F USBHDR_TMS_R 67 JTAG_TMS 7 USBHDR_TDI_R 68 JTAG_TDI 7 GPIF_D12 GPIF_D13 INIT_OUT 70 GPIF_D14 GPIF_D15 BIT_CLOCK SPARE_P079 SPARE_P082 56 NC GPIF_D11 SPARE_P081 55 72 GPIF_D09 SPARE_P080 CTL1_FLAGB NC START SPARE_P085 CTRL1 SPARE_P086 CTRL2 SPARE_P087 52 NC BANK 1 78 NC 79 NC 80 NC 81 NC 82 NC 85 NC 86 NC 87 NC E VCC3V3 3.3V INTERFACE TO LOCAL JTAG OR SLAVE-SERIAL DEVICE CHAIN. BANK 2 FOR LONG CHAINS OR TRACES, DISTRIBUTE EMBEDDED_TCK 76 NC VCCINT VAUX VCCIO1 VCCIO2 PART_NUMBER=CY7C68013A TQFP100 NO CONNECTION GPIF_D08 E GPIF 12 EMBEDDED_INIT GPIF_D07 SPARE_P078 CTL0_FLAGA NC GPIF_D06 TMS_PROG 18 NC 11 GPIF_D04 USB_MINI_B NC 13 2 60 LAST DEVICE TDO 2 PA6_PKTEND 56 TMS_LEVEL NC 2 PA5_FIFOADR1 VERSION_REQUEST 71 FIRST DEVICE TDI R56 15 5% 1/16W PA4_FIFOADR0 88 1 JTAG_TDO 1 XTALOUT PE2_T2OUT PORT A 2 TMS ALL DEVICES G SPARE_P071 VBUS FPGA_TMS R57 15 5% 1/16W 2 R120 2 PORT E PA7_FLAGD 1 TCK ALL DEVICES USB_HEADER_TDI XC2C256 1 1 Y1 1 TAP_STATE0 1 C263 NPO 2 50V 11PF F FPGA_TCK U24 33 24MHZ 10 JTAG XTALIN G 1 C264 NPO 2 50V 11PF TO N/C R58 15 5% 1/16W 11 70 NC 1 2 C72 X5R 2 10V 0.1UF 1 1% C132 3.3UF 10V 33 4.75K 1 SERIAL_NUMBER 87 PE1_TIOUT 12 RECEPTACLE 1 VCC1V8;26,57 VCC3V3;5 VCC3V3;20,38,51 VCC3V3;88,98 R195 20K 5% 1/16W BANK 1 GND;21,25,31,62 GND;69,75,84,100 INIT_IN AND EMBEDDED_TMS WITH LVDS BUFFERS. 1 2 EMBEDDED_INIT 28 D D BANK 1 PC0_GPIFADR0 PC1_GPIFADR1 PC2_GPIFADR2 PC3_GPIFADR3 PORT C NC NC VCC3V3 NC 32 PC4_GPIFADR4 WR 31 PC5_GPIFADR5 RD 28 PC6_GPIFADR6 BKPT PC7_GPIFADR7 57 COUNT0 14 58 COUNT1 15 59 COUNT2 16 60 COUNT3 17 61 COUNT4 18 62 JTP_CMD0 19 63 JTP_CMD1 29 64 JTP_CMD2 30 BANK 2 COUNT0 SPARE_P089 COUNT1 SPARE_P090 COUNT2 SPARE_P091 COUNT3 SPARE_P092 COUNT4 SPARE_P099 2 100 CLKOUT R180 10K 5% 1/16W IFCLK TDO_SAMPLE_CLK 23 84 PE3_RXD0OUT INT5 1 R187 1 10K 5% 1/16W2 23 2 22 24 R186 1 10K 5% 1/16W 2 25 TDO_SAMPLE_CLOCK LAST_BIT 26 BUS_ENABLE PE4_RXD1OUT INT4 PORT E PE6_T2EX T0 PE5_INT6 T1 PE7_GPIFADR8 89 CPLD_TCK 90 CPLD_TMS 92 CPLD_TDI 91 CPLD_TDO 93 SPARE_COM 33 B1 48 R185 1 10K 5% 1/16W 2 41 B1 47 B1 45 B1 83 33 99 NC 10 NC 4 NC 2 NC VCC3V3 R196 20K 5% 1/16W 33 33 9 43 RDY0 TXD0 RDY1 RXD1 RDY2 GPIF RDY3 TDO DOWN_CNT0 SPARE_COM BANK 2 R182 10K 5% 1/16W RDY5 USB_SCL 29 USB_SDA 30 SCL VCCINT VCC3V3;1,16,20,33,38 VCC3V3;49,53,66,78,85 NC1 SDA NC2 GND;65,75,94,99 GND;2,19,21,39,48,50 NC3 63 RDY1 64 DOWN_CNT1 5 RDY2 59 6 7 8 13 NC 77 RESET RESERVED DONE_SM0 RDY1 DONE_SM1 RDY2 DONE_SM2 JTAG_TDO 20 97 NC 96 NC 95 NC 94 NC 93 NC 3 NC 6 NC 7 NC LEGEND: DONE_INH 8 BANK 2 VQFP100 B1 1 2 3 PLACES R177 10K 5% 1/16W OPTIONAL NETS ROUTED IN PARALLEL TO LOCAL 2MM CABEL CONNECTOR J1. R181 10K 5% 1/16W P PARALLEL TO SERIAL CONVERTER 15 NC 1 27 BANK 1 VCC3V3 14 NC 2 WAKEUP DONE 1 R175 1 R176 R174 10K 5% 1/16W RDY4 GPIF_DONE 4 2 TDI 1 TXD1 3 2 42 RXD0 2 R183 1 10K 5% 1/16W2 40 1 C TDO_B TMS T2 2 R184 1 10K 5% 1/16W 2 NC POR NC BANK 1 TCK DOWN_CNT4 NC 33 NC 92 JTP_CMD2 DOWN_CNT2 6 PLACES 33 91 JTP_CMD1 DOWN_CNT3 33 NC TAP C B NC 90 JTP_CMD0 SHIFT_CLK 1 89 B COMPONENTS TO BE LOADED FOR THE PRODUCTION ASSEMBLY VERSION ONLY. E OPTIONAL COMPONENTS THAT SUPPORT DEBUG AND/OR DIAGNOSTICS. 79 27 NOTE: 1 2 R188 10K 5% 1/16W MAKE PARALLEL CONNECTIONS TO J1 (OPTION B) AT EACH OF THE NETS MARKED B1 TO FACILITATE FASTER IN-CIRCUIT Embedded USB JTAG: PCB P/N: SCH P/N: Test P/N: ART P/N: USB Controller, CPLD RE-PROGRAMMING OF THE CPLD DURING BOARD TEST. USB CONTROLLER 0431534 0381305 TSS0123 1280473 J1 DOES NOT NEED TO BE POPULATED DURING PRODUCTION, BUT THE Drawing Number: A ASSEMBLY FOOTPRINT IS RECOMMENDED FOR THE PWB LAYOUT. 0381242 A Date: 14-JUNE-2006 Sheet Size: D Sheet LAST REVISION: 9-24-2009_15:56 8 7 6 5 4 3 2 32 of Ver: C Rev: 04 Drawn By 35 SCHWEIGLER 1 8 7 6 5 4 3 2 1 The Embedded USB JTAG Download circuit on this page is for reference only! This circuit should not be designed into an end customer product or solution. Xilinx will not provide support on this embedded USB JTAG Download circuit. DEFAULT PID/VID EEPROM H STATUS LEDS (OPTION A) H LED_GRN 32 VCC3V3 32 LED_RED U33 24LC00T-SN I2C EEPROM 3 NC 7 2 2 1 2 E R145 2.0K 5% 1/16W R244 360 5% 1/16W 1 1 2 2 E R245 270 5% 1/16W NC NC SCL 6 USB_SCL NC SDA 5 USB_SDA 32 32 EMBEDDED VENDOR ID 0x004B4 0x03FD PRODUCT ID 0x8613 0x000D STATUS LED G 3 XILINX DEFAULT G CYPRESS DATA FIELD 2 E R P 1 LOW POWER BOOT CONDITIONS DS10 SOT23_LUMEX GND 4 G 2 NC VCC 8 NC E R198 20K 5% 1/16W 1 2 1 R217 0 5% 1/16W 1 NC R144 2.0K 5% 1/16W SSL-LX15IGC NC 1 USE FILE 1080058 (HEX) TO PROGRAM THE I2C PROM PRIOR TO ASSEMBLY. F F POWER-ON RESET PC4 JTAG CONNECTOR (OPTION B) VCC3V3 J26 U35 VCC3V3 VTST 5 VCC 3 RESET 1 POR MR R205 100K 1% 1/16W 1 C160 0.01UF 2 X7R 16V E 2 2 VREF MAX6412UK22 GND SRT POWER SUPERVISORY 32 6 CPLD_TCK TMS 4 CPLD_TMS 10 INIT 14 2 TDO 8 GTST 1 GND 3 GND 5 GND 7 GND 9 1 C262 X7R 2 50V 1800PF PRODUCES 5MS POWER-ON RESET DNP NC TCK TDI 1 4 NOTE: 12 GND 11 GND 13 32 32 CPLD_TDI 32 NC CPLD_TDO 32 E E TSM_107_01_L_DV D D BYPASS CAPACITORS ELECTRONIC SERIAL NUMBER C C VCC3V3 VCC3V3 C83 X5R 2 10V 0.1UF C84 X5R 2 10V 0.1UF 1 1 C85 X5R 2 10V 0.1UF 1 C86 X5R 2 10V 0.1UF 1 C87 X5R 2 10V 0.1UF 1 C88 X5R 2 10V 0.1UF 1 C89 X5R 2 10V 0.1UF 1 C90 X5R 2 10V 0.1UF 1 1 C170 3.3UF 2 25V TANT VCC3V3 1 2 VCC3V3 VCC1V8 32 R143 2.0K 5% 1/16W U13 SERIAL_NUMBER 6 VCC NC 2 I/O NC 1 GND NC 3 NC 4 NC 5 NC DS2411 C73 X5R 2 10V 0.1UF B C74 X5R 2 10V 0.1UF 1 1 C75 X5R 2 10V 0.1UF 1 C76 X5R 2 10V 0.1UF 1 C77 X5R 2 10V 0.1UF 1 C78 X5R 2 10V 0.1UF 1 C79 X5R 2 10V 0.1UF 1 C80 X5R 2 10V 0.1UF 1 C81 X5R 2 10V 0.1UF 1 C82 X5R 2 10V 0.1UF 1 B Embedded USB JTAG: IIC, POR, Decoupling, LED, JTAG Header, Serial Number Drawing Number: A PCB P/N: SCH P/N: Test P/N: ART P/N: 0381242 0431534 0381305 TSS0123 1280473 A Date: 14-JUNE-2006 Sheet Size: D Sheet LAST REVISION: 9-24-2009_15:00 8 7 6 5 4 3 2 33 of Ver: C Rev: 04 Drawn By 35 SCHWEIGLER 1 4 3 2 MSTK1 1 0250446 D D PCIE MSO2 PL1 POWER MRB3 MN1 MS1 NUT_SS_4-40 RUBBER_BUMPER MACHINE_SCREW_SS_PHILHD_4-40_X_3-8 MSO5 MRB5 MN5 MS5 MJS2 NUT_SS_4-40 RUBBER_BUMPER MACHINE_SCREW_SS_PHILHD_4-40_X_3-8 MSO3 PB1 MRB2 MN3 MS4 12v Power Brick C C MJS1 NUT_SS_4-40 RUBBER_BUMPER MACHINE_SCREW_SS_PHILHD_4-40_X_3-8 3650017 MRB1 MSO1 MN2 MS2 CBL1 110V Prong NUT_SS_4-40 MACHINE_SCREW_SS_PHILHD_4-40_X_3-8 MSO4 MS3 MRB4 MN4 Power Cord NUT_SS_4-40 MACHINE_SCREW_SS_PHILHD_4-40_X_3-8 Power Brick RUBBER_BUMPER RUBBER_BUMPER MX1 1 CBL2 USB A OE VCC 8 USB Mini-B B OSC 4 MH7 OUT 5 MBH2100H-27.000MHZ USB Mini-B Cable 1 1 MH_125_250 MH6 MH_125_250 MH5 1 MH_125_250 GND B Half Size Oscillator MH9 SFP_BOT_CAGE 1 1 MH_125_250 MH8 MH_125_250 CG1 Mechanical Components PB2 MJB1 MJB3 MJB4 SFP_TOP_CAGE MJB2 Title: A JUMPER_BLOCK_2-PIN JUMPER_BLOCK_2-PIN JUMPER_BLOCK_2-PIN JUMPER_BLOCK_2-PIN Mechanical Components SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: SCH P/N: Test P/N: ART P/N: 0431534 0381305 TSS0123 1280473 A Date: 9-25-2009_10:34 Sheet Size: B Sheet 4 3 2 34 of Ver: D Rev: 04 Drawn By 35 BF 1 4 3 VCC1V5_FPGA 2 VCC2V5 1 VCC1V5_FPGA VCC3V3 U14 5 5 5 5 5 5 SYSACE_MPBRDY_LS SYSACE_MPIRQ_LS SYSACE_MPCE_LS SYSACE_MPA06_LS SYSACE_MPA05_LS SYSACE_MPA04_LS NC NC 2 1 3 4 5 6 7 8 9 10 U52 VCCA A1 A2 A3 A4 A5 A6 A7 A8 OE VCCB B1 B2 B3 B4 B5 B6 B7 B8 GND 19 20 18 17 16 15 14 13 12 11 SYSACE_MPBRDY SYSACE_MPIRQ SYSACE_MPCE SYSACE_MPA06 SYSACE_MPA05 SYSACE_MPA04 5 5 5 5 5 GPIO_HEADER_0_LS GPIO_HEADER_1_LS GPIO_HEADER_2_LS GPIO_HEADER_3_LS PCIE_PERST_B_LS NC NC NC NC NC TXB0108 VCCA A1 A2 A3 A4 A5 A6 A7 A8 OE VCCB B1 B2 B3 B4 B5 B6 B7 B8 GND 1 VCC1V5_FPGA D 19 20 18 17 16 15 14 13 12 11 TXB0108 C91 X5R 2 10V 0.1UF 1 X5R 2 10V 0.1UF 2 1 3 4 5 6 7 8 9 10 C385 C96 1 20 20 20 20 20 20 GPIO_HEADER_0 GPIO_HEADER_1 GPIO_HEADER_2 GPIO_HEADER_3 PCIE_PERST_B 14 14 14 14 12 NC NC NC 1 C384 X5R 2 10V 0.1UF X5R 2 10V 0.1UF D VCC2V5 C C U15 5 5 5 5 5 5 5 5 2 1 3 4 5 6 7 8 9 10 SYSACE_D7_LS SYSACE_D6_LS SYSACE_D5_LS SYSACE_D4_LS SYSACE_D3_LS SYSACE_D2_LS SYSACE_D1_LS SYSACE_D0_LS VCCA A1 A2 A3 A4 A5 A6 A7 A8 OE VCCB B1 B2 B3 B4 B5 B6 B7 B8 GND 19 20 18 17 16 15 14 13 12 11 SYSACE_D7 SYSACE_D6 SYSACE_D5 SYSACE_D4 SYSACE_D3 SYSACE_D2 SYSACE_D1 SYSACE_D0 TXB0108 C93 X5R 2 10V 0.1UF 1 X5R 2 10V 0.1UF C92 1 20 20 20 20 20 20 20 20 B B VCC1V5_FPGA VCC2V5 U16 NC NC 5 5 5 5 5 5 SYSACE_MPA03_LS SYSACE_MPA02_LS SYSACE_MPA01_LS SYSACE_MPA00_LS SYSACE_MPWE_LS SYSACE_MPOE_LS 2 1 3 4 5 6 7 8 9 10 VCCA A1 A2 A3 A4 A5 A6 A7 A8 OE VCCB B1 B2 B3 B4 B5 B6 B7 B8 GND A 1 C95 X5R 2 10V 0.1UF TXB0108 19 20 18 17 16 15 14 13 12 11 NC NC SYSACE_MPA03 SYSACE_MPA02 SYSACE_MPA01 SYSACE_MPA00 SYSACE_MPWE SYSACE_MPOE 20 20 20 20 20 20 Level Shifters C94 X5R 2 10V 0.1UF 1 Title: Level Shifters SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM 0431534 0381305 TSS0123 1280473 A Date: 9-24-2009_15:00 Sheet Size: B Sheet 4 PCB P/N: SCH P/N: Test P/N: ART P/N: 3 2 35 of Ver: D Rev: 04 Drawn By 35 BF 1
