Tamkang Journal of Science and Engineering, Vol. 11, No. 4, pp. 387-394 (2008)
387
Layout Dependence of ESD Characteristics on High
Voltage LDMOS Transistors
Shuang-Yuan Chen1*, Mu-Chun Wang2, Shao-Min Ho1, Wei-Yi Lin1,
Yeh-Ning Jou3 and Heng-Sheng Haung1
1
Institute of Mechatronic Engineering, National Taipei University of Technology,
Taipei, Taiwan 106, R.O.C.
2
Department and Institute of Electronic Engineering, Minghsin University of Science and Technology,
Hsin Chu, Taiwan, R.O.C.
3
Vanguard International Semiconductor Corporations,
Hsin Chu, Taiwan, R.O.C.
Abstract
In this work, laterally diffused MOS (LDMOS) transistors deployed with six layout parameters
have been contrived and manufactured to prove the effectiveness of ESD protection using transmission
line pulsing (TLP) measurements. The phenomena with high-current breakdown in ESD stress were
observed and their electrical behaviors were analyzed to extract the optimal layout rules. After
analyzing the ESD test results, the cardinal contributions of layout parameters affecting the trigger
voltages of LDMOSs indicate the lateral buried layer length and the STI spacing. Additionally,
non-uniform turn-on in the gate-grounded NMOS (GGNMOS) transistors, which would influence
their ESD robustness, was observed by employing an EMMI (emission microscope) instrument.
Through these analyses, the experimental results and the physical interpretations compose an
important base on the design of using LDMOS transistors as ESD protection devices.
Key Words: Electrostatic Discharge (ESD), Transmission Line Pulsing (TLP), Laterally Diffused
MOS (LDMOS)
1. Introduction
CMOS technology has proved its tremendous success in making micro- or nano- electronic devices in low
voltage integrated circuits (ICs). In high voltage regime,
CMOS technology is also very promising and its application is just to begin. High voltage MOS (HV-MOS) process used in manufacturing LCD display driver ICs supporting voltages up to 40 V is a well-known example.
The main advantages of adopting HV-MOS certainly are
low cost, compatible with standard CMOS process, and
hence they can be easily integrated with the core logic/
analog circuits to form a smart power system.
But in high voltage regime, the devices within must
*Corresponding author. E-mail: sychen@ntut.edu.tw
be able to cope with voltages and currents substantially
higher than the ones in low voltage applications. Certainly, more electrostatic discharge (ESD) consideration
is also a necessity. To fulfill the requirement, laterally
diffused MOS (LDMOS) transistors are commonly used
as the salient active devices in HV-MOS circuits because
their breakdown voltages can be increased by an additional drift region between gate and drain terminals.
On the other hand, to withstand a reasonable ESD
stress (typically, 2 kV in the human-body-model [1]) for
safe mass-production, on-chip ESD protection circuits
have to be added into the IC products. A typical wholechip ESD protection concept had been developed, redrawn as in Figure 1 [2]. Therefore, an inevitable choice
is to choose LDMOS devices as the main “valve” of the
clamp circuit in Figure 1 to drain out the high-current in-
388
Shuang-Yuan Chen et al.
Figure. 1. Typical on-chip ESD protection design for input/
output (I/O) pad and power- rail [2].
duced by ESD. That is why recently there are quite a few
research publications concerning this subject [3-5].
In order to design area-efficient ESD protection circuits, the ESD protection devices are desirable in a limited layout area with robust characteristics. However,
to sustain the desired 2 kV ESD level, real on-chip ESD
protection circuits are often drawn with larger device dimensions. Multiple-finger layout strategy is also adopted
to reduce the total ESD-device area. Nevertheless, these
will certainly influence ESD robustness in circuit protection [3,6]. On the other hand, electrical properties such as
avalanche breakdown or snapback voltage can be controlled by selecting adequate layout-design parameters
[5]. Therefore, layout types and sizes are sensitive to the
device ESD characteristics. To optimize the efficiency
of LDMOS devices for ESD protection, the impact of
LDMOS devices with different layout variables under
high-current stress must be entirely understood.
In this research, the behavior of actual LDMOS devices under ESD stress of the TLP (transmission line
pulsing) measurement technique is analyzed. Through
the investigation of layout parameters on ESD characteristics of LDMOS devices, the optimized parameters are
extracted and can be used to enhance the effectiveness of
LDMOS devices under ESD test.
2. TLP Measurement
TLP test systems have been employed to evaluate the
ESD behavior of silicon devices and integrated circuits
from Maloney et al. in 1985 [7]. Since then, TLP has revealed tremendous insight into the electrical characteristics of ESD protection circuits and devices [8-10]. The
turning-points in TLP characteristics expose strong relationship with the circuits’ ESD behavior. The test results
can then be used to reduce the design cycle time of these
protection circuits [11].
While measuring the I-V behavior of an ESD protection device with the TLP system, the device is actually
being stressed with ESD-type pulses. This is effective
because 100-ns time width and high-current pulses are
applied. When the device fails during TLP test, one can
analyze the figure of merit that reflects the actual ESD
robustness of the device. Due to the nature of the chosen
TLP pulse, one can expect the TLP failure results correspond to the HBM test results.
The traditional way of depicting TLP data is to draw
the I-V curve. The common way indicating failure is to
exhibit the so-called It2 point, or the current of second
breakdown point [8]. Hence, it is suggested that It2 equals
the maximal current handling capability of the ESD protection devices. An illustration is shown in Figure 2 where
a gate-grounded NLDMOS was tested and the drain leakage currents after each TLP were also measured. The
high-current capacity It2 is determined when the leakage
current exceeds 1 mA.
Figure 2. An example of high-current I-V curve with the drain
leakage current after each TLP. The (Vt1, It1) indicates the breakdown trigger voltage and current.
The (Vt2, It2) represents the second breakdown
point determined by the leakage current over 1 mA.
Layout Dependence of ESD Characteristics on High Voltage LDMOS Transistors
3. Layout Variation and Its Impact
The layout factors sticking the ESD robustness of
LDMOS transistors have been practically investigated
by fabricating the test-chips using a 0.25 mm silicided
HV-CMOS process. The Barth 4002 TLP Pulse Curve
Tracer is applied to measure the HBM level of the fabricated test-chips.
In order to probe transistor layouts in terms of
maximal ESD protection and performance for the high
voltage technology, a set of systematic variables of important layout dimensions as shown in Figure 3, were
designed based upon 0.25 mm 40V HV design rules.
These layout parameters and values have been considerately adjusted, as shown below and the measured
results will be exhibited as well as discussed in the following sections.
l W, channel width (double or four fingers with each
finger width W = 50 mm)
l L, channel length (L = 2.5, 3, 4 mm)
l b, length of accumulation region (b = 1, 2 mm)
l S, spacing under STI (shallow trench isolation) (S
= 3, 4 mm)
l With or without RPO (resistor protection oxide)
covering drain surface
l
389
With or without NBL (N+ buried layer) under the
transistor
3.1 Channel Width Dependence
The NMOS and PMOS devices with different widths
have been fabricated in a 0.25 mm silicided CMOS process. The unit width of the NMOS and PMOS devices in
this investigation is set as 50 mm. The TLP-measured
I-V curves of GGNMOS (gate grounded NMOS) and
GDPMOS (gate connected to drain PMOS) with different channel widths (W = 100 mm, 200 mm) are compared
in Figures 4 and 5, respectively. The common failure criterion is when the leakage current exceeds 1 mA, and the
curves of leakage currents are omitted for simplicity. The
Figure 4. I-V curves for various channel widths of HV
GGNMOS transistors after TLP tests.
Figure 3. The schematic layout of the LDNMOS and its crosssection with the definition of layout parameters.
Figure 5. I-V curves for various channel widths of HV
GDPMOS transistors after TLP tests.
390
Shuang-Yuan Chen et al.
layout style and the other parameters are the same, such
as L = 2.5 mm, b = 1 mm, S = 3 mm, without NBL but with
RPO layer.
From Figure 4, one can observe that the NMOS devices almost have the same trigger voltages, i.e., their
trigger voltages are independent of their widths or number of fingers. The high-current capacities It2 (the highest
current of each case) of the NMOS devices are somewhat
irregular with respect to their channel widths. This is due
to the non-uniform turn-on among the multiple fingers of
the devices. Later we will show the EMMI (emission microscope) photographs to prove this. From Figure 5, one
can observe that the PMOS devices do not have clear
snapback phenomenon and their It2 are approximately
proportional to their widths. This implies more uniform
turn-on than their NMOS counterparts. However, the It2
levels are too low, which makes the GDPMOSs less capable in draining out ESD surge current. A summary related to channel widths versus ESD characteristics per
unit layout area is shown in Table 1.
With the consideration of sinking more ESD current,
the channel widths of LDMOS transistors are often designed with larger dimension, and often with multiple
fingers. To reveal the turn-on behavior of the ESD protection devices during stress, EMMI photographs can be
used. When the applied potential is increased sufficiently
to trigger the parasitic lateral bipolar junction transistor
(BJT), the hot spots at turn-on region can be clearly discovered. The turned-on finger-gates cause the ESD current mainly discharging through these fingers. If the local
turn-on region cannot be quickly extended to whole regions of all fingers, the region will be burned out because
of the over-heating by ESD current. Hence, if nonuniform turn-on occurs, the devices with a larger channel
width are not effective to sustain the high ESD current as
expectation. Therefore, the turn-on uniformity constitutes
an important issue in investigating the robustness of ESD
protection devices.
The EMMI photographs on the double-finger LDMOS
transistors during the stresses are shown in Figures 6 and
7. In Figure 6, the hot spot is only exhibited at the one
side of the finger-type NMOS. This local hot spot implies that the device generates non-uniform turn-on after
the snapback as that shown in Figure 4. Therefore, it is
presumable that this is the reason causing the irregular It2
of the NMOS devices on different channel widths. It is
then safe to infer that multiple-finger structure of NLDMOS
is not effective to increase the ESD It2 capability.
Figure 6. EMMI photographs on a GGNMOS transistor to
observe its turn-on behavior.
Figure 7. EMMI photographs on a GDPMOS transistor to
observe its turn-on behavior.
Table 1. The ESD characteristics after testing using TLP
Device
Channel width (mm)
Layout area (mm2)
ESD It2 level (A)
ESD It2 level per unit layout area (A/mm2)
GGNMOS
100 (2 fingers)
28.6 ´ 65
1.95
1.05E-03
200 (4 fingers)
55.7 ´ 65
2.07
5.72E-04
GDPMOS
100 (2 fingers)
28.6 ´ 65
0.1
5.38E-05
200 (4 fingers)
55.7 ´ 65
0.21
5.80E-05
Layout Dependence of ESD Characteristics on High Voltage LDMOS Transistors
On the contrary, from Figure 7, the non-uniform
turn-on for GDPMOS devices is not as serious as those
for GGNMOS devices because the PMOS device does
not have an obvious snapback phenomenon as that shown
in Figure 5. However, suffered from the too low It2 levels, GDPMOSs are not suitable for used as main ESD
protection devices. Therefore, we will focus our discussion on GGNMOS transistors from now on.
3.2 Channel Length Dependence
The relations of the device channel lengths (L = 2.5
mm, 3 mm and 4 mm) and with or without RPO versus the
ESD trigger voltage is shown in Figure 8. The layout
style and other parameters are all kept the same (W = 100
mm, b = 1 mm, and S = 3 mm). From the test results, the
trigger voltages are insensitive to the variations of channel lengths as well as RPO.
391
significant effect on the ESD trigger voltages.
3.4 Length of STI Spacing (S-factor Variation)
The ESD trigger voltages of the NMOS devices with
S = 3 or 4 mm and L = 2.5 or 3 mm are investigated, and
the results are shown in Figure 10. All other parameters
are fixed at W = 100 mm, b = 1 mm, without NBL but with
RPO layer. It can be observed that when STI spacing S
increased from 3 mm to 4 mm, the ESD trigger voltages of
the NMOS rose from 100 V to 117 V. Thus the STI spacing is an effective parameter to control the trigger voltage, or say to control the turn-on of parasitic BJT. Instead, the channel length L is quite inactive to the trigger
voltage.
3.3 Length of Accumulation Region
(b-part Variation)
The dependence of b parameter (the clearance from
the HV P-well edge to the STI edge), with or without
RPO, on the ESD trigger voltage is shown in Figure 9. In
this study, all of the layout styles and other spacing factors
are the same (W = 100 mm, L = 2.5 mm, and S = 3 mm).
Only the accumulation region lengths are adjusted from
1.0 mm to 2.0 mm in the test-chips. From the experimental
results, the clearance variation just leads to a slight variation on the ESD trigger voltages from 90 V to 93 V for the
NMOS devices. Hence, neither b parameter nor RPO has
Figure 9. The relationship of trigger voltages with different
lengths at accumulation region (b parameter).
Figure 8. The relationship of trigger voltages with different
channel lengths and RPO.
Figure 10. The relationship of trigger voltages with different
STI oxide spacing and channel lengths.
392
Shuang-Yuan Chen et al.
3.5 Buried Layer Dependence
(NBL-variable Variation)
To investigate ESD characteristic dependence on the
N+ buried layer, four types of GDNMOS structures were
designed, and their cross-sections are schematically shown
in Figure 11(a)-(d). Those structures had been optimized to satisfy the different electrical requirements. The
TLP-measured I-V curves of the four devices are simultaneously exhibited in Figure 12. From the experimental
results, the trigger voltages of the transistors can effectively be reduced by increasing the lateral NBL length.
Consequently, N+ buried layer can be treated as a control
variable to obtain a desirable trigger voltage. As for the
RPO, no significant effect can be discovered.
Next, the electrical behavior will be discussed for the
LDMOS device containing an N+ buried layer under the
drain side. Schematic transistor cross sections of the conventional LDMOS and LDMOS with NBL are shown in
Figures 13 and 14. The breakdown voltage of the conventional device can be regarded as being governed by the
breakdown of the two junction diodes, D1 and D2. But for
the LDMOS with NBL, the N+ buried layer serves the pur-
pose for isolating the device from the substrate, which results in replacing D2 by D3. Because of the heavy doping
of the NBL, the breakdown voltage of D3 is lower than
that of the other two diodes, D1 and D2. Accordingly, the
current would flow under the well and lead to the lower
breakdown voltage comparing with the other structures.
Figure 12. TLP I-V characteristics for different structures of
NBL, with or without RPO.
Figure 11. Cross-sections of four different NBL structures.
Layout Dependence of ESD Characteristics on High Voltage LDMOS Transistors
393
pends on specific applications of the circuits. The other
parameters, such as channel length, length of accumulation region and RPO, have no significant influence on the
ESD characteristics. Hence, channel length and length of
accumulation region are recommended to maintain at the
minimum according to the layout rules and to avoid using RPO to save an additional mask.
References
Figure 13. Schematic cross-section of a conventional LDMOS
transistor.
Figure 14. Schematic cross-section of a LDMOS transistor
with NBL.
4. Conclusion
In this work, the dependence of ESD characteristics
on layout parameters of LDMOS transistors in a 0.25 mm
silicided CMOS process has been experimentally and
completely investigated. The ESD properties concerning
six different layout parameters of the high voltage devices have been measured using a TLP instrument and
analyzed in this paper. The results show that the GDPMOS
transistors are not suitable as ESD protection devices because their ESD current capacities are too low. While the
GGNMOS transistors are capable to sink high-current
fulfilling the requirement of HBM, multiple-finger structure is not recommended due to possible non-uniform
turn-on. Therefore, to obtain the optimal design, the length
of lateral N+ buried layer and the length of STI spacing
are both applicable and effective in adjusting the trigger
voltages of the GGNMOS devices. This certainly de-
[1] Electrostatic Discharge Sensitivity Testing - Human
Body Model (HBM) - Component Level, ESD Test
Standard, Method ESD STM5.1 (1999).
[2] Ker, M. D., Chuang, C. H. and Lo, W. Y., “ESD Implantation for On-Chip ESD Protection with Layout
Consideration in 0.18-mm Salicided CMOS Technology,” IEEE Trans. on Semiconductor Manufacturing,
Vol. 18, pp. 328-337 (2005).
[3] Chung, Y., Besse, P., Zecri, M., Baird, B., Ida, R.,
Nicolas, N. and Bafleur, M., “Geometry Effect on
Power and ESD Capability of LDMOS Power Devices,” IEEE Proc. ISPSD, pp. 265-268 (2003).
[4] Suzuki, N., Yamacuchi, H. and Shiraki, S., “BreakThrough of the Trade-Off between On-Resistance and
ESD Endurance in LDMOS,” IEEE Proceeding of the
17th International Symposium on Power Semiconductor Devices & IC’s, pp. 179-182 (2005).
[5] Chung, Y., Min, W. G., Xu, H., Ida, R. and Baird, B.,
“ESD Scalability of LDMOS Device for Self-Protected Output Drivers,” IEEE Proceeding of the 17th
International Symposium on Power Semiconductor
Devices & IC’s, pp. 351-354 (2005).
[6] Jiang, C., Nowak, E. and Manley, M.,“Process and Design for ESD Robustness in Deep Submicron CMOS
Technology,” in Proc. IEEE Int. Reliability Physics
Symp., pp. 233-236 (1996).
[7] Maloney, T. and Khurana, N.,“Transmission line
Pulsing Techniques for Circuit Modeling of ESD Phenomena,” in Proc. EOS/ESD Symp., Vol. EOS-7, pp.
49-54 (1985).
[8] Amerasekera, A., Roozendaal, L. V., Bruines, J. and
Kuper, F.,“Characterization and Modeling of 2nd Breakdown in NMOST’s for the Extraction of ESD-related
Process and Design Parameters,” IEEE Trans. Electron Devices, Vol. 38, pp. 2161-2168 (1991).
[9] Chen, T. P., Chan, R., Fung, S. and Lo, K. F., “Repro-
394
Shuang-Yuan Chen et al.
ducibility of Transmission Line Measurement of Bipolar I-V Characteristics of MOSFETs,” IEEE Trans
Instrum Meas., Vol. 48, pp. 721-723 (1999).
[10] Ashton, R. A., “Transmission Line Pulse Measurements: A Tool for Developing ESD Robust Integrated
Circuits,” Proc. IEEE 2004 Int. Conference on Micro electronic Test Structures, Vol. 17, pp. 1-6 (2004).
[11] Beebe, S.,“Methodology for Layout Design and Optimization of ESD Protection Transistors,” in Proc.
EOS/ESD Symp., Vol. EOS-18, pp. 265-275 (1996).
Manuscript Received: Oct. 11, 2006
Accepted: Jan. 25, 2008