EE 218 - Stanford University
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Stanford University EE 218: Introduction to Nanotechnology and Nanoelectronics H.-S. Philip Wong Professor of Electrical Engineering Stanford University, Stanford, California, U.S.A. hspwong@stanford.edu http://www.stanford.edu/~hspwong Center for Integrated Systems EE 218 Department of Electrical Engineering Stanford University What is Nanotechnology? Source: Apple Computer, Inc. 2 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University The Beginning of Nano Source: IBM Source: IBM Invention of the Scanning Tunneling Microscope (STM) 3 H.-S. Philip Wong Gerd Binnig, Heinrich Rohrer Nobel Prize, 1986 EE 218 Department of Electrical Engineering Stanford University Source: IBM 4 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005. 5 H.-S. Philip Wong EE 218 Department of Electrical Engineering The Scale of Things -- Nanometers and More Source: NSF website 10-2 m Ant ~ 5 mm 10-3 m 1 cm 10 mm 1,000,000 nanometers = 1 millimeter (mm) Dust mite Human hair ~ 10-50 µm wide Fly ash ~ 10-20 µm The Microworld 200 µm Red blood cells with white cell ~ 2-5 µm 10-4 m 0.1 mm 100 µm 10-5 m 0.01 mm 10 µm 1,000 nanometers = 1 micrometer (µm) Visible spectrum 10-6 m m 0.1 µm 100 nm 10-8 m 0.01 µm 10 nm 10-9 m 1 nanometer (nm) The Nanoworld 10-7 ~10 nm diameter ATP synthase DNA ~2-1/2 nm diameter Atoms of silicon spacing ~tenths of nm 10-10 m 0.1 nm Nanotechnology Progress Generating New Excitement Things Natural Things Manmade Source: J. Sphorer (IBM) Head of a pin 1-2 mm 21st Century Challenge MicroElectroMechanical Devices 10 -100 µm wide O P O O O O O O O O O O O O O O O O O O O O O O S S S S S S S S Red blood cells Pollen grain Nanotube electrode Combine nanoscale building blocks to make functional devices, e.g., a photosynthetic reaction center with integral semiconductor storage Nanotube transistor Quantum corral of 48 iron atoms on copper surface positioned one at a time with an STM tip 6 Carbon nanotube ~2 nm diameter Stanford University US Nanotechnology Funding Source: M. Roco, NNI (10/29/2003). 7 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University NNI Funding by Agency Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005. 8 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Global Nanotechnology Investment Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005. 9 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005. 10 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: M. Roco, NNI (10/29/2003). 11 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: M. Roco (NNI), National Research Council, Washington, D.C., March 23, 2005 12 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005. 13 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University http://www.research.ibm.com/pics/nanotech/ 14 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Questions? 15 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University An 8 nm Transistor Gate Gate Source Drain Lgate=8 nm Source: IBM 16 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Atoms are starting to look big Source: IBM When one atom high “bumps” look significant in a photo of your transistors, both their manufacture and behavior are “exciting” 17 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Integrated Circuit Complexity Source: G. Moore, Intel (2003) 18 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: K. David (Intel) 19 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: K. David (Intel) 20 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University State-of-the-Art Technology 90 nm technology 65 nm technology Source: M. Bohr, Intel (2004) 21 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University A view from Intel 22 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Blue Sky Time Horizon 2004 2007 2010 2013 2016 2020 Physical Gate Ultrathin SOI 37 nm 25 nm 18 nm 13 nm 9 nm High k gate dielectric 6 nm FinFET Double-Gate CMOS Strained Si, Ge, SiGe doped channel raised source/drain Strained Si, Ge, SiGe top-gate Gate channel halo buried oxide depletion layer buried oxide isolation Silicon Substrate isolation Silicon Substrate Evolutionary 23 H.-S. Philip Wong channel back-gate isolation Source buried oxide Drain Revolutionary EE 218 Department of Electrical Engineering Stanford University Poly-silicon Future Si Devices Tox=16A Gate Source Tsi=7 nm H. Shang et al., IEDM 2002 Gate Drain Source NiSi Gate NiSi Drain B. Doris et al., IEDM 2002 Si Fin J. Kedzierski et al., IEDM 2001 , IEDM 2002 Tox = 1.6nm Tsi = 25nm K. Rim et al., IEDM 2003 Si BOX W CoSi2 on RSD HfO2 Strained silicon 60nm SiO2 SiGe Si M. Yang et al., IEDM 2003 24 H.-S. Philip Wong EE 218 Buried oxide B. Lee et al., IEDM 2002 Department of Electrical Engineering Stanford University Innovation Overtakes Scaling in Driving Performance Innovation (invention) will increasingly dominate performance gains – Scheduled "invention" is now the majority component in all plans • Risk has increased significantly IBM Transistor Perform ance Im prov em ent Gain by Traditional S caling Gain by Innovation 100 60 CMOS10S CMOS11S CMOS8S2 CMOS9S CMOS7S-SOI 65 nm CMOS6X 90 nm H.-S. Philip Wong 130 nm 25 180 nm Source: IBM 250 nm 0 350 nm 20 CMOS5X 40 500 nm Relative % Improvement 80 EE 218 Department of Electrical Engineering Stanford University Straight Line Projections Can Be Wrong… Source: G. Moore, Intel (2003) Therefore, we need to focus on the fundamentals 26 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University To Learn More About Si Technology… EE 212 – Fabrication technology (J. Plummer) EE 316 – Si CMOS device (H.-S. P. Wong) EE 311 – Device technology (K. Saraswat) EE 309 – Semiconductor memory (H.-S. P. Wong) EE 410 – Fabrication lab (K. Saraswat) 27 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Questions? 28 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Several distinct technologies have been used to We are here ! implement complex logic $1000 buys... 1.E+12 Pentium 4 PC Additions per second Vacuum tube 1.E+09 Discrete transistor Integrated circuit IBM PC 1.E+06 DEC PDP-8 1.E+03 ENIAC 1.E+00 1.E-03 1940 1950 Data from R. Kurzweil, 1999, The Age of Spiritual Machines 29 H.-S. Philip Wong 1960 1970 1980 1990 Year 2000 2010 2020 Source: IBM EE 218 Department of Electrical Engineering Stanford University Gestation for Technologies Solid State Diode T1 26 (1874-1900) T2 7 (1900-1907) T3 6 (1907-1913) Example: Solid State Rectifier Development Level 5 Market production (Established Technology) 4 Learning Period Commercialization: 1907 (Entrant) 3 Prototype built 1900 (Braun) Background/Infrastructure: T2 1874 (Braun) 2 1 0 1870 ‘Research Curve’ T1~ 20years 1880 1890 1900 1910 Vacuum Tube T1 20 (1884-1904) T2 9 (1904-1913) T3 6 (1913-1919) Learning Period T3 1920 1930 13 years 15 years Transistor T1 25 (1923-1948) T2 6 (1948-1954) T3 5 (1954-1959) Learning period 11years ~10years • To be ready for 2016 - start now narrowing down options Integrated Circuit T1 17 (1942-1959) T2 3 (1959-1961) T3 5(1961-1966) Learning Period 8 years After Ralph Cavin, SRC 30 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University International Technology Roadmap for Semiconductors The International Technology Roadmap for Semiconductors (ITRS) is an assessment of the semiconductor technology requirements. The objective of the ITRS is to ensure advancements in the performance of integrated circuits. This assessment, called roadmapping, is a cooperative effort of the global industry manufacturers and suppliers, government organizations, consortia, and universities. The ITRS identifies the technological challenges and needs facing the semiconductor industry over the next 15 years. It is sponsored by the European Semiconductor Industry Association (ESIA), the Japan Electronics and Information Technology Industries Association (JEITA), the Korean Semiconductor Industry Association (KSIA), the Semiconductor Industry Association (SIA), and Taiwan Semiconductor Industry Association (TSIA). International SEMATECH is the global communication center for this activity. The ITRS team at International SEMATECH also coordinates the USA region events. 31 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: ITRS, J. Hutchby Emerging Research Logic Devices 2003 ITRS PIDS/ERD Chapter Device FET Cell Size 100 nm RSFQ 0.3 µm Density 3E9 1E6 (cm-2) Switch 700 GH 1.2 THz Speed z Circuit 250– 30 GHz 800 GHz Speed Switching 2×10–18 >1.4×10–17 Energy, J Binary Throughput, 86 0.4 2 GBit/ns/cm Resonant 1D Tunneling structures Devices SET Molecular QCA Spin transistor 100 nm 100 nm 40 nm Not known 60 nm 100 nm 3E9 3E9 6E10 1E12 3E10 3E9 Not known 1 THz 1 GHz Not 30 MHz 700 GHz known 30 GHz 30 GHz 1 GHz <1 MHz 2×10–18 >2×10–18 86 86 1 MHz >1.5×10–17 1.3×10–16 >1×10–18 10 N/A 0.06 30 GHz 2×10–18 86 http://public.itrs.net 32 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: ITRS, J. Hutchby Emerging Research Memory Devices 2003 ITRS PIDS/ERD Chapter Present Day Baseline Technologies Phase Change Memory* Floating Body DRAM Nanofloating Gate Memory** SET MIM oxides Bi-stable switch Molecular NEMS Single/Few Insulator Electron Resistance Memories* Change * Memory** Molecular Memories** Storage Mechanism DRAM NOR Flash OUM 1TDRAM eDRAM Engineered tunnel barrier or nanocrystal Availability 2004 2004 ~2006 ~2006 ~2006 >2007 ~2010 >2010 Cell Elements 1T1C 1T 1T1R 1T 1T 1T 1T1R 1T1R Device Types http://public.itrs.net 33 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: M. Roco (NNI), Nanotechnology Research Directions II, September 8, 2004. 34 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Nano Pants Lee Men's Flat Front Performance Khakis - Black "Nanocare revolutionizes fabric technology, making these pants totally carefree! Product Features: * Repels liquids * Minimizes stains * Wrinkle free * Comfort waist with relaxed seat and thigh * Contemporary plain styling * 16 1/2 inch leg opening." $ 38.00 >> $ 19.90 Buy at EssentialApparel / more info 35 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Nano Cosmetics 36 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Nano Skin Care Products 37 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Questions? 38 H.-S. Philip Wong EE 218 Department of Electrical Engineering
