International Conference on Recent Advances in Communication, VLSI & Embedded Systems
ISSN (Online):2349-0020, ISSN (Print): 2394-4544, (ICRACVES-2014)
A Novel 3 Transistor XOR Gate Based Full
Adder Design for VLSI Applications
Korra Ravi Kumar
Dept. of ECE
P.Narsimulu
Dept. of ECE
Sree Chaitanya College
Sree Chaitanya College
of Engg, Karimnagar
of Engg, Karimnagar
ravikumar.korra@gmail.com, narsimulupolala@gmail.com
Abstract--This paper deals with a new way of
designing XOR gate using 3 transistors. A full adder
circuit has been designed using proposed 3T XOR
circuit and a transmission gate is used extensively in
very large-scale integration (VLSI) application. The
power consumption of the circuit is in range of
421.7256uw to 581.542uw in 0.35 um technology with a
voltage supply range of 1.8V to 3.3V. The simulation
process has performed by the SPICE and DSCH tool
based on TSMC 0.35um CMOS technology. The power
consumed by the 3T XOR gate as well as single bit full
adder has been compared with previous reported
circuits, the proposed circuit shows good performance
in terms of the factors power consumption, speed and
area optimization(transistor count).
Keywords: CMOS, transmission gate, full adder,
exclusive-OR (XOR).
I. INTRODUCTION
Now a days electronic devices like laptops,
portable systems, and cellular networks with
increasing demand of low power consumption, less
area occupation, less delay, high speed and high
degree of sophistication. Attentions towards Research
in low power VLSI (very large-scale integration)
have increased. With increase in the number of
transistors integrated on a chip, power consumption
of the integrated circuit is also increasing leads to
cause reliability and packaging hazards [1]. In
Complementary Metal Oxide Semiconductor VLSI
circuits power consumption can be categorized into
three different ways: Dynamic, static and short circuit
power consumption [2].
Ptotal = Pdynamic + Pstatic + Pshort circuit ….(1)
A.Santhosh Kumar
Dept. of ECE
M.Raju
Dept. of ECE
Sree Chaitanya College
Sree Chaitanya College
of Engg, Karimnagar
of Engg, Karimnagar
santhosh.allenki@gmail.com, m.raju2002@gmail.com.
large-scale integration (VLSI) systems such as
application-specific digital signal processing (DSP)
and microprocessors. In recent years several
variations of different logic styles have been
proposed to implement 1-bit adder cells [1-12]. The
basic CMOS 28T full adder design with good load
driving capability and high noise margin [3]. In [4] a
full adder design with XOR pass transistor logic
(PTL) is reported. CMOS adder based on
transmission gate using 20 transistors is reported in
[5]. Design of full adder using 10 transistors with low
power and high delay presented in [6].
II. FULL ADDER CIRCUIT DESCRIPTION
The full adder performance can be explained as
follows: the addition of two 1-bit inputs A and B with
carry Cin gives the two 1-bit outputs Sum and Cout,
where
Sum = ( A ⊕ B ) ⊕ Cin …………………(2)
Cout = A.B + Cin ( A ⊕ B ) …………….(3)
In our design, we rewrite the Boolean function as
Sum = X ⊕ Cin = XCin'+ X ' Cin ….…....(4)
Cout = A.B + A'.B.Cin + A.B'.Cin .......…(5)
Cout = ( A'.B '+ A.B ). A + ( A'.B + A.B ' ).Cin …...(6)
Cout = A ⊕ X = A. X '+ A' X ……….…(7)
Static power is because of unwanted leakage
current when transistor is in off state. The dynamic
power dissipation is due to switching action of
parasitic components, also called switching power.
Short circuit power consumption is because of current
flowing from Vdd to Vss.[2].
Binary addition is a fundamental arithmetic
operation which is used extensively in many very
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Fig.1: Block diagram of full adder
SR Engineering College, Warangal
International Conference on Recent Advances in Communication, VLSI & Embedded Systems
ISSN (Online):2349-0020, ISSN (Print): 2394-4544, (ICRACVES-2014)
Table.1. Truth table for full adder
A
B
Cin
SUM
Cout
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
The standard way of designing full adder using
XOR gate and multiplexer is as shown in figure
(1) of [7]. The XOR gate and multiplexer are basic
building blocks in full adder design. Arithmetic
operation of full adder circuit is depends on
performance of XOR and multiplexer blocks. The
design should have less number of transistors to
implement XOR circuits for low power dissipation.
The multiplexer circuit MUX is adopted in our
proposed design to generate Cout. Transmission gate
is used as a 2 to 1 multiplexer. The transmission gate
has advantage for the circuit: firstly, it speeds up the
carry propagation as a buffer along the carry chain.
Secondly, it provides, the transmission gate can
improve the output voltage swing as a level restoring
circuit The proposed full adder circuit, which uses
two XOR gates and one multiplexer, requires eight
transistors. Choosing appropriate width to length
rates of transistors, Fig.2: Design of proposed XOR cell
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Fig.3: Input and output patterns for proposed XOR circuit
A novel xor circuit with 3 transistors shown in
fig(2). When A and B both the inputs are Low the
circuit producing Logic Low as output, when inputs
A is low and B is high then transistor s Q1 is on, Q2
and Q3 are off and provide logic high at output
terminal. When input combinations A are high and B
is low, Q1 is off, Q2 is on and Q3 is on leads to
provide the output as high, when A is high and B is
high then circuit provides Low as output. So the
proposed circuit functioning as XOR circuit. Output
wave forms shown in fig(3).
The proposed 8 transistor full adder circuits
designed by joining the 2 XOR circuits and a single 2
to 1 multiplexer. In this circuit the sum output is
generated by two XOR gates and carry out is
generated by two transistor multiplexer block or
transmission gate. It provide the better performance
than the previous full adder circuits and obtain less
area due to less number of transistor count. A novel
design of full adder using proposed XOR gate with 8
transistors has been implemented as shown in fig (4).
Fig.4: Full adder using two XOR gates and multiplexer
SR Engineering College, Warangal
International Conference on Recent Advances in Communication, VLSI & Embedded Systems
ISSN (Online):2349-0020, ISSN (Print): 2394-4544, (ICRACVES-2014)
Fig.5: Input and output patterns for proposed full adder
III. RESULTS AND DISCUSSIONS
Table 2 shows power consumption, delay and
output voltage levels with variable supply voltage
ranging from [3.3-1.8]V for proposed xor gate, power
consumed by this circuit is changes from[ 500.72789.93 ] entire simulation done with supply voltage
ranging from(1.8-3.3)V is suitable to compare the
power consumption and delay.
TABLE.2: Power consumption, delay and output levels of
proposed XOR gate.
Supply
voltage(
V)
Power
consumption
(µw)
Output
delay(ps )
Minim
um
level
for
high
output
(V)
3.3
500.727
14.466
2.05
0.084
3.0
395.378
15.846
1.84
0.072
2.5
218.996
18.165
1.41
0.054
2.0
127.452
21.099
1.13
0.041
1.8
89.931
23.050
0.92
Maximu
m level
for high
output(V
)
0.034
Fig.6: Power consumption of XOR gate with supply voltage
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Fig.7: Delay of XNOR gate with supply voltage
Fig.6 shows the power consumption versus supply
voltage, with this, it has been observed that power
consumption of XOR circuit is decreasing with
decreasing the supply voltage. Fig.7 shows the output
delay versus supply voltage, delay increasing with
decrease in supply voltage.
The entire simulation done with supply voltage
ranging from(1.8-3.3)V is suitable to compare the
power consumption, delay of single bit full adder
circuit and also the simulation result of the proposed
full adder circuit is compared with existed CMOS full
adder circuits. Power consumption has been reduced
due to reduced transistor count and reduced
capacitance in the XOR circuit. The shorting of
terminals from power supply to ground is completely
eliminated. So that short circuit current is also low in
the circuit.
TABLE 3: Comparison between different types of full adder
designs
Full adder
type
Power
consumption(µw)
Number
of
transistors
for design
conventional
946.116
28
22T adder
546.289
22
TG adder
371.632
20
10SERF
263.038
10
Present
work
197.104
8
Power efficient adders have been designed with
different combination of XOR gates and transmission
gate transistor multiplexer concept Power
consumption has been reduced From the above table
SR Engineering College, Warangal
International Conference on Recent Advances in Communication, VLSI & Embedded Systems
ISSN (Online):2349-0020, ISSN (Print): 2394-4544, (ICRACVES-2014)
3, It is clear that even though proposed circuit has 8
transistors, still it consuming less power.
IV. CONCLUSION
In this present work a low power and area
efficient design of full adder with 8 transistors using
proposed 3 transistors XOR gate has been presented.
The characteristics of the proposed full adder circuit
are compared against earlier reported full adder
circuits based on power consumption. Full adder
shows the power consumption of 197.104 µw and
better output signal levels with reduced transistor
count.
References [1] J.M. Rabaey, and M. Pedram, ”Low Power Design
Methodologies, ”Kluwer Academic Publishers,
2002
[2] R. Zimmermann and W. Fichter, ”Low-power logic
CMOS versus pass-transistor logic,”IEEE J.Solid
Circuits,Vol.32,july1997,pp.1079-90
Styles
- State
[3] N. Waste and K. Eshraghian, Principles of CMOS VLSI
Design, A System perspective, Addison - Wesley,1993.
[4]
A. M. Shams and M. Bayoumi, “A novel highperformance CMOS 1-bit full adder cell,
” IEEE
Transaction on Circuits Systems II,
Analog Digital
Signal Process, vol. 47, no. 5, pp. 478–481,
May 2000.
[5] N. Weste and K. Eshraghian, “Principles of CMOS VLSI
Design,” A System Perspective, Addison-Wesley, 1993.
[6]
R. Shalem, E. John, and L. K. John, “A novel low-power
energy recovery full adder cell,” in Proc.Great Lakes
Symposium on VLSI, pp. 380–383, Feb. 1999.
[7]
Manoj Kumar, Sandeep K. Arya and Sujata pandey,” Single
bit Full adder design using 8 transistors with novel 3
transistors XNOR gate”International Journal of VLSI
design & communication Systems,Vol.2, no.4,December
2011.
[8]
Manoj Kumar, Sujata Pandey and Sandeep K. Arya,
Design of CMOS Energy Efficient Single Bit Full Adder,”
Book Chapter of Communications in Computer and
Information Science, Springer-Verlag Berlin Heidelberg,
CCIS 169, pp. 159-168, Jul. 2011.
[9]
Sanjeev Kumar, Pankaj Yadav,”Design of a six transistor
Full adder cell for VLSI applications. ”international
journal of reaserch in computer applications and robotics,
Vol.1, no.8,pp.15-21, November 2013.
[10] Jiang Y, Al-Sheraidah A, Wang Y, Sha E and Chung J,”
A novel multiplexer-based low-power full adder, IEEE
Transactions on Circuits and Systems II: Express Briefs
51 (7).
70
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