Progress and Advances in Serial
Powering of Silicon Modules for the
ATLAS Tracker upgrade
E.G.Villani
on behalf of
SP Community
STFC
Rutherford Appleton Laboratory
1
Outline
• Serial Powering Concept Scheme
• Serial Powering design: Stavelets and Stave program
• Test results
• System issues and further developments
• Conclusions
2
Powering issues
In SCT there are 4088 Detector modules
Independent powering:
4088 cable chains
22 PS racks
4 crates / rack
48 LV and 48 HV channels/crate
Installation is a major logistical challenge
Power dissipated in cables: ~ 20kW
Overall efficiency ~40%
3
Powering issues
1 billion collisions/sec
Up to 1000 tracks
4
10 billion collisions/sec
With SP cable volume and
detector mass will be
significantly reduced. Without
a distributed powering
services volume and cable
losses would no longer be
acceptable for the future
silicon tracker.
Serial Powering concept
The Serial arrangement is Norton equivalent to the Parallel one
The power to the chain of loads is provided by a current source
5
Serial Powering system
Detector modules are placed on staves, that provide mechanical support, cooling and
electrical communication/powering
detector staves are arranged into barrels
6
Serial Powering system
The staves carry 12 detectors, 24 readout hybrids on each side
each hybrid carries 20 ABCn ROICs
In the Serial powering option each hybrid implements a shunt regulator based power supply
7
Serial Powering system
• Each load on each hybrid is represented by 20
ABCN25
• ABCN-25 is 0.25 µm CMOS ROIC prototype and
include SP features
• Hybrid to serve 100 mm x 100 mm sensors
• Prototype for ATLAS SLHC short strip tracker
RAL single chip PCB and Liverpool Hybrid
8
Serial Powering system
•
Hybrid with Shunt “W”
•
•
Use each ABCN’s integrated shunt regulator
Use each ABCN’s integrated shunt transistor(s)
•
Hybrid with Shunt “M”
•
•
Use one external shunt regulator
Use each ABCN’s integrated shunt transistor(s)
–
9
Two (redundant) shunt transistors, 140mA each
•
Hybrid with SPi (or similar)
•
•
Use one external shunt regulator
Use one external power transistor
Serial Powering stavelets
Stavelets
•
•
•
•
•
•
10
It allows comparison of different power configurations
Different bus cable designs
Different grounding and shielding concepts
Stavelets end of summer 2010, realistic stave 09 2011 ?
Plans for DC2DC powering option on stavelets
Stavelets allow option choices
Serial Powering stavelets
W
M
S
A plug-in board, to be inserted into the
protection circuit PCB, has been designed at
RAL. It allows testing of different powering
schemes (W,M,S) on stavelets.
11
Stavelets Module production status
• 6 modules produced and are
under testing
• 6 additional hybrids have die
attached and are undergoing
bonding
• This will yield modules for the
first 2 stavelet sides + 1
additional module for
irradiation by the end of May
12
Serial Powering test results
• strong variations of current are unexpected feature of ABCN-25
• minor design fault , will be amended in next versions
• hybrid current has sharp peaks (~1.5 A over ~ms) challenging test of SP
circuitry
13
W scheme - Results
Features
• one shunt device per chip
• one shunt regulator per
chip
Conceptual diagram of the distributed
shunt
IR camera pictures during operation
Over-current protection distributes excess current
equally
after turning off the clock in 10 chip hybrid
14
• no external components
• sophisticated overcurrent protection
Stress test. Shunt stands huge
currents (~ A) without damage
W scheme - Results
Corresponding ENC plot
• W scheme performs well if triggers
timed to avoid current bump
Bumps and the voltages @ 3.8A
• DAQ could be set-up to
accommodate bump if required.
15
15
Separated
bumps and the voltages @ 4.2A
450e- RMS Corresponding ENC plot
M scheme - Results
schematic of external control
Schematic of shunt driver
implementation with SPi and discretes
implementation in ABCN-25
Excellent performance. Next version in 130 nm
16
M scheme - Results
Response to a current step
Start-up
| Shut-down
• The transient response to a current step is excellent
• The start-up is fine
• ENC is as simulated and same as for independent powering
ENC for all channels of the 20 chip hybrid
17
SPi
Serial Power interface. Generic chip in 0.25 µm CMOS. Designed by M. Trimpl
(FNAL), M. Newcomer, N.Dressnandt (Penn), specs by RAL.
SPi on test PCBs
2.7 mm
5.5 mm
Two shunt regulator schemes
Data communication/ AC coupling
Power management
Monitoring/alarms
18
• 68 I/O bumps
• 76 power bumps
• Minimum pitch 275 µm
Preliminary - Modules test results
Using SCTDAQ +BCC powered from hybrid, noise performance of DC and AC-referenced hybrids are the
same within spread of measurement and improved relative to discrete 3.3 V LVDS repeater boards
Ultimate noise performance could be improved with better strobe delay settings, trim files and improved
stand grounding
19
Serial Powering system design
The power to the chain of loads in the SP scheme is provided by a current source
Isrc ver.1.0
• The first dedicated current source (CS)
prototype was designed, built and tested: very
good performances (J.Stastny, ASCR)
20
Isrc ver.2.0
• The 2nd version includes overvoltage
protection, isolated USB interface and
programmable PID coefficients for system
tuning.
Serial Powering system design
programmable CS version 2 block diagram
• specifically designed for stave09, it should work well also
for next development involving ABCN130
• up to 6A, 2mA I setting, 80V compliance, USB
• test in progress at RAL
21
SP Protection schemes
Whilst demonstration staves have generally been reliable:
• Need to cope with open circuit module failure
• Need to cope with a module becoming excessively noisy
• Need to bypass a module
We want to provide a system to “short out” each module under control of DCS or
automatically:
• Voltage across shorted module should be small (<100mV)
• Area of components and number of control lines must be small
• Automatic shorting (over current and over voltage protection)
• Protection circuit must draw no (minimal) power when module active
• Ability to put modules into “stand by” (low power state)
22
SP Protection schemes
An independent protection and module by-passing function would improve
reliability of SP
LBL Discrete schematic – PCB implentation
Vpl
16
PLUS
9,10,11,12
Slow
Control
Gate
4
Vph
3
R2
4
R3
1K
100K
3
MM5Z24V
10K
1,2,5,6
3
7,8
5,6
AO6404
ZXTDA1M832
1
4
R1
2SC4102
DS2413
Data
1
2
6
2
MMSZ4683T1
•
AO6404
4
5,6,7,8
MINUS
1,5
15
GND
1,2,5,6
3
1K
14
Realtime
Gate
The discrete version is functional and
will be on the stavelets.
• Plan to get the custom implementation
out spring/summer (2010).
23
SP High Voltage schemes
Standard HV powering: one HV per
module
Alternative HV powering: one HV supply per M
modules
• Serial Powering is compatible with the use of a single HV supply for several modules
• Each sensor is dynamically connected to current source ground through output
impedances of the chain of shunt regulators
• Low shunt output impedance is crucial to achieve good ‘grounding’ and reduce noise
24
Stavelet construction progress
at RAL
Module placement area
Rotate stage
25
Module placement arm
Y stage
ZX stages
Stavelet test box
RAL expects to:
• Start placing modules as soon as they arrive and are
tested.
• Module mounting tooling is almost complete
• Test gluing patterns for coverage.
• Appropriate cooling is being put in place.
• Test stavelets (in conjunction with Liverpool/LBL)
Conclusions
All elements of a serial powering system have been specified and prototyped including:
•
•
•
•
•
Current source(s)
Shunt circuitry (external, integrated into FE chips)
Protection circuitry
HV distribution
AC coupling of control and data signals
A series of SP staves have been built and operated with excellent
performance.
A first ABCN demonstrator stavelet is planned for this year (10), to assess:
•
•
•
•
•
Different serial powering approaches
Bypass and protection
AC coupling
Dc2DC powering approach
System issues
Will then implement all the above features in a single large-scale object: ATLAS stave09
26
Backup-HSIO Development
61
• Next steps are to:
– Readout dummy module with HSIO+2 power
protection boards (PPB)+ 2 BCC with dummy
module
– Get noise reference with HSIO+2 BCC + real
module in test frame
• Should be finished in next 1-3 weeks
Backup -Module Mass
• Weight confirms hybridto-sensor glue ~40 mm
thick
• 1.53 %X0 for two
modules consistent with
1.49 %X0 estimated at
NIKHEF workshop
– Increase now is due
to 5-layer (4+1 shield)
vs. 4-layer (3+ 1
shield) hybrid build
(+0.06% X0 relative to
NIKHEF estimate)
Backup -Some of our SP set-ups
for strips
Initial ATLAS SCT silicon strip
tests at RAL
Stave 06
6 SP hybrids
with sensors at
LBNL and RAL
• several integrated supermodules with SP have
been constructed.
• Performance is excellent. However SP
electronics was still based on commercial discrete
components
Stave 07 - 30 SP hybrids/sensors
ABCD BeO hybrid
with SP interface PCB
Backup - System tests of SP staves
Thick Film Hybrid for 6 ABCD chips with
integrated Serial Powering circuitry:
requires ~0.75A at 4V
We have verified that:
1. Noise is not an issue
2. AC coupled (M)LVDS works
3. SP uses little extra real estate
4. Can use single HV line / strip stave
stave working well !
Stave07: 30 module stave with ABCD
30 * 4V = 120V (ABCD, 800nm)
Future: 24 * ~1V = 24V for 130nm ABCN