User's Guide
SCAU040 – March 2010
Quad Sine-Wave Clock Buffer Evaluation Board
1
2
3
4
5
6
7
8
Contents
General Description .........................................................................................................
1.1
Features .............................................................................................................
Signal Path and Control Circuitry .........................................................................................
Getting Started ..............................................................................................................
Power-Supply Connections ................................................................................................
Output Clock .................................................................................................................
Enabling/Disabling Outputs ................................................................................................
Bill of Materials ..............................................................................................................
Schematic ....................................................................................................................
2
2
2
3
3
3
3
4
6
List of Figures
1
CDC3S04 Evaluation Board ............................................................................................... 2
2
Schematic – (1 of 3) ........................................................................................................ 6
3
Schematic – (2 of 3) ........................................................................................................ 7
4
Schematic – (3 of 3) ........................................................................................................ 8
1
Clock Source
List of Tables
2
3
4
5
................................................................................................................
Supply source ...............................................................................................................
Outputs on the CDC3S04EVM ............................................................................................
Jumpers to Control the CDC3S04 ........................................................................................
Bill of Materials ..............................................................................................................
3
3
3
3
4
I2C is a trademark of NXP B.V Corporation.
SCAU040 – March 2010
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Quad Sine-Wave Clock Buffer Evaluation Board
Copyright © 2010, Texas Instruments Incorporated
1
General Description
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Figure 1. CDC3S04 Evaluation Board
1
General Description
The CDC3S04 is a four-channel low-power sine-wave clock buffer. It can be used to buffer a single master
clock to multiple peripherals. The four sine-wave outputs (CLK1–CLK4) are designed for minimal
channel-to-channel skew and ultralow additive output jitter. Each output has its own clock request input
which enables the dedicated clock output. These clock requests are active-high (can also be changed to
be active-low via I2C™), and an output signal is generated that can be sent back to the master clock to
request the clock (MCLK_REQ). MCKL_REQ is an open-source output and supports the wired-OR
function (default mode). It needs an external pulldown resistor. MCKL_REQ can be changed to wired-AND
or push-pull functionality via I2C.
This evaluation module (EVM) is designed to demonstrate the electrical performance of the
CDC3S04.Throughout this document, the acronym EVM and the phrases evaluation module and
evaluation board are synonymous with the CDC3S04 EVM. Figure 1 illustrates the CDC3S04 EVM.
For optimum performance, the board is equipped with 50Ω SMA connectors and well controlled 50Ω
impedance microstrip transmission lines.
1.1
Features
•
•
•
•
2
Easy-to-use evaluation board to fan out low phase noise
Easy device setup
Control pins configurable though jumpers
Board powered using USB or external supply
Signal Path and Control Circuitry
The CDC3S04 EVM has a TCXO soldered. If the customer wants to try out a different source then the
EVM allows routing the external signal to the CDC3S04. Resistors must be solder or desolder. See
Table 1 for each configuration.
2
Quad Sine-Wave Clock Buffer Evaluation Board
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Getting Started
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Table 1. Clock Source
3
Component
TCXO on board
External input
R80
Not mounted
Not mounted
R74
Not mounted
Not mounted
R98
0R0
Not mounted
R97
Not mounted
0R0
C8
15 pF
15 pF
Getting Started
The CDC3S04EVM has self-explanatory labeling and uses similar naming conventions as the CDC3S04
product data sheet (SCAS883). In this user’s guide, all words in boldface and italic print reflect the
actual labeling on the EVM.
4
Power-Supply Connections
The CDC3S04EVM has three pins that require external supply. Those pins are VDD_ANA, VDD_DIG and
VBAT. These supplies can come from the USB or using an external power supply. See Table 2 for further
information.
Table 2. Supply source
USB
External Power Supply
R113 = 0R0
J50 OFF
R112 = Not mounted
J51 OFF
J50 ON
P3 = VDD_ANA
J51 ON
P1 = VDD_DIG
Also the CDC3S04 has an LDO build in that generates the supply for the TCXO. This voltage can be
generated using the TPS71219 on board or the P2 connector.
5
Output Clock
The outputs of the CDC3S04 are available on any of the SMA connectors
Table 3. Outputs on the CDC3S04EVM
6
SMA
Output
J17
CLK1
J68
CLK2
J21
CLK3
J20
CLK4
Enabling/Disabling Outputs
The CDC3S04EVM has several jumpers that can control the output enable of the CDC3S04.
Table 4. Jumpers to Control the CDC3S04
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Jumper
Function
J66
REQ1
J67
REQ2
J68
REQ3
J69
REQ4
J74
RESET
Quad Sine-Wave Clock Buffer Evaluation Board
Copyright © 2010, Texas Instruments Incorporated
3
Bill of Materials
7
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Bill of Materials
Table 5. Bill of Materials
4
QTY
Value
Designator
PKG/CASE
Manufacturer
Lot Number
10
0.01uF
C8, C12, C13, C33, C35,
C53, C58, C63, C67, C71
0402
Venkel
C0402X7R500-103KNE
15
0.1uF
C4, C5, C6, C16, C34, C36,
C49, C54, C64, C68, C72,
C55, C73, C75, C76
0402
Venkel
C0402X7R160-104KNE
2
0.22uF
C3, C74
0402
Venkel
C0402X5R6R3-224KNE
1
0.47uF
C7
0402
Murata Electronics North Am
GRM155R61A474KE15D
5
1.0uF
C51, C62, C66, C70, C48
0402
Murata Electronics North Am
GRM155R61A105KE15D
5
10pF
C1, C2, C43, C46, C47
0402
Venkel
C0402COG500-100JNE
3
15pF
C31, C32, C61
0402
Venkel
C0402COG500-150JNE
2
2.2ìF
C59, C60
0402
Murata Electronics North Am
GRM155R60J225ME15D
1
10000pF
C14
0603
Tdk Corporation
C1608X7R1H103K
1
10ìF
C77
0603
Panasonic
ECJ-1VB0J106M
1
0.1ìF
C57
0805
Kemet
C0805C104J5RACTU
10
4.7ìF
C41, C42, C44, C50, C52,
C56, C65, C69, C78, C79
0805
Venkel
C0805X5R250-475KNE
2
10ìF
C11, C15
3216-18 (EIA)
Kemet
B45196H3106K109
1
100K
R73
7.04 x 6.71 x 4.8
Bourns Inc.
3361P-1-104GLF
7
0R0
R98, R106, R108, R112,
R113, R114, R115
0402
Panasonic - Ecg
ERJ-2GE0R00X
2
1.00K
R124, R125
0402
Venkel
CR0402-16W-1001FT
1
1.00M
R7
0402
Venkel
CR0402-16W-1004FT
1
1.40K
R3
0402
Panasonic - Ecg
ERJ-2RKF1401X
3
10
R70, R75, R77
0402
Venkel
CR0402-16W-10R0FT
12
10.0K
R79, R94, R95, R99, R100,
R101, R102, R103, R104,
R109, R116, R123
0402
Rohm
MCR01MZPF1002
1
100K
R8
0402
Yageo America
RC0402FR-07100KL
7
22.1
R107, R117, R118, R119,
R120, R121, R122
0402
Panasonic - Ecg
ERJ-2RKF22R1X
1
3.32K
R78
0402
Panasonic - Ecg
ERJ-2RKF3321X
1
30.1K
R111
0402
Venkel
CR0402-16W-3012FT
1
31.6K
R110
0402
Panasonic - Ecg
ERJ-2RKF3162X
2
33.2
R1, R2
0402
Venkel
CR0402-16W-33R2FT
1
33.2K
R105
0402
Panasonic - Ecg
ERJ-2RKF3322X
1
332
R76
0402
Vishay/Dale
CRCW0402332RFKED
1
47.5K
R9
0402
Venkel
CR0402-16W-4752FT
1
5.1K
R96
0402
Venkel
CR0402-16W-5101FT
2
5.62K
R5, R6
0402
Venkel
CR0402-16W-5621FT
1
USB - Mini AB type
USB1
SMT
Jae Electronics
DX3R005HN2E700
1
38.4MHz
X1
4-SMT
KDS
1XXD38400CAA
1
TPD2E001DZDR
U7
4-SOP
Texas Instruments
TPD2E001DZDR
1
LLSD103A-7
D1
Mini MELF
Diodes Inc
LLSD103A-7
5
50
L6, L7, L8, L9, L10
1206
Murata Electronics North Am
BLM31PG500SN1L
1
TPS71219DRCT
U5
10-SON
Texas Instruments
TPS71219DRCT
1
CDC3S04YFFR
U4
20-DSBGA
Texas Instruments
CDC3S04YFFR
3
LED - Green Clear
D3, D4, D8
1206
Lite-On
LTST-C150KGKT
1
LED - Red Clear
D5
1206 (3216)
Cml Innovative Technologies
CMD15-21VRC/TR8
2
PTS635SL25SMTR LFS
SW2, SW3
6mm x 3.50mm
C&K Components
PTS635SL25SMTR LFS
5
142-0701-801
J17, J18, J19, J20, J21
RF SMA EDGE
Emerson Network Power Co
142-0701-801
2
Test Loop - Black
J72, J73
0.1"
Components Corporation
TP-105-40-00
6
1X2
J7, J11, J12, J50, J51, J52
0.1"
HTSW-150-08-G-S
K10000012278
Quad Sine-Wave Clock Buffer Evaluation Board
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Bill of Materials
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Table 5. Bill of Materials (continued)
5
1X3
J66, J67, J68, J69, J74
0.1"
HTSW-150-08-G-S
K10000012278
4
Banana Plug - Metal
P1, P2, P3, P4
4mm
Emerson Network Power Co
108-0740-001
5
4-40/0.25"- Screws
MH1, MH2, MH3, MH4,
MH5
Building Fasteners
PMSSS 440 0025 PH
5
0.75"
MH1, MH2, MH3, MH4,
MH5
14
DNI
C9, C10, R26, R27, R28,
R29, R30, R31, R32, R33,
C45, R74, R80, R97
2
DNI
J70, J71
1
DNI
U3
1
DNI
Y1
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5
REQ1
V
REQ2
4
3
1
1
2
2
V_LDO
0R
R98
0R
R97
MCLK_IN_2
2
R95
10k
J66
Jumper3
2
R100
10k
J67
Jumper3
R99
10k
TCXO
GND
GND OUT
X1
R74
500R
MCLK_IN_1
R94
10k
1
2
J19
1
1.8V_Vdd_DIG
3
1.8V_Vdd_DIG
2
3
4
5
1
2
1
2
1
C8
R96
5k1
REQ3
15PF
2
E3
SDAH
R102
10k
J68
Jumper3
Adj_V
REQ4
REQ3
REQ2
REQ1
VBAT
2
R104
10k
J69
Jumper3
CDC3S04
VLDO
MCLK_REQ
CLK4
CLK3
CLK2
CLK1
1.8V_Vdd_DIG
R103
10k
1.8V_Vdd_DIG
REQ4
REQ3
REQ2
REQ1
/Reset
MCLK_IN
ADR_A0
SDAH
SCLH
U4
1.8V_Vdd_ANA
REQ4
C49
100nF
E2
C1
C3
A1
A3
B2
MCLK_IN B1
D4
E4
SCLH
RESET
R101
10k
1.8V_Vdd_DIG
1.8V_Vdd_DIG
1
2
R80
500R
3
1
B3
SMA-EDGE
3
1
D1
VDD_DIG
GND_ANA
B4
VDD_ANA
GND_DIG
D2
3
1
CLK4
CLK3
CLK2
CLK1
MCLK_REQ
V_LDO
2
R123
10k
J74
Jumper3
R116
10k
1.8V_Vdd_DIG
0R0
R106
MCLK_REQ_P
22R
R107
C48
800nF
RESET
E1
D3
C2
C4
A2
A4
100n
C55
SMA-EDGE
R31
R
DNP
J20
CLK4_1 1
SMA-EDGE
100n
C76
R29
R
DNP
R32
R
DNP
R33
R
DNP
J21
CLK3_1 1
J18
CLK2_1 1
R28
R
DNP
1.8V_Vdd_ANA
100n
C73
1.8V_Vdd_ANA
SMA-EDGE
SMA-EDGE
MCLK_REQ_P
R125
1k
R124
1k
1.8V_Vdd_DIG
C34
100nF
J73
HEADER 1
C33
10nF
1.8V_Vdd_DIG
C35
10nF
The outputs of the CDC4S04 need to have the minimum
amount of capacitance to GND and VDD.
100n
C75
R30
R
DNP
1.8V_Vdd_ANA
R26
R
DNP
J17
CLK1_1 1
R27
R
DNP
5
4
3
2
5
4
3
2
1.8V_Vdd_ANA
3
Copyright © 2010, Texas Instruments Incorporated
1
Quad Sine-Wave Clock Buffer Evaluation Board
1
6
5
4
3
2
C36
100nF
1.8V_Vdd_ANA
M HOLE1
MH5
1 1
M HOLE1
MH4
1 1
M HOLE1
MH3
1 1
M HOLE1
MH2
1 1
M HOLE1
MH1
1 1
8
5
4
3
2
1.8V_Vdd_ANA
Schematic
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Schematic
Figure 2. Schematic – (1 of 3)
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JTAG
J70
1
2
3
4
5
6
0R0
C12
10nF
C13
10nF
ADC_0
ADC_1
C6
100nF
MCLK_REQ
C5
100nF
1.8V_Vdd_MSP
+ C11
10uF
C16
100nF
C7
470n
DVcc
AVcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Test/SBWTCK
TDO
TDI
TMS
TCK
RST/NMI/SBWTDIO
measurement for
Vdd_ANA & Vadj
+ C15
10uF
SW2
SW PUSHBUTTON
1.8V_Vdd_MSP
R108
C10
2.2nF DNP
R9
47K
1.8V_Vdd_MSP
Y1
4MHz
C3 220nF
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
P7.0/CB8/A12
P7.1/CB9/A13
P7.2/CB10/A14
P7.3/CB11/A15
P5.0/VREF+/VeREF+
P5.1/VREF-/VeREFU3
AVcc1
P5.4/XIN
MSP430F5529
P5.5/XOUT
AVss1
P8.0
P8.1
P8.2
DVcc1
DVss1
Vcore
C45 15PF
C9 15PF
SW3
SW PUSHB
DNP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
R3 1k4
R8
100K
C79
4u7
22R
22R
22R
22R
22R
22R
R122
R121
R120
R119
R118
R117
MSP_EN_Adj
RESET
REQ1
REQ2
REQ3
REQ4
P7.7/TB0CLK/MCLK
P7.6/TB0.4
P7.5/TB0.3
P7.4/TB0.2
P5.7/TB0.1
P5.6/TB0.0
P4.7/PM_NONE
P4.6/PM_NONE
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.4/PM_UCA1TXD/PM_UCA1SIMO
DVcc2
DVss2
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.0/PM_UCB1STE/PM_UCA1CLK
P3.7/TB0OUT/SVMOUT
P3.6/TB0.6
P3.5/TB0.5
P3.4/UCA0RXD/UCA0SOMI
P6.3/CB3/A3
P6.2/CB2/A2
P6.1/CB1/A1
P6.0/CB0/A0
!RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P5.3/XT2OUT
P5.2/XT2IN
AVss2
V18
VUSB
VBUS
PU.1/DM
PUR
PU.0/DP
VSSU
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
P2.4/TA2.1
P2.5/TA2.2
P2.6/RTCCLT/DMAE0
P2.7/UCB0STE/UCA0CLK
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
R7
1.0M
C46
10PF
2
C2
10PF
1
C1
10PF
R2 33
R1 33
VBUS_4v3
C14
10000PF
C4 100nF
1.8V_Vdd_MSP
J7
I2C
C31
15pF
R5
5.6K
2
1
IO2
3
4
C32
15pF
R6
5.6K
1.8V_Vdd_MSP
2
1
J12
2
J11
1
TPD2E001DZD
IO1
GND Vcc
U7
USB Connection
with ESD protection
VBUS_4v3
SDAH
SCLH
C78
4u7
D1
LL103A
5
4
3
2
1
R105
33k
C43
10PF
VBUS_4v3
GND
IO
D+
D-
VBUS
USB1
USB_MINI-B
C47
10PF
Shield1
Shield2
Shield3
Shield4
GND1
GND2
GND3
GND4
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J72
HEADER 1
1
C74 220nF
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Schematic
Figure 3. Schematic – (2 of 3)
Quad Sine-Wave Clock Buffer Evaluation Board
7
1
2
HEADER 2
J71
VCC_Battery
1
1 2
VCC_1.8V
2
1
2
R113
0R0
R112
0R0
JUMPER
J51
VCC_Battery
D5
RED
C77
10u
JUMPER
J50
50Ohm @ 100MHz
1
2
R76
330
1
2
1
MSP_EN_Adj
C56
4.7uF
P1
1.8V_DIG
C41
4.7uF
1
1
1
1
2
8
10
NC
EN2
EN1
IN
L8
2
50Ohm @ 100MHz
C65
4.7uF
C66
1uF
C51
1uF
C69
4.7uF
L9
2
50Ohm @ 100MHz
C44
4.7uF
R109
10k
L6
2
50Ohm @ 100MHz
C50
4.7uF
JUMPER
J52
P3
1.8V_ANA
2
100nF
C57
U5
GND
T-PAD
5
11
C68
0.1uF
C54
0.1uF
C53
10nF
C70
1uF
C67
10nF
GREEN D8
2
R75
10
1
R77
10
1.8V_Vdd_DIG
1
C61
15pF
1
R70
10
R78
3.3k
ADC_1
R79
10k
VCC_Adj_V
VCC_1.8V
C60
2.2uF
P4
GND
ADC_0
1.8V_Vdd_MSP
R111
30k1
R73
60k
R110
31k6
C59
2.2uF
GREEN D3
2
C71
10nF
1.8V_Vdd_ANA
C72
0.1uF
GREEN D4
2
7
4
9
3
C58
10nF
FB2/NC
OUT2
FB1/NC
OUT1
TPS71219
NR
6
L10
1
2
Copyright © 2010, Texas Instruments Incorporated
1
Quad Sine-Wave Clock Buffer Evaluation Board
2
1
8
2
VBUS_4v3
P2
VCC_Adj_V
R115
0R0
R114
0R0
Adjustable_V
Note:
R73 + R72 = (Vout/1.25V -1) * R71
L7
2
50Ohm @ 100MHz
C42
C52
4.7uF
4.7uF
1
C62
1uF
C61 = ((3*10^5) * ((R73 + R72)+R71)) / ((R73 + R72)*R71)
C64
0.1uF
Adj_V
C63
10nF
Schematic
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Figure 4. Schematic – (3 of 3)
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Evaluation Board/Kit Important Notice
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the
product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are
not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations,
including product safety and environmental measures typically found in end products that incorporate such semiconductor
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This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
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EVM Warnings and Restrictions
It is important to operate this EVM within the input voltage range of 2.2 V to 3.6 V and the output voltage range of 2.2 V to 3.6 V .
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are
questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the
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specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 85°C. The EVM is designed to
operate properly with certain components above 85°C as long as the input and output ranges are maintained. These components
include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of
devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near
these devices during operation, please be aware that these devices may be very warm to the touch.
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