1472 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 7, JULY 2007
Abstract— As the tuning range of integrated LC -VCOs increases, it becomes difficult to co-design the active negative resistance core and the varactor size optimally for the complete frequency range.
The presented VCO design solves this by adjusting the size of the negative resistance transistors with a switched active core, with the additional benefit that this reduces parasitics and hence allows to achieve better phase noise and an even higher tuning range. Also the VCO gain variations are counteracted by employing an analog varactor that can change in size. The implementation in 0.13- m
CMOS shows a tuning range from 3.1 to 5.2 GHz, with a power consumption varying accordingly from 7.7 to 2.1 mA from a 1.2 V supply. The measured phase noise is 118 dBc/Hz at 1 MHz from a 4-GHz carrier.
Index Terms— Phase noise, tuning range, voltage-controlled oscillator.
I. I NTRODUCTION
M OBILE system design is rapidly changing from singlestandard systems to multi-mode terminals. The design of these terminals is focusing more and more on software-defined radio (SDR) front-ends [1], instead of combining multiple single-mode front-ends. The major challenge for these systems is to add a large amount of reconfigurability and flexibility into all radio building blocks without impairing the radio performances, power consumption and time-to-market. Because of the widely varying carrier frequencies, an extreme range of local oscillator (LO) carrier frequencies is needed.
To generate those LO signals, several frequency generation techniques have been proposed to relax the tuning range specifications of the voltage-controlled oscillator (VCO). They use division [2], [3], mixing [4], multiplication [5] or a combination of these [6]. However, to make these systems efficient in terms of phase noise and power consumption, the VCO tuning range still has to be maximized.
To reach the stringent phase noise specifications for today’s mobile communication systems, most RF transceiver ICs use
LC -VCOs. Frequency tuning of LC -VCOs is often done by changing the capacitance value of the resonant tank using varactors. Switched or controlled inductor designs have been reported
[7], [8], but it remains difficult to cover the desired wide band continuously and to limit the deterioration of the phase noise performance caused by the insertion of these switches.
Instead of using a single large varactor to tune the frequency, a mixed discrete/continuous tuning scheme is usually chosen [9],
[10]. A small varactor is used for fine continuous tuning whereas larger steps are realized by digitally switching capacitors in and out of the resonant tank. This has two advantages: the VCO gain is lower, allowing easier phase-locked loop (PLL) design, and digitally switched varactors have a higher ratio between the capacitance in the on-state state ). A higher
) and the capacitance in the offratio allows a larger VCO frequency tuning range.
However, as the tuning range of a VCO is increased and exceeds the typical 20% range obtained in many designs, new problems and trade-offs appear that need a solution. In this design we will tackle the two main problems encountered in wideband
LC -VCOs. First, the negative resistance required to maintain oscillation varies a lot over the frequency range, leading to significant overhead when a fixed active core is used. Secondly, the large variation of the VCO gain ) across the whole tuning range creates problems for optimal and stable PLL design.
Solutions are proposed for both problems and are explained in Sections II and III. Then, the final VCO architecture, its calibration and its implementation in the frequency synthesizer are presented in Sections IV to VI. Finally, measurement results and conclusions are given.
II. T ANK L OSS V ARIATIONS
A. Required Negative Resistance
In the target frequency range ( GHz), MOS varactors in modern CMOS processes achieve quality factors of 40 or even higher [11], such that the losses in the oscillator tank are usually dominated by the inductor. The inductor loss can be modeled by a series resistance , which we will consider in this simple example to be frequency-independent. This simplification is of course not completely valid, since extra losses due to e.g. the skin effect will increase the resistance at higher frequencies, but that does not change the general conclusion we will make.
The required negative resistance needed to compensate the inductor losses is given by [17]
(1)
Manuscript received November 17, 2006; revised February 26, 2007. This research was carried out in the context of IMEC’s multimode multimedia program which is partly sponsored by Samsung.
D. Hauspie was with IMEC,Wireless Research, B-3001 Leuven, Belgium, and is now with Melexis, Tessenderlo, Belgium.
E.-C. Park is with Samsung Advanced Institute of Technology, Yongin
44-712, Korea.
J. Craninckx is with IMEC, Wireless Research, B-3001 Leuven, Belgium
(e-mail: jan.craninckx@imec.be).
Digital Object Identifier 10.1109/JSSC.2007.899105
where is the total tank capacitance and is the oscillation frequency which is of course given by the simple formula with L the inductance value. If we want the oscillation frequency to change for example by a factor 2, the total capacitance of the resonant tank has to be changed by a factor 4.
From (1), we see that the required negative resistance needed to maintain oscillation will also change by a factor 4. The required
0018-9200/$25.00 © 2007 IEEE

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Fig. 1. Phase noise and tuning range comparison. (a) Circuit schematic. (b) SpectreRF phase noise simulation.
transconductance of the active core is 4 times higher at the lower end of the frequency tuning range than at the higher end.
In a traditional design the active core will be designed for the toughest case, i.e., for the lowest frequency. For the highest frequency the active core is largely over-dimensioned, a factor
4 in our example. As this is obviously a waste of power, the oscillator bias current should be scaled over the frequency range.
The question to be raised here is whether or not we should focus on the optimal bias current or on the optimal transconductance for the wideband oscillator design.
It we focus on the required transconductance for reliable oscillator start-up, a MOS transistor in the quadratic region would require a change in current by a factor 16 to obtain a factor 4 change in transconductance. This is not practical and does not allow good performance since the operating point of the transistors changes too much (from strong to weak inversion), and the oscillator ends up in the current-limited regime, which is normally not optimal for phase noise performance. If transconductance is important, it would be better to change the current only by a factor of 4, and simultaneously also change the size of the transistor by a factor of 4 such that the operating point remains the same.
In the next section, a better analysis of the wideband oscillator phase noise will show the best trade-offs to be made.
B. Phase Noise and Tuning Range Considerations
Recent phase noise theory based on the impulse sensitivity function (ISF) theory of phase noise, together with a linear-timevariant circuit analysis [12], [13], has shown however that it is not the small-signal transconductance that must be considered for optimal phase noise. Instead, phase noise only depends on the large-signal oscillation amplitude, and that one is proportional to the bias current and the parallel tank resistance. Again considering our simplified example of a tank loss dominated by a frequency-independent inductor series resistance , the equivalent parallel tank resistance is given by
(2)
So if the frequency doubles, quadruples and the bias current can be reduced by a factor of 4 to maintain the same oscillation amplitude and hence also phase noise, without touching the size of the active core transistors. The negative transconductance will be larger than required by (1), but this will not affect the oscillator phase noise.
Two arguments can be brought forward that encourage us to look for a solution that does benefit from changing the size of the transistors. First, as already pointed out in [13], the phase noise analysis changes drastically when parasitics are taken into account. The bias current source in our design was not cascoded, because of the limited headroom in the low power supply
(1.2 V) used, nor did we employ a series inductor resonating at the double frequency [14], because that technique is narrowband in nature. The total tank capacitance is also to a large extend not differential, but contains parasitics to ground in the inductor, the varactors, and certainly the transistors themselves. Because of these two parasitic effects noise from the transistors can find a

1474 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 7, JULY 2007
Fig. 2. Possible unit active core configurations. (a) Switches at the gate. (b) Switches at the drain.
path to ground, and the phase noise degrades by several decibels from the ideal case [13].
The second argument is even more important, because it shows the influence on the achievable tuning range. The key to a wideband VCO is of course to have a tank capacitance that consists as much as possible of varactors and as little as possible parasitics. The smaller the active transistors, the better.
Here it is obvious that if we could eliminate some of the parasitics at high frequencies, the tuning range could be extended considerably. Fig. 1 compares the simulated phase noise of two
VCOs designed according to the two possible strategies. In both cases the oscillator is simulated at its highest frequency, i.e., when the required current is minimal. All the varactors are in their ‘off’ state, and the bias current is set to 2 mA. In the first case the active core transistor sizes are set to the value they would be designed for in the worst case, i.e., they are sized 4 times larger such that they will be able to handle the quadruple current required for oscillation in the low frequency range. The varactor is sized such that the oscillation frequency is 5 GHz.
The simulated phase noise is shown in Fig. 1(b) and equals dBc/Hz at 1 MHz offset. To evaluate the tuning range of this approach, the oscillation frequency with all the varactors in the ‘on’ state and a 4X higher bias current is also simulated, which results in a lower frequency range of 3.17 GHz.
In the second case, the transistors are sized 4 times smaller for high-frequency operation only, leading to smaller parasitic capacitance, so the varactor size is enlarged to compensate this and keep the frequency at 5 GHz. In this case the simulated phase noise is 116.4 dBc/Hz at 1 MHz offset, i.e., 3.5 dB lower.
The oscillation amplitude is similar in both cases, but the lower phase noise can be explained by the reduced effect of the parasitics in the oscillator. Moreover, the lowest frequency obtained now (assuming larger bias current and larger transistors in that simulation) is as low as 2.77 GHz, because of the large varactor used. These results clearly show the benefits of scaling the active core size for better phase noise and tuning range performance.
C. Switched Core Architecture
The basic idea behind the solution presented here is thus to not only scale the biasing current of the active core, but to simultaneously change the size of the transistors as well in order to keep parasitics at a minimum, which is beneficial for both the phase noise performance as for the achievable tuning range.
Therefore, the active core will be constructed from an array of core units, which can be turned on or off when necessary. In each of these core units, switches must be added to turn the active transistors on or off. The position and size of those switches has to be considered carefully, to avoid degrading the oscillator phase noise performance as well as to ensure that additional parasitic capacitances are small.
The starting point is the classical active VCO core, which in the example presented here uses both nMOS and pMOS crosscoupled pairs. A pMOS current source is used since it has less
1/f noise than an nMOS source. As already stated earlier, no high output impedance current source could be realised here because of the limited voltage headroom and the wideband operation.
The three terminals of a transistor (drain, source and gate) provide basically three positions to de-activate the transistor.
Fig. 2(a) shows a basic core schematic where switches are added in series with the gates of each transistor to cut them out of the oscillator circuit. Since the gates cannot be left floating, four additional switches (small, not shown) are also inserted to pull the gate-source voltage to zero. Sizing the four switches SW1–4 turns out to be a very difficult trade-off between the resistance in the on-state and the parasitic capacitance in the off-state. The series resistance of the switch is in series with the gate resistance of the active transistor, and hence has the same transfer function of its thermal noise to the oscillator phase noise. Since that noise contribution is relatively large, the switches have to be sized wide enough to avoid phase noise degradation, and hence the large parasitics severely limit the tuning range.
The configuration in Fig. 2(b) where the switches are placed in series with the drain is much more convenient. The series

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Fig. 3. Schematic of one oscillator core unit.
resistance in the on-state can be much larger, since it does not have a large effect on the oscillator phase noise performance. In first order, it can be regarded as being a resistance in series with a current source or a transconductance, such that there is even no transfer of its noise to the output. Of course, several other considerations do put a limit on the maximum series resistance or minimum transistor width.
The circuit schematic can still be improved. Since the current is flowing either from the pMOS to the tank, or from the tank to the nMOS transistor, but never flows from the pMOS to the nmos, the two drain switches can be grouped into one common switch. This has the advantage of providing a two times smaller parasitic capacitance for the same series resistance. This is depicted in Fig. 3.
As is clear from the analysis in Section II.B, it is of utmost importance that together with the negative resistance, also the parasitic capacitance is removed from the oscillator tank to ensure a large tuning range. In the ‘on’ state the switch is closed, and the parasitic capacitance is then determined by the draingate and source-gate capacitance of the switch, plus the drain and gate capacitance of the active transistors. The small-signal
(single-ended) ON -capacitance is given by ages will be pulled to ground, and this has a different effect on the three transistors.
• First, the active nMOS transistors (M1–M2) keep their gate connected to the LC -tank, and they are now in the trioderegion since they have a positive gate-source voltage and zero drain-source voltage. Basically, their gate capacitance remains a parasitic of the LC -tank.
• Second, the active pMOS transistors (M3–M4) are turned off because they also have a positive gate-source voltage.
The gate capacitance therefore drops considerably, although special attention should be given to the fact that for large signals the transistor can enter the accumulation mode, where the capacitance is again high [15]. Simulations have shown here that the large-signal capacitance is hardly affected by the accumulation effect.
• Third, the switch transistors (SW1–SW2) also turn off and only the drain parasitics stay attached to the gate, which results in a large drop is capacitance.
To summarize, we see that the nMOS capacitance stays fixed, the pMOS reduces, and the switch disappears almost completely. This information is of course used in the sizing of the different transistors. The nMOS is made small times bigger m per unit) and the pMOS is approximately 3 m). The largest width is given to the transistor that has the largest ratio of / , so the switch size is set to m. With this structure a ratio close to 3 is obtained, without any significant contribution of the switches’ series resistance to the overall phase noise.
So in fact we have been able to use the negative resistance core as a varactor. For high oscillation frequency, the capacitance is low and there is no negative resistance. For lower frequencies, more and more core units are gradually activated, the total bias current increases to keep the oscillation amplitude steady and the parasitic capacitance increases, helping the “normal” varactors in their goal to increase the total tank capacitance.
III. S ENSITIVITY V ARIATIONS
The second problem solved in the presented design is the variation of the VCO sensitivity for large tuning-range VCOs. A change in the control voltage the analog varactor capacitance results in a change in
. This causes a change in frequency f. The size of this frequency change depends on the relative importance of the analog capacitance change with respect to the total tank capacitance (that consists for a large part of digitally switched varactors).
(3) which is obviously larger than the parasitics of a simple negative resistance because of the added switch parasitics, but that is not an issue. Indeed, the core units are only activated when the oscillation frequency is lowered, and hence a larger capacitance is tolerated. Another remark to be made is of course that for the oscillator the large-signal effective capacitance must be considered, but these cannot be written down in a simple equation as above.
To estimate the capacitance in the OFF state, several effects have to be considered. When the switches open, the drain volt-
(4)
If we go back to the example of the VCO with a frequency ratio of 2, we have seen that the tank capacitance has to change by a factor 4. As can be seen from (4), the VCO frequency sensitivity will then change by a factor . In this example the nonlinearity of the CV -curve of the varactor has been neglected, but typically the varactor is used in the middle of its tuning range, where this curve is rather linear.
Such a large change in VCO gain gives serious problems for the surrounding PLL design. Large variations of the VCO gain

1476 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 7, JULY 2007 switched core units are employed, in parallel with a fixed negative resistance that has the size of about 10 units. This allows controlling the negative resistance generated by the VCO core to be tuned over a factor 4, as was required for a factor 2 tuning of the oscillation frequency. Correspondingly, the total current of the active core will vary between 2.1 mA and 8.5 mA, whereas the bias circuit consumes 0.55 mA.
The analog varactor consists of 15 small units and is controlled by . That digital code actually consists of two control words. Four bits are used to set the number of varactors that must be connected to the analog control voltage
Fifteen other bits are used to set the varactor control to power
.
(1) or ground (0) in case it is not used for analog control. That creates a large set of extra fine tuning curves that cover the range between two adjacent coarse tuning settings.
Fig. 4. VCO architecture.
give problems for the loop stability, and will prevent to keep the
PLL bandwidth constant for optimal phase noise performance.
The solution proposed here is to make the varactor size changeable. Instead of making one big analog varactor, a number of unit analog varactors are used. These varactors can be controlled in two ways. Some units are used for analog continuous tuning, and their control node is connected to the oscillator tuning voltage . The other units are used for fine-grain discrete tuning, and their control node is connected either to the power supply or to ground. At the lowest frequency the sensitivity is low, so a large analog varactor is needed. Most of the unit varactors will be connected to the analog control voltage. At high frequencies the sensitivity is relatively high and only a small analog varactor is needed. The other units can then be used as discrete switched varactor, giving extra fine discrete tuning curves.
IV. C IRCUIT I MPLEMENTATION
Fig. 4 shows a simplified view of the complete VCO architecture implemented. A 0.13- m digital CMOS technology is used with a 1.2 V supply voltage. The VCO is roughly composed of an inductor, a switchable coarse capacitor array, a switchable fine/analog capacitor array and a switchable active core.
The inductor value was chosen small (0.75 nH) and is optimized for wide tuning range. It has a symmetrical octagonal shape [15] and is implemented in the top metal layer which has a thickness of 2 m. The next metal level is used for the underpass connections only. The typical series resistance of the inductor is about 1 .
The coarse frequency tuning is done with an array of 31 large varactors, controlled by the 5-bit control word . In combination with those varactors, active core units (control word
) add the necessary negative resistance and also add some extra capacitance when the frequency is lowered. A total of 31
V. C ALIBRATION
As there are many control bits to properly set the frequency and gain of the VCO, and as the required settings of those bits are partially dependent on process, temperature and voltage variations, a calibration sequence is needed to identify the correct setting for each desired center frequency. At power-up time, before actual operation, both the frequency and the frequency sensitivity can be estimated by comparing the number of divided output cycles to the number of reference crystal periods for a restricted set of control settings.
Practically, the VCO frequency is measured in free running mode. The frequency is estimated by setting the divider to a fixed number, e.g., 64 in our case. The number of periods of the divided signal is then measured during 64 periods of the 40
MHz reference clock.
(
As a first approximation, the number of active core units
[4:0]) is always set to be equal to the number of coarse digital varactors ( [4:0]). This is in principle only true in the nominal process corner. If needed, an extra calibration step could be added that measures the minimum number of units that must be activated in order to sustain oscillation.
Multiplying that number by a safety factor of e.g. 2 or 3 than guarantees a fast and reliable startup of the oscillator for each coarse frequency band setting. A static divider is used in the prescaler, so the condition ‘oscillation or not’ can easily be measured by monitoring the activity of the frequency divider output. Even if the prescaler needs a certain minimum input signal swing, that can be taken into account in the calibration by using a smaller multiplication factor.
To be able to control the analog tuning voltage without adding an extra digital-to-analog converter, we only use digital varactor control, which corresponds to an analog tuning voltage of 0 or
1.2 V. The oscillation frequency at midrange (0.6 V) and the
VCO gain is estimated from these two measurements.
Since the typical tuning curve of a MOS varactor is not linear across the whole voltage range from 0 to Vdd, we can of course not simply estimate the midrange VCO gain from the interpolation between these two points. Instead, a heuristic formula is used, based on the combination of these two points with the measured and simulated shape of the typical tuning curves, that results in a correction factor for the estimated slope. The expected accuracy of this heuristic method is below 5%, which

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For each coarse frequency band setting, a calibration routine can be summarized as follows:
1) Optionally: determine the number of active core units needed to reliably start up and sustain oscillation (otherwise use default setting)
2) Determine the center frequency
3) Determine the VCO gain associated with one small varactor by measuring de frequency difference between the on- and off-state. Based on that value, determine the number of small varactors needed to set the desired .
The other small varactors will be used to create a set of fine tuning curves
4) For each fine tuning curve a) Determine the center frequency b) Store this value in a look-up table
The data stored in the look-up table can be used during normal operation to set the best VCO configuration for the desired PLL operating frequency, and the feedback action in the PLL will determine the voltage on the analog tuning node.
Slow changes in temperature or supply voltage can be corrected by monitoring the tuning voltage during burst-mode operation of the transceiver. Two comparators on the analog tuning node can detect if the voltage is below or above a threshold voltage (min 0.4 V, max 0.8 V in our design). The VCO can then be switched to the next tuning curve (as determined during the power-up calibration routine), and the data in the look-up data must be updated.
VI. F RACTIONAL N PLL D ESIGN
A fractionalN PLL has been implemented around this VCO.
The overall PLL architecture is shown in Fig. 5. It is a traditional fourth order, type-2 charge-pump PLL with active loop filter.
The external reference clock is 40 MHz. The active loop filter has a total capacitance of 190 pF, an amount that is low enough to be integrated on chip. In line with the concept of reconfigurable building blocks in a software-defined radio, the charge pump and the loop filter values can be programmed in order to modify the loop bandwidth and the PLL output phase noise.
A dead-zone free phase-frequency detector (PFD) is used, where a controllable delay allows modifying the minimum width of the up/down pulses . Because of the limited voltage headroom, the charge pump (QP) has a simple architecture of a current source with switches as shown in Fig. 6.
The active loop filter sets the voltage at the charge pump output always around half of the power supply, so the current sources can be implemented with a large value for in order to limit their noise. To program the charge pump current it is again not beneficial to modify the biasing point of the
, current sources. Reducing the overdrive voltage leads to a large transconductance per current and hence a larger drain-source current noise. The best solution is again to keep the biasing point constant, and instead change the size of the transistors.
This has been applied in this design by dividing the charge pump in 8 small units of 25 A each, which can be activated or
Fig. 5. FractionalN PLL architecture.
de-activated by a digital control signal. If the charge pump unit must be inactive, NAND and NOR gates on the up/down control signals set the charge pump current course permanently off as shown in Fig. 6. The nominal charge pump current can thus be varied over a range of 25 to 200 A, to set the bandwidth of the
PLL in combination with the programmable VCO gain to the value optimal for the envisioned application.
The active loop filter consists of a classical impedance across an operational amplifier, followed by a passive fourth pole. The capacitance is fixed for low in-band phase noise, but again the resistance values can be programmed by a digital control word to set the desired PLL bandwidth. The typical loop bandwidth is around 200 kHz, and it can be varied over a range of 50 to 250 kHz.
The PLL reference frequency is set relatively high at 40 MHz, and the smallest division number is 75 ( GHz MHz). If we would use a classical divider consisting of dual-modulus prescaler (DMP) followed by a pulse/swallow (P/S) counter, the smallest division number is given by the square of the prescaler division factor. That limits the DMP modulus to a value of maximum eight ( is still ). With a 5 GHz VCO frequency this would mean that the P/S counter should work at MHz. To avoid the use of digital circuits at these high frequencies, we use the divider architecture proposed in [18]. It is a modular architecture with a chain of divide by cells, each time working at a lower frequency. Because each cell has the same architecture, and the architecture avoids the use of long lines, also layout is an easy task. The division ratio can be programmed to a value in the range between 64 and 127.
A MASH or cascaded 1-1-1 sigma-delta modulator provides the fractionalN operation. This architecture was chosen for its easy integration and unconditional stability [19].
VII. M
EASUREMENT
R
ESULTS
The VCO and the PLL were implemented in a 0.13- m
CMOS technology. The process has eight metal layers, of which the top metal layer has a 2- m thickness. The supply voltage is 1.2 V for all blocks. Due to the choice of this low
1.2-V supply, conversion to 90 nm and beyond is in our view straightforward. A die photo is shown in Fig. 7.
The calibration routine on the VCO was run in order to keep the VCO gain proportional to the frequency over the whole frequency range. Indeed, for best PLL design it is not necessary to keep fixed. A linear variation with frequency keeps the PLL gain (and hence also the PLL bandwidth and phase

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Fig. 6. Charge pump and loop filter schematic.
Fig. 7. Die microphotograph.
margin) constant. This can be deducted from (5), which gives the crossover frequency of a third order, type-2 charge pump
PLL [17].
(5)
If we can keep proportional to the PLL division ratio
(and hence proportional to the PLL output frequency), this relaxes the requirements of the charge pump flexibility or the margin we have to take to keep the loop stable in all frequency conditions.
Fig. 8 shows a selected set of the measured frequency response of the VCO. Only some of the 32 coarse frequency steps are shown for most of the frequency range, showing a total tuning range from 3.14 GHz to 5.2 GHz, or 49%. This tuning range is slightly smaller than the predicted 2.77 to 5 GHz range of the simple circuit in Fig. 1, but that is of course due to extra circuit parasitics. To our knowledge, this is one of the largest tuning ranges achieved with a fixed-inductor LC oscillator design.
In the upper frequency range of Fig. 8, a detail of the fine tuning steps is also shown. At this high frequency, only two of the 15 small varactors are controlled by the analog tuning voltage. The other ones can be set digitally to 0 or 1, resulting in an extra set of 14 fine tuning curves. The plot shows that there is enough overlap between consecutive curves. In the lower frequency range (not shown), the coarse tuning curves are closer together because the total capacitance in the tank is higher. But also more analog varactor units are connected to the tuning voltage, leaving fewer analog units that are digitally controlled

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TABLE I
M EASUREMENT S UMMARY
1479
Fig. 8. Selected set of coarse and fine VCO tuning curves.
Fig. 9. VCO tuning curves for different analog varactor size settings.
and hence less fine tuning curves. Eventually the whole frequency band can be continuously covered with the desired slope for the oscillator sensitivity.
The flexibility of the VCO gain is shown in Fig. 9. For a fixed coarse frequency setting, the number of analog varactor units is changed, giving different slopes of the frequency curves. The varactors that are not connected to the analog tuning voltage are biased at the power supply, hence all curves overlap at
V. Clearly visible in the graph is of course the limited linear range of the MOS varactors used in the design. In the PLL the
VCO settings are controlled such that it is only used in the most linear range of the tuning voltage, between 0.4 and 0.8 V, where is almost constant.
These measurements show that the VCO achieves a continuous coverage over the whole frequency range, with a fully controllable , resulting in a stable and optimal PLL design for the whole tuning voltage range used.
Fig. 10 shows the measured free running phase noise of the
VCO at 3, 4, and 5 GHz for offset frequencies ranging from
100 kHz to 10 MHz. The 1/f noise corner remains below 200 kHz for all frequency settings. Phase noise measurements are summarized in Table I. The phase noise at lower frequencies is better than the results at higher frequencies, but this 4 dB difference can be perfectly explained by the difference in
[17], indicating indeed that the design is still limited by the limited of the inductor and that the use of the switched active core allows to keep the current consumption optimal over the whole frequency range.
To evaluate the performance of the VCO, we use the classical figure-of-merit (FOM) definition.
FOM mW
(6)
The measured VCO FOM ranges from 179 dB at lower frequencies to an excellent 185 dB at the upper limit of the frequency range. So although the basic phase noise is worse at higher frequencies, the obtained figure of merit is better, due to the fact that the power consumption has been drastically decreased in that case.
A figure of merit that allows making a more fair comparison between narrowband and wideband VCOs is the power-frequency-tuning normalized formula defined in [20] that includes the tuning range:
PFTN (7)
Fig. 10. Measured phase noise of the free running VCO and the closed-loop
PLL.
As indicated in Table I, an excellent value ranging from 2 to
3 dB is obtained.

1480 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 7, JULY 2007
Closed-loop phase noise measurements of the complete PLL are also shown in Fig. 10. The frequency is set at 4 GHz. The integrated phase noise between 0 and 10 MHz offset is 36 dBc for this setting.
VIII. C ONCLUSION
In this paper two circuit-level innovations that solve the two main problems in wideband LC -VCO designs have been presented. As the equivalent parallel resistance of the tank varies widely over the large tuning range, obviously the oscillator’s bias current must be reduced at higher frequencies to avoid a waste of power consumption and inferior phase noise behavior. The design presented here takes this one step further by employing a switched active core topology that adjusts the sizes of the negative resistance transistors to together with the bias current.
This technique eliminates a lot of parasitics in the oscillator’s tank, resulting in a better phase noise performance. Moreover, it allows the active core units to be used simultaneously as a switched varactor, allowing to obtain a very large tuning range.
Secondly, the VCO gain is controlled by changing the analog varactor size. This avoids instability in the PLL loop and enables an optimized PLL phase noise performance in the whole frequency range.
Measurements show that the proposed solutions allow the
VCO to oscillate over the extreme range of 3.1 to 5.2 GHz.
Over this band it shows a constant behavior, and optimized phase noise performance for every frequency. The phase noise is always lower than 114 dBc/Hz at 1 MHz offset. The power consumption scales with the frequency and varies between
3.2 mW at 5.2 GHz and 9.2 mW at 3.1 GHz. The VCO gain is fully controllable over the whole frequency band.
A CKNOWLEDGMENT
The authors would like to thank Prof. P. Andreani, TU Denmark, for his very insightful discussions on oscillator phase noise theory.
R EFERENCES
[1] J. Craninckx et al.
, “A fully reconfigurable software-defined radio transceiver in 0.13m CMOS,” in IEEE Int. Solid-State Circuits
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Dries Hauspie received the M.Sc. degree in electronics from KHBO, Oostende, Belgium, in 1999, and the M.Sc. degree in electronic system design from Leeds Metropolitan University, U.K., in 2001.
In 1999 he joined IMEC, Leuven, Belgium, as an
Analog/RF Research Engineer. His main research topics were low-noise amplifiers and voltage-controlled oscillators. Since 2006, he has been designing sensor interfaces for Melexis Semiconductors,
Belgium.
Eun-Chul Park received the M.S. and Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon,
Korea, in 1998 and 2003, respectively, where he was working on MEMS and Microsystems for RF system integration. Since 2003, he has been with Samsung
Advanced Institute of Technology working on highclude RF passives, VCO/PLLs, and LO generators.
Dr. Park was a Silver Medal winner of the Human
Tech. Prize awarded by Samsung Electronics in 2002 and at Samsung Tech.
Conference in 2006.
performance multi-GHz Wireless Personal Area Network (WPAN) applications. His research interests in-
Jan Craninckx (S’93–M’98) received the M.S. and
Ph.D. degrees in microelectronics from the ESAT-
MICAS Laboratories of the Katholieke Universiteit
Leuven, Belgium, in 1992 and 1997, respectively.
His Ph.D. work was on the design of low-phase noise CMOS integrated VCOs and synthesizers.
From 1997 until 2002, he worked with Alcatel
Microelectronics (now part of STMicroelectronics) as a Senior RF Engineer on the integration of RF transceivers for GSM, DECT, Bluetooth, and WLAN.
Since 2002, he has been a Principal Scientist in the wireless research group in IMEC, Leuven, Belgium, where his research interests are in the design of RF transceivers for software-defined radio (SDR) systems.
Dr. Craninckx is a member of the Technical Program Committee for IEEE
ISSCC and ESSCIRC.