EECS 443:Digital Systems Design Lab
Introduction
Instructors:
Neiza Fatima Torrico Pando, neizaaf@ku.edu
Akshatha Rao, akshatharao@ku.edu
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Modeling Digital Systems
• We use VHDL to implement system models
• For this class you will use simulations to test the correctness of
models, then synthesize and implement in the FPGA.
• The design process will be:
– Modeling – Stating the design requirements.
– Simulation – Executing the code and analyzing the response of
the design with different inputs.
– Synthesis – Mapping VHDL design to the FPGA.
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LAB Tools
1) Xilinx ISE: Model and synthesize the Design.
2) Impact: Board programming tool
3) ModelSim: Simulate the design.
4) ChipScope Pro: Capture output and pass input data directly to the
FPGA.
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Schedule:
WEEK
PROJECT
Week 1-3
Introduction and Project 0
Week 4-7
Project 1
Week 8 &9
Project 2
Week 10&11
Project 3
Week 12&13
Project 4
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VHDL
Any program will have two building blocks:
• ENTITY: It gives the name of the entity, ports of the entity and information
related to the ports.
• ARCHITECTURE: It describes the functionality of the entity and contains
the statements that model the behavior of the entity. There can be many
architectures related to one entity and there are different architectures
namely behavioral, structural, data flow and mixed.
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Entity Declaration
Say we want to design a 4-bit register, with enable and clock. We could do this 2
different ways:
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Design 1:
entity reg4 is
port(d0,d1,d2,d3,en,clk: in std_logic;
q0,q1,q2,q3 : out std_logic);
end entity reg4;
Design 2:
entity reg4 is
port(d : in std_logic_vector(3 downto 0);
en, clk : in std_logic;
q : out std_logic_vector(3 downto 0));
end entity reg4;
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Behavioral Architecture for Design 1
architecture beh of reg4 is
begin
update: process (d0,d1,d2,d3,en,clk) is
begin
-- if register is enabled, and rising-edge clock, update outputs
if en=‘1’ and clk=‘1’ and clk’event then
q0<=d0;
q1<=d1;
q2<=d2;
q3<=d3;
end if;
end process update;
end architecture beh;
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Notes on Behavioral Architectures
• Signals – wires; concurrent assignment
q0<=d0; -- these happen at the same time
q1<=d1; -(<= is also relational operator)
• Variables – State; sequential assignment
var1:=d0; -- these happen sequentially
var2:=var1 or ‘1’; -- there is state (memory) associated with -- the variables
• Internal signals are declared at top of architecture
• Internal variables are declared at top of process
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Structural Architectures
• Think of this as building an architecture using existing building-blocks, and connecting
the signals. We could make our 4-bit register out of 4 flip-flops:
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Structural Architecture implementation
Say we have already implemented the entity d_latch with architecture beh (with input
bits d,clk; output bit q)
d_latch entity declaration:
entity d_latch is
port (d,clk : in std_logic;
q : out std_logic);
end entity d_latch;
We also have the entitiy and2 (an and gate), with architecture beh.
We will “and” the clock with enable to send to the clk input of each gate (note: it is
not an ideal design to send your clock through logic gates).
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architecture struct of reg4 is
signal internal_clk : std_logic; -- Note: no direction(in/out) for internal signals
begin
bit0: entity work.d_latch(beh)
port map(d0,int_clk,q0);
bit1: entity work.d_latch(beh))
port map(d1,int_clk,q1)
bit2: entity work.d_latch(beh))
port map(d2,int_clk,q2)
bit3: entity work.d_latch(beh))
port map(d3,int_clk,q3)
clock: entity work.and2
port map(clk,en,int_clk);
end struct;
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Notes on Structural Architectures
• There should be NO processes
• The port maps tell you what signals in your structural architecture gets mapped to the
signals in the entities. You may be mapping port signals or internal signals. Make sure
you place them in the correct order. Let’s look at the latch entity compared to the first
instantiations of a latch in the architecture:
entity d_latch is
port (d,clk : in std_logic;
q : out std_logic);
end entity d_latch;
• d_latch instantiation:
bit0: entity work.d_latch(beh)
port map(d0,int_clk,q0);
So, here we are saying d0 goes to the input d, int_clk goes to the input clk, and q0 goes
to the ouput q.
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Data Flow and Mixed
• Data flow is a set of concurrent assignment statements.
• As the statements are concurrent, the order of statements assignment does not
affect the design.
• Delay can introduces in Data Flow modeling.
• A mixed will use a combination of all the three architectures.
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Test Benches
• Test benches help determine the correctness of a design.
• The steps of a testbench are:
• Instantiate the component(s) to be tested
• Drive the components’ signals
• Wait
• Look at the waveforms generated by the testbench to determine if the design is
correct (note: some problems might be with the testbench, and not the original
design)
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Example Testbench
entity tb is -- Note: there are no signal ports
end entity tb;
architecture test_reg4 of tb is
-- all port signals from component under test are now internal signals
signal d0,d1,d2,d3,en,clk,q0,q1,q2,q3: std_logic;
begin
-- instantiate component(s) under test
-- (dut stands for device under test - name doesn’t matter)
dut: entity work.reg4(beh) -- this means pick the beh architecture to test
port map(d0,d1,d2,d3,en,clk,q0,q1,q2,q3);
drive: process is
begin
d0<='1'; d1<='1'; d2<='1'; d3<='1'; wait for 20 ns; -- nothing changes, because en!=‘1’
en <= '1';
d0<='0'; d1<='1'; d2<='0'; d3<='1'; wait for 20 ns; -- output should change now
d0<='1'; d1<='0'; d2<='1'; d3<='0'; wait for 20 ns;
wait; -- This wait is very important. This is what will stop your simulation.
-- It should be at the end of every testbench process
end process drive;
clock: process is
begin
for i in 0 to 10 loop
clk <= '0'; wait for 5 ns;
clk <= '1'; wait for 5 ns;
end loop;
wait;
end process clock;
end test_reg4;
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Simulation of the Testbench
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Chip Scope Pro System
• This system allows for easy verification and debugging of the circuit
designed.
• It divides the problem into basic parts, it enables a very fast iterative
process of prediction and verification.
• There are certain Chip scope cores which help in debugging and these
cores have to be added to your design.
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Chip Scope Cores
• ICON (Integrated Controller): It provides communication
between the host PC and chipscope modules in the design.
• VIO (Virtual Input/Output): It can monitor and drive signals
in your design in real time.
• ILA (Integrated Logic Analyzer): It allows you to view and
trigger on signals in your design.
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Simulation vs Chipscope
• Running a simulation in Modelsim involves compiling your verilog modules and running
the testbench. All of this takes place on your PC – there is no actual hardware created in
the process.
• Chipscope modules are extremely useful because they allow you to view and manipulate
signals directly from hardware during run-time.
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