Bunch-by-Bunch
Bunch-by-Bunch Front End
Processing Units for Combating
Coupled Bunch Instabilities
Libera Bunch-by-Bunch and Libera
Bunch-by-Bunch Front End
enable closure of transverse and
longitudinal feedback loop. The system
successfully damps coupled bunch
instabilities.
Role in the Accelerator
Beam instabilities are usually caused by cavity high order modes, resistive wall impedance, interactions of the beam with other objects and ion instabilities. Digital
processing unit Libera Bunch-by-Bunch coupled with Libera Bunch-by-Bunch Front
End processes signals from hybrid and applies corrections to the amplifiers and
kickers. Properly processed signals enable successful closure of the feedback loop
and improve the accelerator performance by suppressing the coupled bunch instabilities.
Many instruments. Many people.
Working together.
Stability means knowing your machine
has innovative solutions. For users, stability means a machine achieving its full po-
BPMs
Kicker
tential, enabling them to do more science.
For us, stability means synchronized,
Hybrids
connected, dynamic state-of-the-art instrumentation, working together as one
system.
Because we know that the machine is
Libera
Bunch-byBunch
Front End
Libera
Bunch-byBunch
Modulator
(Longitudinal
FB)
Amplifier
more than just the sum of its parts.
Public Network
(Lab LAN)
Accelerator Control System
Bunch-by-Bunch Feedback System
Bunch-by-Bunch
Libera Bunch-by-Bunch is a digital
processing unit for combating coupled
bunch instabilities.
How Does It Work?
Libera Bunch-by-Bunch samples data at sampling rate equal to RF frequency of the
machine by using fast 12 bit ADC. Samples are divided per bunch. Each bunch is
filtered with 16 tap FIR filter. Additional processing, like gain, delay or phase shifting,
can be applied. Due to restrictions on the speed of FPGA devices, processing is
divided in 4 chains, where each chain processes one quarter of all bunches.
Processed samples are converted to analog domain by usage of 14-bit 500 MHz
digital to analog converter (DAC).
Performance
Specifications
Benefits
All-in-one standalone unit
• standard 1U factor
Digital signal processing, data sampling and data storage at 500 MHz rate
• bunch sampling and processing without decimation
Built on proven technology
• platform architecture and reliability of Libera Bunch-by-Bunch proved at several
accelerators around the world
• experience and support from the Libera community
Parameter
Value
External reference clock
fRF
ADC granularity
12 bit at fRF (500 MHz)
Maximum amplitude per input
2.2 Vpp
FPGA size and speed grade
XC2VP50FG1152-6
Memory size
DDR2RAM 128 Msamples
DAC granularity
14 bit at fRF
Input analog bandwidth
50 kHz-600 MHz
Output analog bandwidth
Depends on fRF
Analog output amplitude
1Vpp (4dBm)
Processing core parameters:
• 16-tap FIR filtering per bunch
• settable delay, from 0ns to
revolution period, in steps of 2 ns
• precision phase setting
• signal gain
• numerically controlled oscillator
Data Paths
ADC
inputs
12 bit @ fRF
selectable
dataflow
Out-of-the-box ready for closing the feedback loop
• all features required for successfull closure of the loop are embedded
in the DSP core
Digital signal
processing
History
buffer
towards:
off-line analasys
4x16 bit @ fRF /4
Easy to integrate in the control system
• well documented and maintained high-level software library (CSPI API)
Data on Demand
Bunch purity
• features needed for bunch cleaning based on numerically controlled oscillator,
selectable per bunch
FPGA Development Kit
• further processing core enrichment
• FPGA Development Kit (FDK) in-house developed and supported
by our team of engineers
Caontinuous Data Flow
14 bit @ fRF
Fast DAC
towards:
amplifier modulator
High-level Software
Architecture
With regards to the hardware architecture that consists of single board computer (SBC) and digital board with Xilinx
FPGA device, software architecture is
composed of CSPI API (running on SBC)
and FPGA software. CSPI API is a highlevel C interface which allows users to
implement a range of applications for the
Libera family. It supports remote access
and provides:
Hardware Interfaces
2
1
3
4
•
•
•
•
8
5
6
RS485 connectors 1 and 2 intended for user de-
10/100 Base-T Ethernet ports used for communication and integration with accelerator con-
Back panel
5
110/230 V AC mains power supply, 50-60 Hz
6
Fast signal interfaces:
•
•
Machine Clock. Sampling clock input.
trol systems. Control and measurement data
are exchanged at lower rates. Port 1 JTAG chain
SFP slots that can be used for fast serial com-
ON/OFF switch
FPGA development kit
Arm. When set, the Libera Bunch-by-Bunch is
Integration
into Control
System
Integration into control system can be
done using the generic server:
Trigger. When set, the measurements are buff-
•
ered and available for analysis.
•
•
munication.
4
FPGA
armed and is ready to receive a trigger.
•
acces. Ports 2 for future use. Port 3 standard.
3
CSPI API
9
fined communication purposes.
2
FPGA software can be additionally developed to meet specific users’ needs.
The in-house developed FDK can be provided on request (free of charge) and
allows users to adapt FPGA software of
Libera Bunch-by-Bunch for their specific
applications.
7
Front panel
1
configuration
data streams
health monitoring
event monitoring
The CSPI API is provided to users with
GNU GPL license and source code.
Analog out. Analog output of fast DAC.
Custom out. Optoisolated open collector out-
•
all necessary source code available
from Instrumentation Technologies
easy implementation based on the
“libera utility” example
put.
7
PMC slot. Standard PMC boards supported. Due
Accelerator Control System
to direct FPGA connection, the interface can be
PCI - or user - defined.
8
RF input
9
JTAG connector
Generic
Server
User
Program
ethernet
Generic Server
LIBERA
BUNCH-BY-BUNCH
HARDWARE
Bunch-by-Bunch
Front End
Graphical User
Interface
Libera Bunch‑by‑Bunch Front End is
a signal pre‑processing module of the
bunch‑by‑bunch feedback system.
The core application is accompanied
with a Matlab GUI with an additional
window for data acquisition.
GUI enables users to set the following
parameters:
•
•
•
•
•
•
filtering coefficients
phase shifting
delay of the processed signal
numerically-controlled oscillator
parameters
general gain and gain per bunch
digital to analog converter operating
mode
Main window
Benefits
•
•
•
•
•
•
one 1U unit for pre-processing of signals for all feedback loops
simple for installation and use
excellent channel isolation
high local oscillator input level tolerance
high dynamic range
low noise
Data acquisition
How Does It
Work?
Filter coefficients
setting window for
one chain
Libera Bunch-by-Bunch Front End demodulates phase or amplitude of the wideband
signal received from hybrid. It provides processing of two signals for transverse and one
for longitudinal feedback. Its outputs can be connected directly to the Libera Bunch-byBunch processing unit.
Performance
•
•
•
•
•
independent phase and amplitude adjustment for each processing channel
Ethernet interface for integration in the control system
double output for all channels that allows simultaneous signal observation
DC coupled output: 0-250 MHz
remote control via Ethernet, RS232 & USB
Hardware Interfaces
1
5
6
2
3
4
10
11
7
8
9
12
References
Libera Bunch-by-Bunch:
Australian Synchrotron (Australia)
ALBA (Spain)
ANKA (Germany)
Back panel
Front panel
1
7
Fan
time review of the signal.
8
Power supply
2
RS232 connector for serial connection
9
Reference clock outputs. The input machine
3
USB port
Control outputs. These outputs, labeled IT, IL,
Y and X, respectively, are used for parallel real-
CLS (Canada)
ESRF (France)
NSRRC (Taiwan)
LNLS (Brazil)
Diamond Light Source (United Kingdom)
clock can be phase shifted by the user and directed to these outputs. They can be connected directly to Libera Bunch-by-Bunch units.
4
Ethernet port: for future use
5
LCD
6
Libera Bunch-by-Bunch Front End:
Australian Synchrotron (Australia)
10
Reference clock input
11
RF inputs. Machine clock, X, Y and I signals,
respectively, should be connected to these in-
Keys and rotary knob
puts.
12
Outputs. Demodulated signals X, Y, IL and IT,
respectively, are directed to these outputs.
They can be connected directly to Libera
Bunch-by-Bunch units.
CLS (Canada)
NSRRC (Taiwan)
LNLS (Brazil)
Related Products in the
Accelerator System
Hadron
Accelerators
6
3rd Generation Light Sources
(Synchrotrons)
7
8
9
4
3
1
5
7
7
8
8
9
2
4th Generation Light Sources
(FELs and ERLs)
10
4
k
Libera Bunch-by-Bunch
Digital processing unit for combating
coupled bunch instabilities
5
Libera Bunch-By-Bunch Front End
RF signal processing for Libera
Bunch-by-Bunch
Solution
Building Block
Bunch-by-Bunch feedback
Libera Bunch-by-Bunch +
+
See the cover spread for
the whole product range
Libera Bunch-by-Bunch Front End
More at www.i-tech.si
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