APPLICATION NOTE
ATA6870 Level Shifted SPI
ATAN0048
Overview
As shown in Figure 1, standard implementation of the Atmel® ATA6870 battery management system utilizes a common ground reference for both the microcontroller and the
bottom-most ATA6870 device. In this configuration, there is no voltage offset between the
microcontroller and the Atmel ATA6870 I/O pins. Normal communication occurs at the regulated VDDHVM (VMCU) output voltage level.
Figure 1.
Standard Atmel ATA6870 Configuration (Common GND)
VBMS
+
+
+
+
-
Atmel
ATA6870
Vreg
PD_N
+
-
CLK
+
-
SPI
MCU
9272B-AUTO-04/15
For some applications, a common ground is not possible. The ground reference for the Atmel ATA6870 (GNDBMS) is set at a
voltage level higher than the microcontroller ground (GNDMCU). In this instance, the supply voltage to the microcontroller is at
the same voltage potential as the ground for the Atmel ATA6870, VMCU = GNDBMS. For SPI communication to occur, the SPI
and system clock signals must overcome the voltage/GND offset between devices. This is accomplished by level shifting the
SPI and system clock lines as shown in Figure 2.
Figure 2.
Atmel ATA6870 GND Offset Configuration
VBMS
+
+
+
-
Atmel
ATA6870
+
+
-
VBAT
+
-
Level
Shifter
GNDBMS
VMCU
+
--
SPI
MCU
CLK
PD_N
GNDMCU
2
ATAN0048 [APPLICATION NOTE]
9272B–AUTO–04/15
1.
Level Shifted Atmel ATA6870
Figure 1-1 shows the reference circuit for the level-shifted Atmel® ATA6870 SPI. This reference circuit was implemented
using the Atmel ATA6870-DK application kit. The kit consists of two application boards: the AVR® host controller and the
Atmel ATA6870-DK battery management board. Since the AVR host controller and the battery management board are
referenced to different ground potentials (GND_AVR and GND_BMS), the SPI and system clock lines must be level-shifted
between the two boards for communication to occur.
Figure 1-1. Atmel ATA6870-DK Level-shifted SPI Implementation
48V Battery Stack (18 cells)
ATA6870-DK
VCC
R1
10kΩ
CLK_OUT
12V SUPPLY
SCK
MOSI_OUT
VCC
MOSI
CS_N_OUT
PD_N_OPTO_HI
R4
R3
10kΩ
Q1
PN2369A
CLK (PB7)
10kΩ
CS_N
VDD_HVM
VDD_HVM
R5
15kΩ
AVDD
R6
4.7kΩ
R7
10kΩ
Q3
PN2369A
10kΩ
R9
15kΩ
GND_MCU
R13
MOSI
10kΩ
Q2
ZVP4105A
R18
CS_N
10kΩ
R11
4.7kΩ
R10
4.7kΩ
Q5
PN2369A
GND_MCU
MISO
Q4
ZVP4105A
R12
10kΩ
R15
15kΩ
IRQ
R14
1.5kΩ
GND_MCU
Q6
PN2369A
R16
4.7kΩ
R17
1.5kΩ
GND_MCU
GND_BMS
R8
SCK
MFIRST
PD_N_OPTO_LO
V_MCU
CLK
SCK_OUT
R2
15kΩ
AVR Board
V_BMS
PD_N_OPTO_HI
GND_BMS
GND_MCU
GND_MCU
MISO
IRQ
MISO_IN
IRQ_IN
GND_AVR
1.1
Level-shifted Inputs (From the MCU to the ATA6870)
Level shifting from the microcontroller to the Atmel® ATA6870 is accomplished through the use of the circuit shown in
Figure 1-2 on page 4. All Atmel ATA6870 input SPI signals (SCK, MOSI, CS_N) and the system reference clock (used by the
ADC) must use this circuit. The level shifter utilizes a high-speed switching NPN transistor and voltage divider to up-convert
the low-level microcontroller output voltage to the regulated, pulled-up Atmel ATA6870 voltage, VDDHVM (3.3V + VMCU).
ATAN0048 [APPLICATION NOTE]
9272B–AUTO–04/15
3
Figure 1-2. Input Level Shifter
VDD_HVM
R1
10kΩ
OUT
R2
15kΩ
IN
R3
Q1
PN2369A
10kΩ
GND_MCU
Note:
1.1.1
Resistor divider values are dependent upon the voltage offset (V_MCU) between the microcontroller ground
(GND_MCU) and the Atmel ATA6870 ground (GND_BMS). The voltage divider in this instance has been optimized for the reference application where V_MCU = 12V.
NPN Transistor Requirements
Due to the high-speed switching characteristic (500kHz) of the Atmel ATA6870 system reference clock, the NPN transistor
must have switching characteristics similar to the PN2369A device used in the reference application. The key parameters of
interest are the turn-on time, ton, and the turn-off time, toff. To ensure proper switching, the ton and toff must be less than 12ns
and 18ns respectively. Please refer to the device datasheet for more detailed information.
1.2
Level-shifted Outputs (From the Atmel ATA6870 to the MCU)
Level shifting from the Atmel ATA6870 to the microcontroller is accomplished by the circuit shown in Figure 1-3. All Atmel
ATA6870 output SPI signals (MISO and IRQ) must use this circuit. The level shifter utilizes a switching PMOS transistor and
a voltage divider to down-convert the Atmel ATA6870-DK output signal to the input voltage required by the microcontroller.
Figure 1-3. Output Level Shifter
VDD_HVM
R4
4.7kΩ
Q4
ZVP4105A
IN
R5
4.7kΩ
OUT
R6
1.5kΩ
GND_MCU
Note:
4
Resistor divider values are dependent upon the voltage offset (V_MCU) between the microcontroller ground
(GND_MCU) and the Atmel ATA6870 ground (GND_BMS). The voltage divider in this instance has been optimized for the reference application where V_MCU = 12V.
ATAN0048 [APPLICATION NOTE]
9272B–AUTO–04/15
1.2.1
PMOS Transistor Requirements
The PMOS device should have specifications similar to the ZVP4105A used in the reference application circuit.
1.3
Atmel ATA6870-DK Configuration
In addition to the level shifters, the following modifications must be made to the Atmel® ATA6870-DK evaluation board:
1. Remove the J27 (VDD_PULL) jumper
a.
2.
Remove the J31 (PD_N_OPTO_GND) jumper and connect PIN 2 of J31 to MCU_GND
a.
2.
References the optocoupler GND to MCU GND
Connect the J14 (POW_ENA) jumper to ON
a.
1.4
Disconnects the MCU supply from the ATA6870 regulator output
Enables the power regulator
Level-shifted Atmel ATA6870-DK Firmware
Adding level shifters between the microcontroller and the Atmel ATA6870 creates an inversion of the SPI and system clock
lines. As such, the Atmel ATA6870-DK firmware must be updated to handle these inverted signals. The new SPI signal
polarity is as follows:
1. Clock: high
2.
MOSI: high
3.
MISO: high
4.
CS_N: low
5.
IRQ: low
Figure 1-4 shows the new signal polarity at the microcontroller side of the level shifters. 1) Yellow, SCK, 2) blue, MOSI
3) magenta, MISO, and 4) green, CS_N.
Figure 1-4. Inverted SPI Polarity
The inverted SPI firmware, “ATA6870-DK_Inverted_SPI.hex,” for the application kit can be downloaded from the Atmel Web
site. The AVR host controller board must be reprogrammed with this firmware.
Note:
Please refer to your specific Atmel AVR programmer for more detailed instructions on how to program your
AVR microcontroller.
ATAN0048 [APPLICATION NOTE]
9272B–AUTO–04/15
5
2.
Appendix
2.1
Standard Atmel ATA6870-DK SPI Polarity
1.
Yellow, SCK
2.
Blue, MOSI
3.
Magenta, MISO
4.
Green, CS_N
Figure 2-1. SPI Signal Polarity (Normal Operation)
2.2
Inverted System Clock
1.
Yellow, system clock level shifter input
2.
Blue, system clock level shifter output (10V signal offset)
Figure 2-2. 500kHz System Reference Clock Level Shifter In/Out
6
ATAN0048 [APPLICATION NOTE]
9272B–AUTO–04/15
2.2.1
Inverted SPI Signals
2.2.1.1 SCK
1.
Yellow, level shifter input
2.
Blue, level shifter output (10V signal offset)
Figure 2-3. SCK Level Shifter In/Out
2.2.1.2 MOSI
1.
Yellow, level shifter input
2.
Blue, level shifter output (10V signal offset)
Figure 2-4. MOSI Level Shifter In/Out
ATAN0048 [APPLICATION NOTE]
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7
2.2.1.3 MISO
1.
Blue, level shifter input (10V signal offset)
2.
Yellow, level shifter output
Figure 2-5. MISO Level Shifter In/Out
2.2.1.4 CS_N
1.
Yellow, level shifter input
2.
Blue, level shifter output (10V signal offset)
Figure 2-6. CS_N Level Shifter In/Out
8
ATAN0048 [APPLICATION NOTE]
9272B–AUTO–04/15
3.
Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
History
9272B-AUTO-04/15
 Put document in the latest template
ATAN0048 [APPLICATION NOTE]
9272B–AUTO–04/15
9
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