THE DESIGN AND IMPLEMENTATION OF
LOW-POWER CMOS RADIO RECEIVERS
A DISSERTATION
SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING
AND THE COMMITTEE ON GRADUATE STUDIES
OF STANFORD UNIVERSITY
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
Derek K. Shaeer
December 1998
c Copyright 1999 by Derek K. Shaeer
All Rights Reserved
ii
Abstract
A
S CMOS technologies continue to enjoy the benets of aggressive scaling, they
become increasingly attractive for use in wireless receivers. Peak device fT 's
on the order of 15GHz are available with 0.5m CMOS devices, making possible
CMOS implementations of radio receivers in the 1-2GHz frequency range. One
wireless system in this range that is particularly amenable to integration is a Global
Positioning System (GPS), whose signals are at 1.57542GHz.
This dissertation explores architectural and design techniques for CMOS wireless
receivers through the vehicle of the GPS system. This system comprises 24 satellites in low earth orbit that continuously broadcast their position and local time.
Through satellite range measurements, a receiver can determine its absolute position
and time anywhere on Earth, as long as four satellites are within view. Portable,
consumer GPS applications require receivers that are compact, cheap and low-power.
Examples of such applications include automotive or maritime navigation, intelligent
hand-o algorithms in cellular telephony, and cellular emergency (911) services, to
name a few.
To enable a cheap, low-power CMOS GPS solution, this work develops a receiver
architecture that lends itself to complete integration. To implement this architecture,
two major foci are the design of low-noise ampliers (LNAs) and power-ecient
active lters in CMOS technologies.
Theoretical investigations of the LNA problem illustrate important deciencies
of present-day CMOS models that frustrate the design task. Methods for circumventing those deciencies are presented, leading ultimately to a power-constrained
optimization of LNA noise performance. This improved theoretical basis enables
iii
the realization of a 2.4dB noise gure, dierential LNA with only 12mW power
consumption in a 0.5m CMOS technology.
Another focus is on the power-ecient implementation of wide dynamic range
active lters. In such lters, the design of the transconductor element is critical, and
techniques for evaluating transconductor architectures are presented. An application
of these ideas to the GPS receiver problem results in a 10mW, 60dB peak spuriousfree dynamic range (SFDR) active lter with 3.5MHz bandwidth.
These advances enable the realization of a 115mW CMOS GPS receiver that
includes the complete RF and analog signal path, frequency synthesizer and A/D
converters. The receiver achieves a level of performance that compares favorably
with existing commercial solutions in more expensive bipolar and BiCMOS technologies, delivering an overall noise gure of 2.8dB and a peak SFDR of 56dB while
occupying only 11.2mm2 in a 0.5m CMOS technology.
iv
Acknowledgments
I
WOULD like to thank the many friends and colleagues who have supported and
challenged me during my tenure at Stanford University. First and foremost, I
wish to acknowledge my adviser and friend Professor Thomas H. Lee, who gave
me the opportunity to join him at the very inception of his work at Stanford. As
an educator, Tom has been an exceptional role model with his insistence on high
academic standards, his great accessibility to students, his incomparable work ethic,
and his natural charisma. It can be said that no one in his research group works
harder, or laughs harder, than Tom. I am particularly grateful for the advice, both
technical and personal, that he has given me over the years, and it is my sincere
hope that this dissertation will adequately reect the mentorship that I have been
so fortunate to receive under his tutelage.
I would also like to thank my associate adviser, Professor Bruce Wooley, who has
been a welcome source of sage advice. In particular, I would like to thank him for
taking the time to serve on my oral exam committee and for reading and improving
my dissertation. I am also grateful for Professor Donald Cox, who served on my oral
exam and reading committees and whose thoughtful comments also improved the
nal manuscript of this work. I have beneted many times from his technical insight
and his years of experience in wireless technology, and I thank him for his time and
advice, given so generously. I also am indebted to Professor Patrick Hanrahan, who
agreed to chair my oral exam committee and took time out of his very busy schedule
to do so.
I am honored to call myself a member of the SMIrC research group, and I want
to thank Arvin Shahani, Dr. Ali Hajimiri, Dave Colleran, Hamid Rategh, Hirad
Samavati, Kevin Yu, Mar Hershenson, Sundararajan Mohan, Rafael Betancourt,
v
Ramin Farjad-Rad and Tamara Ahrens for their friendship. The SMIrC group has
been an incredibly stimulating and enjoyable group to work with, and I thank the
members for their excitement and their technical excellence. In particular, I thank
Arvin, Hamid, Hirad, Mar, and Mohan who worked so diligently on the GPS receiver
project (code named \Waldo") along with Dr. Patrick Yue, Min Xu and Dan Eddleman. I am exceedingly grateful for their eorts that helped the Waldo project to
nish on time, despite an aggressive schedule. Of these, I reserve special gratitude
for Arvin, who has been my constant friend and research partner throughout my
years at Stanford.
Within the Center for Integrated Systems, there exists a spirit of cooperation
that is unique and special. Accordingly, I would like to pay tribute to the many
members of the Wooley, Wong, Horowitz and Meng research groups, among whom I
count some of my closest friends and best professional colleagues. Along with those
that I have already thanked (including past and present members of CIS) are Joe
Ingino, Dr. Adrian Ong, Dr. Sha Rabii, Dr. Stefanos Sidiropoulos, Dwight Thompson, Katayoun Falakshahi, Jim Burnham, Sotirios Limotyrakis, Bendik Kleveland,
Alvin Loke, Dr. Ken Yang, Gu-Yeon Wei, Birdy Amrutur, Dan Weinlader, Won
Namgoong, Jeannie Ping-Lee, Greg Gorton, Syd Reader and Horng-Wen Lee. I
thank Professors Wooley, Wong, Horowitz and Meng for their roles in fostering the
spirit of cooperation that exists in CIS, making CIS a great place to work.
One person who contributes disproportionately to making CIS a wonderful place
is Ann Guerra. Her administrative competence, contagious enthusiasm and warm
sense of humor ease many of the trials of graduate student life, and I am grateful
to her for her assistance, often given under great time pressure, and for her positive
attitude. I am happy to add my thanks to those of the countless students that
have gone before me in acknowledging her central role in brightening their graduate
experiences.
In addition to Ann, there are many sta members within CIS who deserve my
thanks. These include Charlie Orgish and Joe Little who work diligently behind
the scenes to keep the computer systems running smoothly; Tony Souza and Mario
Vilanova who, among other things, manage CIS receiving and the supply room;
vi
and Carmen Miraor, Harrianne Mills and Maureen Rochford who ran the Stanford
SPIE program and gave me several opportunities to visit our industrial aliates. I
count the SPIE trips to our aliates among the most memorable experiences that I
have had at Stanford.
Outside of CIS, I would like to thank Al Jerng, Allen Lu and the laboratory of
Professor Leonid Kazovsky for their valuable assistance with my earliest low-noise
amplier work. In particular, the members of the Kazovsky laboratory were very
generous in allowing me to use their facilities at a time when the SMIrC group
had no laboratory of its own. I would also like to thank Brian Armstrong, Dwight
Thompson, Esin Terzioglu, Wayne Martin and Tien-Chun Yang for whipping me
into shape when I rst came to Stanford as we all studied for the qualifying exam
together.
In addition to those in the Stanford community, I want to thank several people outside Stanford who contributed directly to my work. In particular, I thank:
Norm Hendrickson of Vitesse for supplying high-frequency packages; Howard Swain
for his teaching and for rst alerting me to the issue of induced gate noise; Dan
Dobberpuhl of DEC for giving me the opportunity to do some experimental work
with DEC's 0.35m CMOS technology, and Mark Pierce, Dave Kruckmeyer and the
other members of the Palo Alto Design Center for helping me with simulation and
tapeout; Dr. Chris Hull of Rockwell Semiconductor Systems for partnering with me
for the GPS receiver work and attending to any problems that arose at Rockwell
during the course of the project, and Paramjit Singh of Rockwell for his invaluable
assistance with technology issues; Ernie McReynolds of Tektronix for helping me to
insert a much-needed induced gate noise model into the BSIM-III code and for his
general help on simulation issues; Chuck Saxe, Jack Hurt, Bob Woolhiser and Linley
Gumm of Tektronix for allowing me to continue doing integrated circuit work for
Tektronix while I was at Stanford and for contributing immeasurably to my technical education through many summers working at Tektronix; and Pauline Prather of
New Focus who bonded many chips for me, often on very short notice, and never
once complained about the extra work.
vii
Finally, I must reserve the most special thanks for my friends and family, who
have enriched my life in so many ways. I thank my undergraduate advisor, Dr. John
Choma, Jr. of USC for his mentorship and his encouragement to pursue graduate
work. I thank my many friends at Stanford and elsewhere for their support and
friendship. Among those that I have not already mentioned are Scott and Christina
Dudley, Robert and Debbie Jones, Steve Walther, Mark Hamilton, Annie Koo, and
Mike Swartwout. I am deeply indebted to my parents, Lynn and Carrie, who gave me
a strong home and always emphasized the importance of education to their children,
and to my younger brother Ian whom, despite the usual sibling rivalry, I now consider
to be one of my best friends. And, at last, my most tender and sincere thanks are
reserved for my wife, Debbie, who probably could not have counted the cost of being
wed to a graduate student before coming to Stanford, but who continues nonetheless
to give me her unconditional support and love.
I would like to dedicate this work to all of my teachers, and particularly to my
parents, who were the best teachers of them all.
viii
Contents
Abstract
Acknowledgments
List Of Tables
List Of Figures
1 Introduction
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Radio Receiver Architectures
2.1 The Radio Spectrum . . . . . . . . .
2.2 Classical Receiver Architectures . . .
2.2.1 Crystal Detectors . . . . . . .
2.2.2 Heterodyne . . . . . . . . . .
2.2.3 Regenerative Receiver . . . .
2.2.4 Superheterodyne . . . . . . .
2.2.5 Superregenerative Receiver . .
2.2.6 Autodyne and Homodyne . .
2.2.7 Single-Sideband Transmission
2.2.8 Hartley Modulator . . . . . .
2.2.9 Weaver Modulator . . . . . .
2.3 Summary . . . . . . . . . . . . . . .
3 Fundamentals of Radio Reception
3.1
3.2
3.3
3.4
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Noise in Radio Receivers . . . . . . . . . . . . .
Signal Distortion and Dynamic Range . . . . . .
Frequency Conversion and Frequency Planning .
Cascaded Systems . . . . . . . . . . . . . . . . .
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iii
v
xiii
xv
1
1
2
5
6
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11
12
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24
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27
27
31
33
39
3.5 Integrated Receivers . . . . . . . . . . . . . . . . .
3.5.1 Passive Components and the Filter Problem
3.5.2 Isolation and Substrate Noise . . . . . . . .
3.5.3 Power, Voltage and Current . . . . . . . . .
3.6 Review of Recent CMOS Receivers . . . . . . . . .
3.7 Summary . . . . . . . . . . . . . . . . . . . . . . .
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4 A Global Positioning System Receiver Architecture
4.1
4.2
4.3
4.4
The Global Positioning System . . . . .
Typical GPS Receiver Architectures . . .
Opportunities for a Low-IF Architecture
GPS Receiver Architecture . . . . . . . .
4.4.1 Image Noise Cancellation . . . . .
4.4.2 Receiver Gain Plan . . . . . . . .
4.5 Summary . . . . . . . . . . . . . . . . .
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5 Low-Noise Amplication in CMOS at Radio Frequencies
5.1 Recent LNA Research . . . . . . . . . . . . . . .
5.2 LNA Architectural Analysis . . . . . . . . . . . .
5.2.1 Standard MOS Noise Model . . . . . . . .
5.2.2 LNA Architecture . . . . . . . . . . . . . .
5.2.3 Extended MOS Noise Model . . . . . . . .
5.2.4 Extended LNA Noise Analysis . . . . . . .
5.3 LNA Design Considerations . . . . . . . . . . . .
5.3.1 A Second-Order MOSFET Model . . . . .
5.3.2 Noise Figure Optimization Techniques . .
5.3.2.1 Fixed Gm Optimization . . . . .
5.3.2.2 Fixed PD Optimization . . . . .
5.3.3 Comparison with the Classical Approach .
5.3.4 A Note on MOS Noise Simulation Models
5.3.5 Additional Design Considerations . . . . .
5.4 Summary . . . . . . . . . . . . . . . . . . . . . .
6 CMOS Mixers
6.1 Review of Mixer Architectures . . . . . . . .
6.2 The Double-Balanced CMOS Voltage Mixer
6.2.1 Basic Mixer Conversion Gain . . . .
6.2.2 LTV Conversion Gain Analysis . . .
6.2.3 Mixer Noise Figure . . . . . . . . . .
6.2.4 Mixer Linearity . . . . . . . . . . . .
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44
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6.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7 Power-Ecient Active Filters
7.1 Passive and Active Filter Techniques . . . . . . .
7.2 Dynamic Range of the Active Gm-C Filter . . . .
7.2.1 Noise Figure . . . . . . . . . . . . . . . . .
7.2.2 3rd-Order Intermodulation Distortion . . .
7.2.3 Optimizing Dynamic Range . . . . . . . .
7.3 Power-Ecient Transconductors . . . . . . . . . .
7.3.1 A Class-AB Transconductor . . . . . . . .
7.3.2 A Survey of Transconductor Architectures
7.3.3 Transconductor Implementation . . . . . .
7.4 Summary . . . . . . . . . . . . . . . . . . . . . .
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8 An Experimental CMOS Global Positioning System Receiver
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Low-Noise Amplier . . . . . . . . . . .
Voltage-Switching Mixer and LO Drivers
Intermediate Frequency Amplier . . . .
Active Filter . . . . . . . . . . . . . . . .
Limiting Amplier and Comparator . . .
Biasing Details . . . . . . . . . . . . . .
Experimental Results . . . . . . . . . . .
Summary . . . . . . . . . . . . . . . . .
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9 Conclusions
119
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173
9.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
9.2 Recommendations for Future Work . . . . . . . . . . . . . . . . . . . 175
Appendix A
Cross-correlation Properties of Limited Gaussian Noise Channels . . . . . . 177
A.1 Limited Gaussian Noise . . . . . . . . . . . . . . . . . . . . . . . . . 177
A.2 Cross-Correlation in the Weaver Receiver . . . . . . . . . . . . . . . . 180
Appendix B
Classical MOSFET Noise Analysis . . . . . . . . . . . . . . . . . . . . . . 185
Appendix C
Experimental CMOS Low-Noise Ampliers .
C.1 An Experimental Single-Ended LNA .
C.1.1 Implementation . . . . . . . . .
C.1.2 Experimental Results . . . . . .
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191
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C.2 An Experimental Dierential LNA . . . . . . . . . . . . . . . . . . . 200
C.2.1 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 201
C.2.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 203
Appendix D
Measurement Techniques . . . . . . . . .
D.1 LNA Noise Figure Measurements .
D.2 Pre-Limiter Receiver Measurements
D.3 Whole Receiver Verication . . . .
Bibliography
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207
207
210
213
217
xii
List Of Tables
3.1
4.1
5.1
6.1
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
C.1
C.2
CMOS Receiver Summary . . . . . . . . . . .
Receiver Gain Plan . . . . . . . . . . . . . . .
Summary of Recent LNA Results . . . . . . .
Gc for the four types of LO drive. . . . . . . .
LNA Elements . . . . . . . . . . . . . . . . . .
Mixer/LO Driver Elements . . . . . . . . . . .
IFA Elements . . . . . . . . . . . . . . . . . .
Filter Capacitors . . . . . . . . . . . . . . . .
Transconductor Elements . . . . . . . . . . . .
Transconductor CMFB Elements . . . . . . .
Replica Bias Elements . . . . . . . . . . . . .
Limiting Amplier Elements . . . . . . . . . .
Latch / Output Driver Elements . . . . . . . .
Bandgap Reference Elements . . . . . . . . . .
Spiral Inductors . . . . . . . . . . . . . . . . .
Comparison with Commercial GPS Receivers.
Measured GPS receiver performance. . . . . .
Single-ended LNA Performance Summary . .
Dierential LNA Performance Summary . . .
xiii
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51
61
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200
204
xiv
List Of Figures
2.1 The crystal detector. (a) Schematic. (b) System diagram. . . . . . . .
2.2 The crystal detector and audion amplier. (a) Schematic. (b) System
diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 The heterodyne receiver. (a) Schematic. (b) System diagram. . . . .
2.4 The regenerative audion receiver. (a) Schematic. (b) System diagram.
2.5 The superheterodyne receiver. (a) Schematic. (b) System diagram. .
2.6 The superregenerative receiver. (a) Schematic. (b) System diagram. .
2.7 The homodyne receiver of de Bellescize. (a) Schematic. (b) System
diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 The single-balanced modulator. (a) Schematic. (b) System diagram. .
2.9 The Hartley SSB modulator. (a) Schematic. (b) System diagram. . .
2.10 The Weaver SSB modulator. (a) Schematic. (b) System diagram. . .
3.1 Illustration of intermodulation behavior. . . . . . . . . . . . . . . . .
3.2 Various mixer topologies that fall into the nonlinear and time-varying
categories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 A simple receiver with image-reject lter and channel-select tler. . .
3.4 Illustration of the reciprocal mixing process. . . . . . . . . . . . . . .
3.5 The relative contribution of successive stages to noise and distortion.
3.6 Optimizing dynamic range. (a) Two ampliers with certain cross
dynamic ranges. (b) Illustration of the optimum gain to maximize
the dynamic range. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 A low-IF image-reject architecture using polyphase lters. . . . . . .
3.8 A low-IF image-reject architecture with a wide-band IF. . . . . . . .
3.9 A sub-sampling receiver with discrete-time ltering. . . . . . . . . . .
3.10 A direct-conversion receiver. . . . . . . . . . . . . . . . . . . . . . . .
8
10
11
13
15
17
19
21
23
25
32
35
37
39
41
43
48
49
50
51
4.1 The GPS L1 band signal spectrum. . . . . . . . . . . . . . . . . . . . 55
4.2 Typical GPS receiver architectures. . . . . . . . . . . . . . . . . . . . 56
xv
4.3 The GPS L1 band signal spectrum when downconverted to a 2-MHz
intermediate frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.4 Block diagram of the CMOS GPS receiver. . . . . . . . . . . . . . . . 59
5.1 Common LNA Architectures. (a) Resistive Termination. (b) 1=gm
Termination. (c) Shunt-Series Feedback. (d) Inductive Degeneration. 64
5.2 The standard CMOS noise model. . . . . . . . . . . . . . . . . . . . . 68
5.3 Common-source input stage. . . . . . . . . . . . . . . . . . . . . . . . 71
5.4 Equivalent circuit for input stage noise calculations. . . . . . . . . . . 72
5.5 Induced gate eects in MOS devices. . . . . . . . . . . . . . . . . . . 75
5.6 Revised gate circuit model including induced eects. (a) Standard
representation, as found in [1]. (b) The equivalent, but more intuitive,
Thevenin representation. . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.7 Revised small-signal model for LNA noise calculations. . . . . . . . . 79
5.8 Theoretical predictions of noise gure F for several power dissipations.
L = 0:44m, Rs = 50
, !0 = 10Grps,Vdd = 2:5V, = 1:3 [2], = 2:6,
jcj = 0:395 [1], sat = 1 105 m/s, and "sat = 4:7 106 V/m [3]. . . 89
5.9 Noise gure optimization experiment illustrating the signicance of
Qopt ;Gm and Qopt ;Pd . Note that the curves shown represent constantPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.10 Modied NMOS noise model that includes the eects of induced gate
noise and gate polysilicon resistance. . . . . . . . . . . . . . . . . . . 95
6.1 Commutating mixer architectures, illustrating the switching principle
employed in each. (a) Diode ring with center-tapped LO drive. (b)
Diode ring with transformer-coupled LO drive. (c) Gilbert mixer. . . 103
6.2 CMOS voltage mixer and LO driver. . . . . . . . . . . . . . . . . . . 104
6.3 Quadrature generation with the Miller capacitance. . . . . . . . . . . 105
6.4 Four LO signals investigated . . . . . . . . . . . . . . . . . . . . . . . 106
6.5 Mixer core. (a) Time-varying conductance model, and (b) Thevenin
equivalent circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.6 Mixing function and Thevenin conductance for the four cases . . . . . 108
6.7 Modied mixing functions for the four cases . . . . . . . . . . . . . . 112
6.8 Equivalent block diagram for core conversion gain . . . . . . . . . . . 113
6.9 AG0c vs. r for a break-before-make LO drive. . . . . . . . . . . . . . . 114
7.1 Generic structure of the \electric wave-lter", or ladder lter. . . . . 120
7.2 Four common types of lowpass lters. . . . . . . . . . . . . . . . . . . 121
7.3 A Sallen and Key lowpass lter. . . . . . . . . . . . . . . . . . . . . . 122
7.4 Integrators for the (a) MOSFET-C lter and (b) Gm-C lter. . . . . . 123
7.5 Block diagram of the on-chip Gm-C lter and its equivalent half-circuit.125
xvi
7.6 A simple gyrator and its equivalent circuit with noise sources. . . . . 126
7.7 Distortion models for a gyrator. (a) Full gyrator. (b) Equivalent circuit.129
7.8 Equivalent circuit presented by the lter network to the inductor (a)
at dc, and (b) at resonance. . . . . . . . . . . . . . . . . . . . . . . . 130
7.9 Illustration of the class-A Gm for linearity tradeo. . . . . . . . . . . 134
7.10 A class-AB transconductor. (a) Square-law prototype. (b) Linear
prototype. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.11 Mobility degradation modeled as series feedback. (a) Equivalent circuit. (b) System view. . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.12 Cancelling mobility degradation with positive feedback. (a) Modied
transconductance cell. (b) System view. . . . . . . . . . . . . . . . . 137
7.13 Two class-A transconductor architectures. (a) Standard dierential
pair with resistive degeneration. (b) MOSFET-degenerated dierential pair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.14 Figure of merit for a simple dierential pair with source degeneration. 139
7.15 Figure of merit for the MOSFET-degenerated dierential pair. . . . . 140
7.16 The mobility-compensated class-AB transconductor. . . . . . . . . . . 141
7.17 Figure of merit for the class-AB transconductor. . . . . . . . . . . . . 141
7.18 A linearized class-AB transconductor. . . . . . . . . . . . . . . . . . . 142
7.19 Normalized transconductance characteristic, with and without positive feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
The low-noise amplier. . . . . . . . . . . . . . . . . . . . . . . . . .
Mixer and quadrature LO driver. . . . . . . . . . . . . . . . . . . . .
Intermediate frequency amplier. . . . . . . . . . . . . . . . . . . . .
Simulated gain characteristic of the IFA. . . . . . . . . . . . . . . . .
Active Gm {C lter. The missing input termination resistor is supplied
by the output resistance of the preceding IFA stage. . . . . . . . . . .
Gyrator transconductor. . . . . . . . . . . . . . . . . . . . . . . . . .
Common-mode feedback circuit for the transconductor. . . . . . . . .
Replica biasing of the lter transconductor. . . . . . . . . . . . . . . .
Five-stage limiting amplier and output comparator. . . . . . . . . .
A single stage of the limiting amplier. . . . . . . . . . . . . . . . . .
The output latch and output driver. . . . . . . . . . . . . . . . . . . .
Bandgap reference circuit. . . . . . . . . . . . . . . . . . . . . . . . .
Die micrograph of the GPS receiver. . . . . . . . . . . . . . . . . . .
Measured LNA noise gure. . . . . . . . . . . . . . . . . . . . . . . .
Measured signal path frequency response. . . . . . . . . . . . . . . . .
Results of a two-tone IM3 test. . . . . . . . . . . . . . . . . . . . . .
Measured 1-dB blocking desensitization point. . . . . . . . . . . . . .
xvii
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160
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164
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167
168
168
8.18 FFT of the I channel output bit sequence. . . . . . . . . . . . . . . .
8.19 Cross-correlation at the receiver output. . . . . . . . . . . . . . . . .
A.1 The eect of a limiter on the cross-correlation or autocorrelation of a
Gaussian noise process. . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2 Simplied block diagram of the CMOS GPS receiver, including a coherent back-end demodulation to baseband. . . . . . . . . . . . . . .
B.1 Equivalent noise models for a MOSFET device with drain and gate
current noise. (a) Physical model. (b) Equivalent model with inputreferred sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.1 Complete schematic of the LNA, including o-chip elements. . . . . .
C.2 Die photo of the LNA. . . . . . . . . . . . . . . . . . . . . . . . . . .
C.3 Measured S21 of the LNA . . . . . . . . . . . . . . . . . . . . . . . .
C.4 Measured S11 of the LNA . . . . . . . . . . . . . . . . . . . . . . . .
C.5 Measured S12 of the LNA . . . . . . . . . . . . . . . . . . . . . . . .
C.6 Detailed LNA schematic showing parasitic reverse paths. . . . . . . .
C.7 Noise gure and forward gain of the LNA. . . . . . . . . . . . . . . .
C.8 Results of two-tone IP3 measurement. . . . . . . . . . . . . . . . . . .
C.9 Dierential LNA circuit diagram . . . . . . . . . . . . . . . . . . . . .
C.10 Single-ended version of the DC biasing technique . . . . . . . . . . .
C.11 Die photo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.12 Noise gure vs. device width for Rin = 100
and Rin = 40
. . . . .
C.13 LNA noise gure/S21 measurement . . . . . . . . . . . . . . . . . . .
D.1 Experimental setup for LNA noise gure measurements. . . . . . . . .
D.2 Experimental setup for receiver noise gure measurements. . . . . . .
D.3 Experimental setup for receiver IP3 measurements. . . . . . . . . . .
D.4 Experimental setup for receiver frequency response measurements. . .
D.5 Experimental setup for complete receiver measurements. . . . . . . .
xviii
169
170
181
181
186
193
194
195
195
196
197
198
199
201
202
203
205
206
208
210
212
213
214
Chapter 1
Introduction
W
IRELESS communications research has experienced a remarkable renaissance in the last decade. The advent of cellular telephony has driven much
of the recent research activity, but substantial eorts have also focused on other
wireless applications, such as cordless telephones and, more recently, the Global
Positioning System.
1.1 Motivation
The primary goal of this dissertation is to explore techniques for implementing wireless receivers in an inexpensive complementary metal-oxide-semiconductor (CMOS)
technology. Although the techniques developed apply somewhat generally across
many classes of receivers, the specic focus of this work is on the Global Positioning
System (GPS). Because GPS provides a convenient vehicle for examining CMOS
receivers, a brief overview of the GPS system and its implications for consumer
electronics is in order.
The GPS system comprises 24 satellites in low earth orbit that continuously
broadcast their position and local time [4]. Through satellite range measurements,
a receiver can determine its absolute position and time to within about 100m anywhere on Earth, as long as four satellites are within view. The deployment of this
satellite network was completed in 1994 and, as a result, consumer markets for GPS
1
2
Chapter 1: Introduction
navigation capabilities are beginning to blossom. Examples include automotive or
maritime navigation, intelligent hand-o algorithms in cellular telephony, and cellular emergency (911) services, to name a few.
Of particular interest in the context of this dissertation are embedded GPS applications where a GPS receiver is just one component of a larger system. Widespread
proliferation of embedded GPS capability will require receivers that are compact,
cheap and low-power. For such goals, the benets conveyed by integration are selfevident: minimization of the number of o-chip components (particularly the number of expensive passive lters), improved form factor, reduced cost and ease of
design.
For further cost reduction, it is interesting to consider implementation in a CMOS
technology. Due to the huge capital investment in CMOS, it is only natural to consider whether the technology's shortcomings can be mitigated, making it attractive
in an arena that historically has been dominated by more expensive silicon bipolar
and GaAs MESFET technologies.
Meeting the goal of receiver integration in an inferior technology requires innovation in architectures, circuits and device modeling. Collectively, the scope of these
problems is broad, but a successful approach will bring clear benets for consumer
electronics. And so, these considerations motivate the present research into highly
integrated CMOS GPS receivers that forms the subject of this dissertation.
1.2 Overview
The following chapters delve into the problems of radio receiver design in detail. The
ultimate goal is the design and implementation of a 115mW CMOS GPS receiver
in a 0.5-m CMOS process. The techniques developed along the way are, however,
broadly applicable to other wireless systems.
Chapter 2 begins with an overview of radio receiver architectures by presenting
fundamental concepts through the vehicle of historical examples. Then in Chapter 3,
the subjects of noise, distortion and frequency planning are presented, with special
attention paid to cascaded systems. In addition, a review of the current state of
1.2: Overview
3
the art in CMOS receiver research establishes a context for the present work. In
Chapter 4, the relevant technical details of the GPS system are presented along with
a brief survey of common GPS receiver architectures. Then, applying the concepts
developed in Chapter 2, we introduce a new architecture that takes advantage of
details of the GPS signal spectrum to achieve a high level of integration.
Chapter 5 tackles the subject of CMOS low-noise ampliers in great detail. This
includes a survey of recent work and the development of a power-constrained noise
gure optimization procedure for gaining the best performance for a stated power
budget. Proceeding down the receiver chain, Chapter 6 discusses frequency mixers
and focuses attention on the double-balanced CMOS voltage mixer that provides
high linearity, low noise gure and extremely low power consumption. Chapter
7 follows with an investigation of active lters. Because the active lter is a dynamic range bottleneck in many receivers, this chapter focuses on how to design
lter transconductor elements that maximize dynamic range with a given power
consumption. In particular, we develop a gure of merit that permits a comparison of various transconductors, leading ultimately to a very power-ecient lter
implementation.
To put these theoretical developments into practice, Chapter 8 presents the implementation of an experimental CMOS GPS receiver in a 0.5m process. The
experimental results demonstrate a high level of performance and integration that is
comparable to or better than existing implementations in more expensive technologies, thereby conrming the value of the techniques presented in earlier chapters.
Finally, Chapter 9 concludes with a summary and some suggestions for future work.
For readers who survive the rst eight chapters, several appendices present expanded treatment of certain subjects. Appendix A explores the topic of noise correlations in amplitude-limited gaussian noise channels. Appendix B presents a noise
gure analysis of the MOSFET device using the classical technique. Appendix C
presents some experimental results on two low-noise ampliers: a single-ended amplier and a dierential amplier. Finally, Appendix D describes the measurement
techniques used to gather the experimental data reported in Chapter 8.
4
Chapter 1: Introduction
Chapter 2
Radio Receiver Architectures
T
HE advent of wireless communications at the turn of the 20th century marked
the beginning of a technological era in which the nature of communications
would be radically altered. The ability to transmit messages through the air would
soon usher in radio and television broadcasting and wireless techniques would later
nd application in many of the mundane tasks of everyday life. Today, the widespread
use of wireless technology conveys many benets that are easily taken for granted.
From cellular phones to walkie-talkies; from broadcast television to garage door
openers; from aircraft radar to hand-held GPS navigation systems, radio technology
pervades modern life.
At the forefront of emerging radio applications lies modern research on the integrated radio receiver. The goal of miniaturization made possible by integrated
circuit technologies holds the promise of portable, cheap and robust radio systems,
as exemplied by the advent of cellular telephony in the mid-1980's. As miniaturization continues, embedded radio applications become possible where the features
of multiple wireless systems can be brought to bear on a particular problem. One
example is the use of a GPS receiver in a cellular telephone to permit the expedient
dispatch of emergency service personnel to the caller's exact location.
The design of integrated radio receivers entails a number of important considerations. To provide a background for the discussion of such matters, this chapter
5
6
Chapter 2: Radio Receiver Architectures
explores the important features of modern radio receivers by presenting them in the
context of their historical development.
2.1 The Radio Spectrum
The goal of any radio receiver is to extract and detect selectively a desired signal
from the electromagnetic spectrum. This \selectivity" in the presence of a plethora
of interfering signals and noise is the fundamental attribute that drives many of
the tradeos inherent in radio design. Radio receivers must often be able to detect
signal powers as small as a femtowatt while rejecting a multitude of other signals that
may be twelve orders of magnitude larger! Because the electromagnetic spectrum
is a scarce resource, interfering signals often lie very close to the desired one in
frequency, thereby exacerbating the task of rejecting the unwanted signals.
The scarcity of the spectrum has grown steadily more important over time. Consider the situation at the turn of the century: when Guglielmo Marconi rst succeeded in transmitting the letter \S" across the Atlantic Ocean on December 12th,
1901, there were virtually no radio transmitters in service, and thus the only interference to be contended with was atmospheric noise. The transmitter of choice was the
spark-gap, which was hardly a spectrally-ecient technique. On the receiving end, a
simple \coherer" { a glass tube lled with oxidized metallic lings { served to detect
the electromagnetic pulses generated by the spark [5]. This detection technique was
as unselective as the transmission technique was spectrally wasteful. A spectacular
demonstration of the unselective nature of this type of radio system occurred during
the 1901 America's Cup yacht race when several independent parties tried to broadcast up-to-the-minute race coverage to shore using spark-gap transmitters. Needless
to say, the transmitted information was lost in a cacophony of interference from the
various transmitters so that no one was able to receive intelligible signals [6].
We will use this failure of an early radio system as the starting point for a
history of radio receiver development. For as the number of permanent transmitting
stations grew exponentially, from a scant 100 stations in the U.S. in 1905 to over
1100 stations only ten years later [7], the scarcity of spectrum and the accompanying
2.2: Classical Receiver Architectures
7
drive to higher and higher frequencies (a drive that continues to this day) stimulated
the development of radio receiver architectures that were increasingly sensitive and
selective. With the advent of TV and radio broadcasting in the 1920s and 30s, the
demand for radio technology grew beyond the ranks of the military and the hobbyists
to the all-powerful consumer. The economic incentives for satisfying this demand
added fuel to the re, as evidenced by the rapid pace of technological progress, a
renewed interest in \short-wave" radio [8], and a marked increase in patent litigation
[7]. The technologies developed along the way in part to meet the increasing demands
of radio reception { such as the vacuum tube (or audion, as it was originally called),
the piezo-electric resonator, and later on the transistor and the integrated circuit
{ tell the story of electronics in general, not just of radio. Indeed, one of the rst
consumer products produced at the birth of the transistor age was a portable AM
radio [9].
Today, the electromagnetic spectrum is crowded with literally millions of radio
signals. Frequency use extends from about 3kHz up to 300GHz, or eight orders of
magnitude in frequency. Of course, much of the research on integrated receivers
today lies near the upper end of that frequency range. To understand how to design
robust receivers in such a hostile environment, we will now consider some of the
historical developments that have led to the radio architectures used today.
2.2 Classical Receiver Architectures
The design of wireless receivers is a complex, multi-faceted subject that has a fascinating history. In this section, we will explore many of the fundamental issues
that arise in receiver design through the vehicle of historical examples. These early
receiver architectures illustrate an increasing level of sophistication in response to
the need for improved selectivity at ever-greater frequencies. By considering their
salient features, we lay the groundwork for a more formal treatment of the fundamental issues in the next section.
8
Chapter 2: Radio Receiver Architectures
AM Detector
(a)
(b)
Figure 2.1: The crystal detector. (a) Schematic. (b) System diagram.
2.2.1 Crystal Detectors
One of the earliest radio receivers is the crystal detector, shown in Figure 2.1. It
is hard to imagine a more simple radio than this one. The received signal from
the antenna is bandpass ltered and immediately rectied by a simple diode. If a
suciently strong amplitude modulated radio signal is received, the rectied signal
will possess an audio frequency component that can be heard directly on a pair of
high-impedance headphones. The desired radio channel can be selected via a variable
capacitor (or condenser, according to the terminology of the day). Remarkably, this
radio does not require a battery; the received signal energy drives the headphones
directly without amplication.
In the early 1900's, receivers of this type typically used diodes made of carborundum (silicon carbide) or galena (lead sulde). Later on, with the advent of the
vacuum tube, the \Fleming valve" or vacuum tube diode was sometimes substituted
for the rectifying \crystal". Although exceedingly simple, the detector circuit used
in this design was used in many of the more sophisticated radios that followed.
Though its simplicity is appealing, the crystal radio suers from many important
limitations that future architectures would seek to overcome. First, this receiver has
very poor sensitivity. The rectied signal drives a pair of headphones directly. In
addition, the received signal must be strong enough to periodically forward-bias
2.2: Classical Receiver Architectures
9
the detector diode. These facts imposed a severe limitation on the transmission
distance, or equivalently, on the transmitted power required for a given distance. At
rst, this burden was transferred to the transmitter side, where various techniques
were developed to allow higher and higher transmit powers [7]. Later, the advent of
the vacuum tube amplier would permit the development of more sensitive receivers,
thereby reducing the transmit power requirements.
Second, with only a simple bandpass lter, the crystal radio is not very selective. Accordingly, nearby radio channels may interfere with the desired channel. In
addition, the use of spark gap transmitters, which persisted well into the 1920's,
presented a pernicious source of interference due to the broadband nature of the
spark signals. Although designs that followed would at rst retain a similarly simple
ltering approach, as frequencies increased the fractional bandwidth requirements
for channel ltering would soon make the use of a single RF lter impractical.
With the advent of the vacuum tube triode (or audion, as its inventor liked to
call it [10]), an early attempt to improve the sensitivity of the crystal radio took
the form shown in Figure 2.2 [11]. This design was able to improve the audibility
of received signals by about a factor of ten by using a galena crystal along with the
audion. Signals from as far as 5,000 miles away could be detected with this simple
technique.
It is interesting to note that this particular design was implemented at a time
when the audion was very poorly understood and misconceptions abounded, many of
which were perpetuated by its inventor. The rst correct elucidation of the audion's
behavior was given by Armstrong in 1914 [12], a mere ten days after the design
in Figure 2.2 was presented. This serves to illustrate that even at the turn of the
century, radio designers were working at the leading edge of electronics technology
and were successful despite incomplete knowledge. This is often true today; indeed,
certain aspects of this thesis demonstrate a similar situation, as will be shown later.
From the examples in this section, we see that two important limiting factors in
radio design are the need for sensitivity and selectivity. The rst of these factors was
addressed to some extent with the advent of the heterodyne receiver.
10
Chapter 2: Radio Receiver Architectures
(a)
AM Detector
(b)
Figure 2.2: The crystal detector and audion amplier. (a) Schematic. (b) System
diagram.
2.2: Classical Receiver Architectures
11
AM Detector
(a)
(b)
Figure 2.3: The heterodyne receiver. (a) Schematic. (b) System diagram.
2.2.2 Heterodyne
The heterodyne receiver, shown in Figure 2.3, was rst patented by Professor Reginald Fessenden in 1902 [13]. Initially used for wireless telegraphy, the receiver operates by summing a local oscillator signal with the received radio signal and rectifying
the result. In the process of rectication, a \beat note" is produced in the headphones indicating the presence of the received radio signal. The operator of a receiver
of this type could adjust the frequency of the local oscillator to select a comfortable
pitch of the beat note.
The key advantage to the heterodyne receiver over a simple crystal detector was
the increase in demodulation eciency aorded by the use of the local oscillator.
Even if the received signal was somewhat weak, the local oscillator could commutate the diode detector so that the beat note could be eciently demodulated. So
signicant was this improvement that early treatises on the heterodyne's operation
wrongly concluded that the apparatus increased the energy of the received signal, a
startling claim that was later shown to violate conservation of energy [14].
One signicant problem with the heterodyne receiver in Figure 2.3 is that the
local oscillator is summed in series with the antenna, thereby rebroadcasting the
local oscillator. However, this was not a serious problem when the heterodyne was
rst invented due to the fact that the received signal levels were typically very
12
Chapter 2: Radio Receiver Architectures
large (perhaps hundreds of millivolts). Later on, however, as the density of users
and transmitters increased, and as transmitters began to operate on reduced power
levels, isolation between the local oscillator and antenna became essential.
The most enduring feature of the heterodyne receiver is the use of frequency
conversion under the control of a local oscillator. Although the initial purpose was
to simply produce an audible tone for the detection of wireless telegraphy signals, the
general concept of frequency conversion would later prove to be much more powerful
when adapted for use in the superheterodyne receiver of Armstrong. Apparently,
the general utility of this frequency conversion technique was unrecognized by the
inventors.
In summary, the heterodyne receiver provided an increase in sensitivity by improving the eciency of demodulation with the use of a local oscillator. It also
introduced the concept of frequency conversion that would soon revolutionize the
receiver art.
2.2.3 Regenerative Receiver
Another innovation that sought to improve the sensitivity of radio receivers was the
regenerative receiver, introduced by Armstrong in 1915 [15]. One version of this
improved \audion" receiver is shown in Figure 2.4.
The regenerative receiver employed a single audion bulb for simultaneous use as
a detector and amplier. By placing a capacitor in series with the grid, the gridto-lament circuit could be used as a simple detector with operation identical to
a vacuum tube diode or \Fleming valve" as it was known at the time. However,
unlike a Fleming valve or crystal detector, the audion would amplify the rectied
grid signal in the plate circuit.
However, Armstrong was not happy with the improvement oered by this use
of the audion alone. To increase the gain, he coupled the output of the amplier
back to the input circuit with a radio-frequency transformer. In addition, he used
a coil to increase the inductance of the input signal source. In modern terms, that
inductance, when combined with the shunt capacitance in the grid circuit, forms an
2.2: Classical Receiver Architectures
13
A
B
(b)
(a)
Figure 2.4: The regenerative audion receiver. (a) Schematic. (b) System diagram.
impedance transforming network called an L-match that increases the signal voltage
available for amplication by the audion. A similar L-match appears in series with
the plate circuit.
In another ingenious stroke, Armstrong also coupled the output of the amplier
back to its input with an audio-frequency transformer to pass the demodulated signal
back through the amplier once again. Thus, the single audion served as detector,
RF amplier and audio amplier. To avoid interference with the RF feedback, the
audio transformer was bypassed with capacitors at high frequencies.
In yet another variation on the basic regenerative receiver concept, Armstrong
introduced a dierential version that was able to reject static noise interference
while retaining signal amplication. With this arrangement, Armstrong was able to
receive signals at Columbia University from as far away as Germany and Hawaii. In
a telling statement at the end of the paper, Armstrong attributes the success of his
designs to \a proper understanding and interpretation of the key to the action of
the audion".
Thus, we see that the important features illustrated by the regenerative receiver
include the concepts of impedance transformation, gain boosting with positive feedback and the use of an active device for signal amplication and rectication; in
14
Chapter 2: Radio Receiver Architectures
modern terms, an active mixer. In addition, the selectivity of the system beneted
from the use of multiple lters.
With the operating principle of the audion rmly established, and with the frequency conversion property of the heterodyne, the stage was set for the appearance
of the basic radio architecture that is still used today in the vast majority of radio
receivers: the superheterodyne receiver.
2.2.4 Superheterodyne
The superheterodyne receiver was invented by Armstrong in early 1918 [16] and the
full technical details of the system were made public on December 3, 1919 [17]. A
six-tube version of the receiver would later achieve wide commercial success as the
rst mass-produced AM radio. Despite the vast changes in electronics technologies
since 1918, the superheterodyne architecture has endured and now forms the basis
for almost all radio receivers made today.
In 1918, the detection of short-wavelength radio signals presented several challenges. The signal strength was generally much weaker than at longer wavelengths,
making direct detection impractical and thus raising the need for more sensitive
architectures. Direct amplication of short-wave signals was often impossible due
to the limited frequency response of vacuum tubes available at the time. Finally,
heterodyning of these signals required a very stable local oscillator that was dicult
to implement (the superheterodyne preceded the advent of crystal resonators by a
few years [18]).
Armstrong met these challenges in characteristically brilliant fashion with the
superheterodyne architecture. A simplied version of his receiver with only a single
amplier stage is shown in Figure 2.5. The receiver employs a heterodyne front end
that mixes the incoming radio signal with a local oscillator in a vacuum-tube detector to translate the RF signal to a pre-determined \intermediate frequency" where
the signal can then be amplied and detected. By heterodyning to an intermediate
frequency, the stability of the local oscillator becomes less important (though not
irrelevant by any means, as we will see later on). Highly selective amplication and
2.2: Classical Receiver Architectures
15
D1
A
D2
H
(a)
AM Detector
(b)
Figure 2.5: The superheterodyne receiver. (a) Schematic. (b) System diagram.
16
Chapter 2: Radio Receiver Architectures
ltering can easily be obtained at the lower IF frequency so that detection of weak
signals is made possible. In addition, through the use of multiple frequency conversions, the total required amplication can be distributed across several frequencies
thereby aiding the stability of the amplier stages and increasing the total possible
amplication. Finally, by tuning the local oscillator to dierent frequencies, dierent
RF signals could be selected for detection without having to re-tune the amplier
circuitry. This simplicity of adjustment opened the possibility of making a radio that
could be used by unskilled operators. This feature would prove to be important in
satisfying consumer demand for cheap and easy-to-use AM radios.
The concept of using multiple stages of frequency conversion to gain increased
selectivity and extreme sensitivity is a powerful one that is widely used today. In
addition, the concept of using a simple heterodyne detector to access radio signals
that are beyond the frequency range of existing amplier technology is still widely
used in the millimeter wave frequency range from 30{300GHz [19].
2.2.5 Superregenerative Receiver
There is another receiver architecture due to Armstrong which, though not as enduring as the superheterodyne receiver, deserves honorable mention in the history of
radio for its ingenuity. This architecture, known as the superregenerative architecture, employed a bizarre principle of amplication and detection in which a single
vacuum tube was capable of producing power gains on the order of 100,000; a truly
remarkable feat for a single triode tube [20]. A schematic of one incarnation of the
superregenerative receiver is shown in Figure 2.6.
The rst tube in this receiver is an RF oscillator whose oscillations are periodically quenched by a second oscillator, formed with a second tube, that runs at a
lower frequency. At the end of each quench period, oscillations in the RF tube build
up in response to initial conditions imposed by the incoming radio signal. Thus, after a xed elapsed time imposed by the low frequency oscillator, the RF oscillations
build up to a level whose amplitude is proportional to the instantaneous amplitude
of the received radio signal at the moment that oscillations began. The longer the
2.2: Classical Receiver Architectures
17
(a)
AM Detector
(b)
Figure 2.6: The superregenerative receiver. (a) Schematic. (b) System diagram.
18
Chapter 2: Radio Receiver Architectures
time between quench periods, the greater the gain that can be achieved. In fact,
the maximum gain depends exponentially on the relative frequencies of the two oscillators. The resulting output signal from the RF oscillator is a series of oscillation
bursts whose amplitudes are proportional to the RF signal amplitude. The output
can then be demodulated with a simple AM detector.
Remarkably, this receiver technique is essentially a sampled-data system. The
radio signal amplitude is periodically sampled at the end of each quench period and
the regenerative action of the RF oscillator amplies these signals as the oscillation
envelope grows exponentially. Because of the exponential growth, fabulous signal
gains can be achieved. And, because the sampling rate is less than the carrier frequency but greater than the modulation bandwidth, the superregenerative receiver
can be viewed as the rst sub-sampling radio architecture.
2.2.6 Autodyne and Homodyne
In the regenerative receiver, when the output is overcoupled to the input, the system
oscillates, and this oscillation can be used to heterodyne the incoming RF signal.
Such an arrangement was originally called an \autodyne", or automatic heterodyne,
system [21]. In 1924, Colebrook observed that making the autodyne frequency equal
to the RF frequency eliminated the need for an A.M. detector [22]. Thus, the
homodyne receiver was born.
Unfortunately, for the homodyne to work eectively, the local oscillator must
be precisely synchronized with the RF carrier. Any phase dierence would lead to
a reduction of the demodulated signal level. Recognizing the need for carrier synchronization in the homodyne receiver, a Frenchman named de Bellescize patented
a version of the homodyne in 1930 that included carrier synchronization circuitry
[23]. This receiver is shown in Figure 2.7.
The received RF signal is demodulated by a dual-grid tube in which a local
oscillator is applied to the second grid. The demodulated output is lowpass ltered
and the dierence frequency (nominally D.C.) is applied to a control tube that tunes
the oscillator tube to keep it synchronized with the received RF carrier. Hence, this
2.2: Classical Receiver Architectures
19
(a)
(b)
Figure 2.7: The homodyne receiver of de Bellescize. (a) Schematic. (b) System
diagram.
20
Chapter 2: Radio Receiver Architectures
technique is essentially the same as that used in modern phase-locked loops. Note
that the selectivity of this receiver rests almost entirely on the audio lowpass lter.
The homodyne concept has been revived in recent years for application in paging
receivers, which use a very simple FSK signaling technique. In applications requiring
greater sensitivity and selectivity, the homodyne stands at a disadvantage due to its
sensitivity to D.C. osets and 1/f noise in the audio section. Also, because the
local oscillator is tuned to the RF frequency, it can radiate back out the antenna
and interfere with other receivers or reect and be re-received and downconverted
into a substantial, time-varying D.C. oset. These problems have prevented the
widespread proliferation of the homodyne, although interest in the architecture has
recently been revived [24].
2.2.7 Single-Sideband Transmission
With the growth of the radio art in the 1920's came the need to conserve the use of
the spectrum. Economic factors motivated such conservation because a conservation
of spectrum led in turn to increased capacity. One of the key developments that
enabled a signicant spectral savings was the advent of single-sideband transmission,
which had its origin in multi-carrier wireline telephony [25]. The single-sideband
transmission technique was apparently invented by John R. Carson in 1915 for use
in the Bell System [26] and he led patents for several inventions related to singlesideband transmission and reception in 1915 and 1916 [27] { [29]. For the present
GPS work, the history of SSB transmission has direct relevance because the dual of
the SSB transmitter is the image-reject receiver. The use of image rejection enables
a high level of integration to be achieved, as will be shown in the following chapters.
A standard A.M. system produces a modulated signal comprising a carrier and
two information-bearing sidebands: an upper sideband and a lower sideband. Because the carrier conveys no information, while the two sidebands convey redundant
information, signicant power and spectral savings can be had if the carrier is suppressed and one of the sidebands eliminated before transmission. The benets of
such an approach also include improved transmission distance because the transmit
2.2: Classical Receiver Architectures
21
(a)
(b)
Figure 2.8: The single-balanced modulator. (a) Schematic. (b) System diagram.
power required for the carrier and rejected sideband may be reallocated for use in
transmitting the remaining sideband [30].
One of the key inventions of Carson for SSB transmission that would nd wide
application in radio is the single-balanced modulator, shown in Figure 2.8. This
modulator consists of two triode modulators with the modulating signal injected differentially and the carrier injected in a common-mode fashion. When the modulated
output signal is then extracted dierentially at the output of the two modulators,
the carrier, being a common mode disturbance, is suppressed and does not appear
in the output. Thus, the balanced modulator accomplishes the rst task in SSB
modulation: the rejection of the carrier.
22
Chapter 2: Radio Receiver Architectures
In a typical SSB transmitter of the 1920's, the second task of sideband suppression would be handled by a simple lter that would pass the desired sideband and
reject the undesired one. Due to the practical diculties associated with ltering
out one of the sidebands when the carrier frequency was high, practical transmitters
used a sequence of frequency translations and lters to upconvert the modulated
signal to a target frequency in stages while ltering out the unwanted sidebands
generated at each step, thereby relaxing the required lter order [26]. This same
principle can be applied to receivers as well to obtain greater selectivity. In fact,
one might consider the superheterodyne receiver itself to be a dual of this type of
SSB transmitter. Although this technique was very practical and widely used, it was
expensive to implement due to the number of frequency translation steps involved.
So, two important contributions arising from the SSB transmission eorts of Carson and others are the balanced modulator and the use of multiple frequency translations to ease the ltering burden in selecting the desired sideband. Nonetheless,
the expense of this early SSB technique led to the development of other approaches
that did not rely on sharp lters. The rst of these alternative approaches was the
Hartley modulator.
2.2.8 Hartley Modulator
In 1925, Ralph V. L. Hartley invented a SSB modulator that replaced the more
expensive ltering technique with a phase-shift technique that allowed direct cancellation of the unwanted sideband. His original system, taken from his 1928 patent
[31], is shown in Figure 2.9.
The basic operating principle of the Hartley modulator is to produce two modulated signals: one with sidebands that are in phase with each other, and one with
sidebands that are out of phase with each other. Then, by adding or subtracting the
two modulated signals, one of the two sidebands can be reinforced while cancelling
the other. The necessary phase shifts are most expediently introduced by two 90
phase shifters: one in the audio signal path and the other in the oscillator circuit.
2.2: Classical Receiver Architectures
23
(a)
π/2
π/2
(b)
Figure 2.9: The Hartley SSB modulator. (a) Schematic. (b) System diagram.
24
Chapter 2: Radio Receiver Architectures
In Hartley's original implementation, two bandpass L-C ladder lters (or \electric
wave-lters" as they were then called [32][33][34]) provided a 90 phase shift between
the two audio channels by the addition of an extra L-C section in one of the lters.
The lter complexity was required to provide accurate quadrature over the whole
audio band of interest. In contrast, the quadrature in the oscillator circuit was
obtained with a simple R-C network.
The essential contribution of Hartley's modulator is the use of phase shifts to
achieve cancellation of the undesired sideband. In modern terms, one could say that
he introduced complex signal processing with his use of quadrature signal and local
oscillator paths.
Unfortunately, a major drawback in the Hartley modulator is the need for lters
that provide accurate, broadband quadrature while maintaining amplitude balance
between the two audio channels [35]. This limitation was later removed by an
innovative modication due to Donald K. Weaver, Jr.
2.2.9 Weaver Modulator
In 1956, Weaver introduced another method for generating SSB modulation [36].
Interestingly, he referred to his method as a \third" method, in deference to those
introduced by Carson and Hartley, thereby implicitly ignoring other techniques that
had been developed, such as one due to Kahn that used envelope elimination and
restoration [37]. A schematic of Weaver's original implementation of his method
appears in Figure 2.10.
In essence, the Weaver modulator replaces the broadband quadrature lter networks in the Hartley modulator with a quadrature frequency conversion. The generation of a quadrature rst local oscillator is relatively simple because it operates
at a xed, single frequency. Hence, a simple R-C network suces for quadrature
generation. With the burden of quadrature generation now shifted to the local oscillators, the two signal paths can be more accurately matched for improved sideband
suppression. Just as in the Hartley modulator, sharp lters are not required in this
technique.
2.2: Classical Receiver Architectures
25
(a)
π/2
π/2
(b)
Figure 2.10: The Weaver SSB modulator. (a) Schematic. (b) System diagram.
26
Chapter 2: Radio Receiver Architectures
Although the original implementation employed a frequency downconversion
from the audio band to DC, the principle of operation still holds for other choices
of IF frequency. Indeed, the same architecture can be used as an SSB modulator or
as an SSB receiver by reversing the sequence of frequency translation steps.
The Weaver modulator has become the most widely-used architecture for SSB
receivers today. For a number of reasons that will be addressed in the next chapter,
the Weaver receiver is the architecture of choice for a highly-integrated GPS receiver.
2.3 Summary
In this chapter, we have seen how the developments during the early years of radio
by Armstrong, Carson, Hartley, Weaver and others paved the way for the modern
radio receivers. Collectively, these pioneers introduced the important concepts of
frequency conversion, electrical ltering, balanced modulation and complex modulation are widely used in radio receivers today. Although the specic circuit implementations have changed, the basic principles remain the same. In particular,
the superheterodyne architecture introduced by Armstrong is the most widely used
receiver architecture today.
In the following chapter, we turn our attention to a more formal treatment of the
fundamental issues that are introduced by these techniques which must be addressed
in any successful receiver design. In addition, we will examine certain special issues
that arise specically in the context of integrated radio receivers.
Chapter 3
Fundamentals of Radio Reception
T
HE goal of this chapter is to provide a formal review of the essential concepts
of noise, distortion, cascaded systems and frequency conversion. The selection
of a suitable receiver architecture for a given radio standard is aided by a strong
foundation in these topics. Hence, this section provides the background material for
understanding the architectural tradeos discussed in the next chapter. We begin
with the important topic of noise.
3.1 Noise in Radio Receivers
The sensitivity of all radio systems is limited by the presence of electrical noise that
arises as a result of random uctuations in current ow. Electrical noise can take on
several forms including 1/f noise, thermal noise and shot noise. In radio receivers,
our primary concern is generally with thermal noise which forms the subject of this
section.
Surprisingly, the nature of thermal noise uctuations was not understood until
1928 when Johnson and Nyquist published back-to-back papers describing experimental measurements and a statistical theory of noise [38] [39]. For example, in
1914, Lee de Forest boasted that \there appears to be no lower limit of the sensitiveness to the Audion, no minimum of suddenly applied e.m.f., below which the
received impulses fail to produce any response." [10]. Sadly, he was quite mistaken.
27
28
Chapter 3: Fundamentals of Radio Reception
The work of Johnson and Nyquist showed that all resistances in thermal equilibrium produce an available noise power that is proportional to the absolute temperature and the measurement bandwidth. Thus,
Pav = kTB
(3.1)
where k is Boltzmann's constant. Nyquist, in particular, produced an elegant and
simple derivation of this fundamental relationship from rst principles.
Two observations are in order. First, the fundamental quantity is the available
noise power, which is the maximum power that can be delivered to a load impedance.
This power has a value of 4 10,21 W/Hz at a temperature of T =290K. In the radio
eld, it is common to express signal powers in decibels, referenced to 1mW, which is
typically denoted with the unit \dBm". Thus, the available noise power at T =290K
is given by
,21 W=Hz
Pav = 10 log 4 1 10
10,3W = ,174dBm=Hz
(3.2)
For a real resistance, the condition for maximum power transfer is that the load
resistance be of equal value.1 Because of this, the noise power can be attributed
to an equivalent noise voltage in series with the resistor having a mean-squared
amplitude of
vn2 = 4kTBR
(3.3)
or, equivalently, a noise current in parallel with the resistor having mean-squared
amplitude
i2n = 4kTB
R
(3.4)
Note that for a complex impedance, maximum power transfer occurs when the load impedance
is the complex conjugate of the source impedance.
1
3.1: Noise in Radio Receivers
29
where R is the resistance value. Thus, although the available power is independent
of resistance, the voltage or current is not. Secondly, the Nyquist relationship only
holds for resistances that are in thermal equilibrium. This opens the possibility
of producing by electronic means a real impedance that produces less noise power
than a passive resistor because active electronics do not exist in a state of thermal
equilibrium. This observation forms the basis of the art of low-noise amplication,
in which an amplier presents a specied input impedance that has an equivalent
noise temperature associated with it that may be less than the ambient temperature.
In a radio receiver, the antenna also collects noise from the environment according to its power-directivity receiving pattern. Because the sky has a much lower
noise temperature than the earth, the average noise temperature of an antenna will
generally be less than the ambient temperature. To account for this dierence, one
can dene an eective temperature for the antenna, Ta , that describes how much
noise power it collects. Its available thermal noise power will then be given by
Pa = kTa B:
(3.5)
In addition to noise collected by the antenna, the receiver electronics produce
noise. To quantify the amount of noise thus introduced, North [40] introduced a
quantity called noise gure, which is dened as
Total output noise
F =4 Total output
noise due to the source
(3.6)
where the \source" is the antenna radiation resistance, under the (arbitrary) assumption that the antenna temperature, Ta , is 290K. This slightly chilly reference
temperature was specically proposed by Friis [41] because for this temperature
kT = 4 10,21 W/Hz, a nice round number. Note that, for any passive network,
kTB = 1 = L
F = kTBG
Ga a
a
(3.7)
30
Chapter 3: Fundamentals of Radio Reception
where La is the available power loss of the network, dened as the available power
at the input of the network divided by the available power at the output of the
network.
A minor renement of the language in (3.6) is necessary to avoid confusion in the
case of mixer noise gures. The denominator in that case should read total output
noise due to the source that originates from the signal band of interest. This distinction is necessary because mixers typically convert noise from multiple frequencies,
as discussed in the section on frequency conversion.
With these denitions, the equivalent noise power at the antenna terminals of a
radio receiver is given by
Peq = kTB TTa + (F , 1) :
(3.8)
which reduces to simply FkTB if Ta = T .
With the noise gure thus dened, it is a simple matter to specify the sensitivity
of a radio receiver. If a specied minimum SNR is required for acceptable detection,
the corresponding minimum detectable signal power is simply
Pmin = SNRmin kTB TTa + (F , 1) SNRmin FkTB
(3.9)
where B is equal to the eective noise bandwidth of the system. The approximation
in (3.9) is only valid if Ta T . For the nearly isotropic antennas used in most
commercial GPS receivers, Ta < T and the more exact expression should be used.
It is worth noting that the noise gure of any two-port network is determined
by three quantities: the equivalent input voltage noise, the equivalent input current
noise and the correlation coecient relating the two noise sources. Because the
correlation is generally complex, there are four parameters required to determine
the noise performance of an arbitrary network [42]. Associated with these four
parameters is a minimum noise gure that can be achieved and an optimum source
impedance for achieving it. The reader is referred to [43] for the details of the
3.2: Signal Distortion and Dynamic Range
31
classical technique, or to the Appendix for an example of a noise gure calculation
for a simple MOSFET device.
3.2 Signal Distortion and Dynamic Range
If the thermal noise of a receiver sets the sensitivity, then the distortion introduced
by the receiver sets the maximum signal level. The ratio between maximum and
minimum signal levels denes the dynamic range of the receiver. This section explores the methods by which distortion is generated and formulates an expression
for dynamic range that will prove useful later in the analysis of active lters.
It is common to assume that a distorting element has a transfer characteristic
given by a simple power series
vout = k1vin + k2vin2 + k3vin3
(3.10)
where k1 {k3 are the gain, second- and third-order distortion coecients, respectively.
In such a case, if an input consisting of two closely-spaced sinusoidal components
vin = Acos (!1t) + Acos (!2t)
(3.11)
is applied to the input, the output will contain several distortion products at frequencies n!1 m!2 , where n + m is the order of the distortion product. Hence,
in this case, n + m 3. Furthermore, the amplitude of each product varies as
An+m. So, second-order products vary in proportion to A2 and third-order products
in proportion to A3 [44].
Figure 3.1 illustrates the behavior of the various intermodulation products with
input amplitude. With the input and output amplitudes plotted on a log scale,
the intermodulation product amplitudes follow straight line trajectories with slopes
given by the order of the products. By extrapolating, intercept points can be found
that serve as gures of merit for the linearity of the amplier. These points can be
referred to the input or output of the amplier, as desired. Note that in a dierential
32
Chapter 3: Fundamentals of Radio Reception
dB
dB
-ord
er
1
3
third
2
fir
st
-o
rd
er
1
Output Amplitude
fir
st
-o
on
rd
d-o
er
rde
r
OIP3
sec
Output Amplitude
OIP2
dB
IIP2
dB
IIP3
Input Amplitude
Input Amplitude
Figure 3.1: Illustration of intermodulation behavior.
implementation, the second-order distortion is cancelled. Thus, in practice, secondorder intercept points are typically much higher than third-order intercept points.
One aspect of third-order intermodulation distortion merits special attention.
Among the third-order products are those that occur at 2!1 , !2 and 2!2 , !1.
If !1 !2, then these distortion products lie close to the fundamental tones in
frequency and pass through any signal lters in the system virtually unattenuated.
As a result, third-order nonlinearity represents a particular threat in radio systems.
If we assume that the distortion is dominated by third-order nonlinearity, we can
formulate a useful expression for the spurious-free dynamic range of the amplier.
We dene the peak SFDR as the dierence between the maximum power level for
which third-order intermodulation products lie below the noise oor and the minimum detectable signal power. The input-referred third-order distortion power level
is given by
3
P
s
PIM3 =
;
IIP32
(3.12)
3.3: Frequency Conversion and Frequency Planning
33
where Ps is the available source power and IIP3 is the available source power corresponding to the input-referred third-order intercept point. Setting this expression
equal to FkTB and solving for Ps = Pmax , we obtain
Ps = Pmax = IIP32 FkTB
1=3
(3.13)
Hence, the peak SFDR is given by
IIP3
SFDRpk = Pmax = 1
Pmin SNRmin FkTB
2=3
(3.14)
An important caveat should be mentioned at this point. Although intercept
points are useful gures-of-merit for ampliers, they should be used with caution.
In particular, practical ampliers have gain and distortion curves that do not follow
straight line trajectories when plotted on logarithmic axes. Thus, the intercept point
loses its meaning unless the input or output power from which it is extrapolated is
also specied. As a rule of thumb, the intercept points should be extrapolated from
around the maximum anticipated operating power level of the amplier in question.
As a nal note, although third-order intermodulation distortion has special significance for radio receivers, there are some architectures that are particularly susceptible to second-order distortion. In particular, direct conversion receivers are sensitive
to second-order distortion products that lie near DC because in such receivers the
RF input is translated directly to DC itself [45].
3.3 Frequency Conversion and Frequency Planning
In the previous subsections, we examined the topic of receiver sensitivity and dynamic range. The concepts presented there enable an evaluation of noise and linearity tradeos. In this section, we turn to the frequency domain to consider the
topic of frequency conversion. In particular, we will look at the non-idealities introduced by practical frequency converters and the tradeos involved in the selection
of intermediate frequencies and ltering strategies.
34
Chapter 3: Fundamentals of Radio Reception
The modern term for the frequency converter is the mixer. All mixers operate
on the principle that if two sinusoidal signals are multiplied together, the resulting
product has sum and dierence frequency components. Thus,
2cos (!1t) cos (!2 t) = cos (!1t + !2t) + cos (!1t , !2t) :
(3.15)
Note that if one of the cosines in the above expression is modulated in amplitude or
frequency, the modulation is preserved in the output products. So, by multiplying
an incoming radio signal with a local oscillator, one can translate the modulated
signal to a dierent frequency for further processing.
There are two families of techniques for producing the desired multiplication:
nonlinear techniques and time-varying techniques. In a nonlinear approach, the two
sinusoidal signals are summed together and allowed to interact in a nonlinear device,
such as a diode, vacuum tube or transistor. The resulting cross-modulation terms
provide the desired frequency translation. However, the nonlinearity also produces
signal distortion that is undesirable. In a time-varying approach, a variable gain
block under the control of a local oscillator is used to produce direct modulation of
the input signal. Because this technique is linear, cross-modulation between input
signal frequencies and distortion of the input are avoided. As a result, the majority of
modern mixers are of the time-varying variety. Nonlinear mixers nd their primary
use at very high frequencies and in low-cost applications, such as toy walkie-talkies
and virtually every consumer AM radio. Figure 3.2 shows some examples of each
type of mixer. Note that time-varying mixers may be of the voltage commutating
type, such as the diode ring mixer, or of the current commutation type, such as the
popular \Gilbert" mixer. 2
All mixers are characterized in part by their conversion gain, which is the ratio
of the desired output signal available power to the input signal available power. If
we assume an ideal mixer of the switching variety that is internally lossless and has
Technically speaking, the current-mode mixer shown in Figure 3.2 is not a Gilbert multiplier
because it does not employ translinear principles but rather switches currents from one branch to
the next under local oscillator control. A true Gilbert multiplier achieves a literal multiplication
of two input signals using the translinear principle [46] [47].
2
3.3: Frequency Conversion and Frequency Planning
Nonlinear Mixers
35
Time-Varying Mixers
Figure 3.2: Various mixer topologies that fall into the nonlinear and time-varying
categories.
36
Chapter 3: Fundamentals of Radio Reception
no bandwidth limitation and in which the instantaneous voltage gain from input to
output alternates between one and minus-one at the local oscillator frequency, then
the signal voltage at the IF port of the mixer is related to the signal voltage at the
RF port by
vif (t) = sgn (cos (!lo t)) vrf (t) = m(t)vrf (t);
(3.16)
where the sgn () function yields the sign of its argument. By performing a Fourier
analysis of m(t), we can easily determine that its fundamental component at !lo has
an amplitude of 4=. Thus, by reference to equation (3.15), the voltage conversion
gain is given by
Gc = 2 = ,3:92dB:
(3.17)
In this example, the mixer is internally lossless and hence the voltage conversion
gain is equivalent to the available power conversion gain.
Because the mixer produces both sum and dierence frequencies at its output,
there are two input frequencies that are translated with this conversion gain to the
output at the same intermediate frequency, !if . These are !lo !if . Typically, one
of these frequencies is the desired RF signal while the other is commonly called the
image frequency. Note that signals present at the image frequency can corrupt the
intermediate frequency signal after mixing, making it desirable to reject the image
before mixing.
One technique for doing so is shown in Figure 3.3, where the image frequency
is removed with a simple bandpass lter. Because the image is separated from the
desired frequency by 2!if , a high IF frequency relaxes the design of the image lter.
On the other hand, a second lter at the IF frequency is typically used to select
the desired signal and reject all other remaining signals. This channel-select lter is
easier to implement if the IF frequency is low. Hence, the goals of selectivity and
image rejection are in opposition and can be traded o by appropriately selecting the
IF frequency. The essential aim of frequency planning is to select an IF frequency
3.3: Frequency Conversion and Frequency Planning
37
Det.
I.R. Filter
C.S. Filter
Figure 3.3: A simple receiver with image-reject lter and channel-select tler.
that adequately balances these competing requirements. One possible solution to
this dilemma is to use two IF's, a high rst IF to ease the image-reject lter design,
and a lower second IF where channel selection can easily be done. This is a common approach in systems that have stringent specications for image rejection and
selectivity. Another possible solution is to eliminate the image-reject lter in favor
of an image cancellation architecture, such as the Weaver SSB receiver. This is the
approach taken in the present work for reasons that will be made clear in the next
chapter.
In addition to frequency conversion, mixers also introduce extra noise that can
degrade the noise gure of a receiver. This extra noise may originate due to losses
internal to the mixer, or it may be directly down-converted from image bands at
the mixer input. To understand this second source of noise, consider the case of
an ideal mixer. If the mixer is internally lossless, then it contributes no noise of its
own to the output and all of the output noise arises due to the source resistance.
Secondly, this noise power is unattenuated by the mixer because the mixer only serves
to periodically change the instantaneous sign of the white noise process without
modifying its variance. Thus, it is tempting to conclude that the total output
noise power is equal to the total output noise power due to the source, resulting in
F = 1. We recall, however, that in the case of mixers we should restrict ourselves to
considering the total output noise due to the source that originates from the frequency
band of interest. If we assume that the frequency band of interest is centered about
one of !lo !if , then this component of the input noise spectrum is multiplied by the
38
Chapter 3: Fundamentals of Radio Reception
mixer conversion gain and appears attenuated at the output. Hence, we conclude
that the true noise gure is actually
FSSB = NNout = GNNs = G1 = 3:92dB
out ;src
c s
c
(3.18)
which is commonly called the single-sideband noise gure to indicate that the input
frequency band of interest is only one of the two possible frequency bands that
produce a response at !if .
In some systems the frequency bands of interest include those centered about
both of !lo !if . In this case, the output noise power originating from these two
input frequency bands is twice as large (assuming that each contributes equally),
and the resulting noise gure is
FDSB = NNout = 2GNsN = 2G1 = FSSB , 3dB = 0:92dB
out ;src
c s
c
(3.19)
which is commonly called the double-sideband noise gure, for reasons that should
now be apparent. Note that the DSB noise gure is always less than the corresponding SSB noise gure, typically by about 3dB. In general, real mixers are not internally
lossless and practical noise gures generally exceed these theoretical numbers for an
ideal mixer.
There is yet another mechanism by which the mixing process can introduce noise
to the system. As illustrated in Figure 3.4, a strong interfering signal (labeled \B"
for blocker) can mix with local oscillator phase noise to produce noise that overlaps
with the desired RF signal. The amount by which the noise oor increases as a
result depends on the strength of the blocking signal. In particular, we can quantify
the increase in noise power in a 1-Hz bandwidth due to the blocker
Pn;b = PbL fflo , fbg = Pb L ff g
(3.20)
In this expression, Pb is the blocker power at the mixer input and L ff g is the
local oscillator phase noise power spectral density relative to the carrier. By setting
3.4: Cascaded Systems
39
B
B
RF
RF
LO
phase
noise
Figure 3.4: Illustration of the reciprocal mixing process.
(3.20) equal to FkT (B = 1Hz), we can determine the blocker power that produces
a 3-dB reduction in SNR, which is
Pb = LFkT
ff g :
(3.21)
This expression can be used to determine the required phase noise specication for
the local oscillator in order to achieve a given blocking performance. For example, a
receiver with a 6dB noise gure and a 3-dB blocker level at 3MHz oset of -20dBm
must have a local oscillator phase noise of better than -148dBc/Hz at 3MHz oset.
3.4 Cascaded Systems
When designing a radio receiver, it is often desirable to specify the performance
of individual blocks (ampliers, mixers, lters) separately to simplify the design
task. The system performance is then determined by the cascade connection of
these individual blocks, so it is important to understand the eects of cascading on
gures-of-merit such as noise gure, linearity and dynamic range.
40
Chapter 3: Fundamentals of Radio Reception
The noise gure of a cascade of signal blocks can easily be shown to be
2,1
F = F1 + FG
+ GF3 ,G 1 + : : :
a1
a2 a1
(3.22)
where Fn is the noise gure of the nth block evaluated with respect to the driving
impedance of the preceding block and Gan is the available power gain of the nth block.
Note that available power gain is dened as the available output power divided by
the available power from the source, where the available power is the power delivered
to a matched impedance load. This denition is not the only denition for power
gain [48], but equation (3.22), which is known as Friis's formula [41], is only correct
when available power gain is used.
From (3.22), we can see that the rst amplier in a radio system contributes the
most to the noise gure of the receiver; the contribution of each subsequent stage
is reduced by the total available power gain preceding it. Thus, when designing for
specic sensitivity, the greatest burden is borne by the rst amplier stage. For this
reason, is important to have a low noise amplier as close to the antenna as possible
when maximum sensitivity is desired.
In a similar fashion, we can evaluate the linearity of a cascade of signal blocks.
The production of intermodulation distortion in an amplier cascade is somewhat
more complicated, however, because the distortion products produced by each stage
may have arbitrary phase relationships that make it dicult to precisely determine
the cumulative distortion. However, with the simplifying (and somewhat optimistic)
assumption that all distortion products add in power fashion, we arrive at the following expression [49]
1 1 + Ga1 + Ga1 Ga2 + : : :
IIP 3 IIP 31 IIP 32 IIP 33
(3.23)
where IIP 3n is the input-referred third-order intercept point of the nth stage, expressed in terms of the available source power, and Gan is the available power gain
of the nth stage.
Relative
Contribution
3.4: Cascaded Systems
41
1111111111111111
0000000000000000
0000000000000000
1111111111111111
IIP3
0000000000000000
1111111111111111
0000000000000000
1111111111111111
0000000000000000
1111111111111111
F-1
0000000000000000
1111111111111111
0000000000000000
1111111111111111
Increasing Stage #
Figure 3.5: The relative contribution of successive stages to noise and distortion.
By re-expressing (3.23) in terms of output intercept points, we can demonstrate
a certain symmetry between this expression and the one for cascaded noise gure.
In terms of output quantities, (3.23) becomes
1 1 +
1
1
+
OIP 3 OIP 3n Gan OIP 3n,1 Gan Gan,1OIP 3n,2 + : : :
(3.24)
Now, at the receiver output, we must support a certain signal power for proper
operation of the detector. This required output power plays a complementary role
in linearity design to that of receiver sensitivity in noise gure design. In this case,
as we work backwards from the detector, the contribution of each stage to the total
OIP 3 is reduced by the gain that follows. Thus, the last stage in the chain tends to
contribute the most to the distortion and it is important to end the chain with an
amplier with high linearity.
Using equations (3.22) and (3.24), one can design a receiver that maximizes IIP 3
and minimizes F , resulting in maximum dynamic range. As we've seen from these
expressions, there is a natural tapering that occurs with early stages contributing
more to the noise gure and later stages contributing more to the distortion, as
illustrated pictorially in Figure 3.5. So, in general it is good for early stages to have
good noise performance and later stages to have good distortion characteristics.
When selecting a gain plan for a receiver, there are three approaches that can
be taken: design for minimum noise gure with acceptable linearity, design for
42
Chapter 3: Fundamentals of Radio Reception
maximum linearity with acceptable noise gure, or design for maximum dynamic
range.
In the rst case, one should taper the gains and noise gures of the stages so
that the rst stage dominates. However, it is important for linearity reasons not to
be too greedy for gain. This approach is commonly used in receiver designs where
sensitivity is paramount. In the second case, one should taper the gains and OPI 3's
of the stages so that the last stage dominates. But one needs to be careful to use
enough gain to meet the sensitivity requirements of the receiver. This approach may
be particularly useful in applications where linearity is more important than noise
gure.
In the last case, the condition for maximizing the dynamic range of a cascade of
ampliers can be determined analytically by considering a simple two-stage system.
Suppose that we have two ampliers with specied noise gures and input intercept
points and that we wish to select the proper gain for the rst amplier to maximize
the dynamic range of the cascade. It can be shown using (3.22) and (3.24) that the
optimum rst stage gain is given by
s
Ga1 =
(F2 , 1) IIP 32 =
F1 IIP 31
r
CR21
CR12
(3.25)
where CR21 and CR12 are the cross dynamic ranges (similar to dynamic ranges)
of the two ampliers, as illustrated in Figure 3.6(a). By putting this expression in
decibel form, the meaning becomes clear.
Ga1 = 12 (CR21 , CR12 )
(in dB)
(3.26)
In words, the optimum gain is half the distance, in dB, between the two cross
dynamic ranges. As shown in Figure 3.6(b), Ga1 causes the output dynamic range
of the rst amplier to be centered on a dB scale with the input dynamic range of the
second amplier. So, in a dynamic-range optimized system, each stage contributes
noise and distortion equally.
3.5: Integrated Receivers
A1
43
A2
A1
IIP32
IIP31
OIP31
CR 21
IIP31
CR 12
(F 2 -1)kTB
F1kTB
A2
IIP32
F1kTBG a1
Ga1 (F 2 -1)kTB
F1kTB
(a)
(b)
Figure 3.6: Optimizing dynamic range. (a) Two ampliers with certain cross dynamic ranges. (b) Illustration of the optimum gain to maximize the dynamic range.
44
Chapter 3: Fundamentals of Radio Reception
3.5 Integrated Receivers
Finally, we turn our attention to several issues that are particularly relevant to
integrated receivers. The lack of high quality passive components and the presence
of a common substrate profoundly inuence integrated receiver design. Because the
goal of this work is to achieve a high level of integration, the following sections briey
consider these factors to motivate the material in following chapters.
3.5.1 Passive Components and the Filter Problem
Most of the classical receiver architectures presented in the earlier sections rely heavily on high quality passive components in their implementations. In an integrated
context, it is relatively easy to fabricate high quality xed-value capacitors, but inductor options are rather limited. The two most viable sources of inductance for
integrated radios are bondwires and spiral inductors. For bondwires, quality factors on the order of 50 are possible at 1GHz, but the achievable inductance values
are limited to a few nanohenries and the absolute tolerance is also limited [50]. In
contrast, spiral inductors oer relatively large inductance values and tolerances on
the order of 5%, but quality factors are typically limited to less than 10 [51]. Recent work has demonstrated methods for improving the quality of spiral inductors
using patterned ground shields [52], but spirals still have markedly inferior quality
compared to o-chip passive components.
For these reasons, selective lters are dicult to achieve in integrated form. At
frequencies near or above 1GHz, spirals and bondwires are very useful for reducing
power consumption and providing limited selectivity, but at lower frequencies the
required inductance values are out of the question. To integrate selective lters
at frequencies below 100MHz, active lters are currently the only viable option.
Unfortunately, active lters impose well-known dynamic range limitations that limit
their utility [53]. In general, architectural choices that reduce the required fractional
bandwidth of the active lters in the chain lead to improved dynamic range. Active
lter issues are discussed in more detail in Chapter 7.
3.5: Integrated Receivers
45
3.5.2 Isolation and Substrate Noise
Integrated radios, by their monolithic nature, have a common substrate that is
shared by all of the circuit blocks on the chip. Because the substrate is not a perfect
ground, isolation between blocks can be a particularly vexing issue [54]. Although
substrate coupling is important in many mixed signal systems, it is especially dicult to mitigate in radio systems. Received signal levels may be on the order of a
microvolt while digital signal amplitudes are typically more than a volt. To avoid
desensitization of the front end due to digital noise coupling, it is therefore necessary
to have isolation on the order of 120dB, which is very dicult to achieve.
To mitigate potential substrate coupling problems, a dierential architecture is
very helpful. The substrate presents a source of common-mode interference that
may be partially rejected with the use of dierential circuits. However, the goal of
cointegrating the baseband DSP and the radio front end on the same chip remains
elusive due to the extreme isolation requirements.
Another method by which isolation is compromised is through spiral inductor
parasitics. Because spirals are relatively large structures (on the order of 300m
square), their capacitive parasitics to the substrate can be quite large. Fortunately,
this source of coupling can be nearly eliminated through the use of patterned ground
shields [52].
In addition to compromising isolation, the substrate introduces resistive losses
that can reduce the quality factor of on-chip reactive components. This is particularly true of spiral inductors and varactors. Furthermore, the parasitic capacitances
associated with bondpads and electro-static discharge (ESD) circuits couple into the
substrate and the reected losses can signicantly impair the performance of lownoise ampliers. So, it is important to shield critical bondpads from the substrate
and carefully optimize ESD circuits to minimize their capacitive parasitics whenever
possible to reduce these vexing sources of loss.
46
Chapter 3: Fundamentals of Radio Reception
3.5.3 Power, Voltage and Current
In the previous sections, design criteria were presented that depend fundamentally
on the available power gains of the individual blocks in a receiver signal chain. There
appears to be widespread confusion in the recent literature about the applicability
of power gain in non-50
environments. This section seeks to clarify some common
misconceptions that seem to persist in the recent literature. Because of these misconceptions, it seems necessary to spend a few paragraphs understanding their source
in the interest of clear communication of the experimental results of this thesis.
There is a fundamental reason for why power quantities are useful in radio design:
the available noise power from any passive network at thermal equilibrium is kTB ,
independent of the resistance or reactance of the network. Note that, in particular,
this available power is independent of the terminating impedance of the network. It
is for this explicit reason that Friis, in his classic paper on noise gure, introduced
available power gain in the denition of noise gure. To quote Friis, \it is the presence
of such mismatch conditions in amplier input circuits that makes it desirable to use
the term available power" (emphasis added) [41].
It is important to recognize that impedance mismatch is a motivator of the use
of power quantities, because it has often been argued that power gain is irrelevant
in integrated radios because integrated radios do not use matched impedances. But
as Friis clearly states, the opposite is in fact true: it is the presence of mismatches
that motivates the use of power terminology! This is not to say that voltage and
current quantities lack utility, but rather that power terminology often provides a
natural and helpful viewpoint.
The widespread misunderstanding of this point stems, in part, from confusion
about power gain itself. The problem is that there are, in fact, at least three denitions of power gain that are useful in dierent situations. These are available gain,
operating gain, and transducer gain, which are respectively dened as [48]:
available from the network
Ga = PPAVN = power
power available from the source
AVS
(3.27)
3.5: Integrated Receivers
47
power delivered to the load
Gp = PPL = power
input to the network
IN
(3.28)
power delivered to the load
Gt = PPL = power
available from the source
AVS
(3.29)
Of these, confusion between operating gain and available gain seems to be the root
of the problem. Note that the operating power gain, Gp, is dened with respect to
the power input to the network. Hence, if the network presents an input impedance
that is highly reactive (such as the gate of a MOSFET), then the operating power
gain can become poorly dened. This argument is sometimes used in support of the
notion that power gain is irrelevant in integrated CMOS ampliers. However, the
power gain used in the design equations of the previous sections is available power
gain, which is perfectly well-dened, even when the operating gain is not. Hence,
available power gain remains a useful quantity for designing ampliers with reactive
input impedances.
But, perhaps the most startling viewpoint of all is that power metrics { and in
particular, power units { are only valid in matched, 50
systems. This viewpoint
has been used by some authors to justify a modication of a standard unit of measure, the dBm, which is correctly dened as the signal power, referenced to 1mW,
expressed in dB. Unfortunately, it is becoming widespread to use dBm to mean the
signal power dissipated in a reference 50
resistor. When used this way, dBm does
not refer to the signal power at all, but rather the signal voltage, referenced to a
hypothetical power level in a ctitious 50
resistance without regard for the actual
signal impedance. Unfortunately, not all authors that employ this non-standard definition are explicit about their assumptions, which leads to unintentional confusion
in the presentation of experimental results and tends to undermine the goal of clear
scientic discourse. Other embarrassments that accompany the use of the corrupted
unit may include an apparent violation of conservation of energy (e.g. ampliers
that deliver more output \power" than they consume from the power supply) and
a complete invalidation of Friis's formula in cases where current noise is signicant.
48
Chapter 3: Fundamentals of Radio Reception
Polyphase Filter
+
I
-
Q
+
+
I
Q
Polyphase
Filter
Figure 3.7: A low-IF image-reject architecture using polyphase lters.
Thus, we can see that a redenition of standard units of measure leads to a plethora
of unfortunate consequences.
So, in the interest of avoiding these problems, power gain will generally refer to
available gain, unless stated otherwise, and the dBm unit will be used with its only
true denition: the signal power, referenced to 1mW, and expressed in dB.
3.6 Review of Recent CMOS Receivers
In this section, we establish a context for the results to be presented in the following
chapters by briey reviewing some of the recent work on CMOS radio receivers.
There are essentially three approaches to integrated CMOS receiver design that
have recently been pursued: image rejection, sub-sampling and direct conversion.
This section presents examples in each category from the recent literature.
Image reject receivers seek to eliminate multiple stages of frequency conversion
and o-chip ltering in favor of image cancellation and a single stage of on-chip
ltering. One example of this approach is illustrated in Figure 3.7 [55]. In this
architecture, the 900MHz RF signal is amplied and ltered with a polyphase lter
3.6: Review of Recent CMOS Receivers
49
+
-
+
+
I
Q
Polyphase
Filter
I
Q
Polyphase
Filter
Figure 3.8: A low-IF image-reject architecture with a wide-band IF.
that produces a complex signal at its output. This signal is then converted to a
low intermediate frequency of 250kHz with a set of complex mixers that essentially
multiply the RF signal by ej!t . Quadrature local oscillators are generated using
another polyphase lter to achieve a 0:3 phase accuracy.
There are two drawbacks of this architecture that are worth mentioning. First,
the use of a polyphase lter in the signal path contributes to a high noise gure due
to the signal loss in the lter. Second, the image rejection is limited to about 46dB,
even after correcting for amplitude errors in the two signal paths. The achievable
image rejection is fundamentally limited by on-chip component matching and the
phase accuracy of the quadrature-generating polyphase lters.
A second approach, shown in Figure 3.8, replaces the polyphase lter in the
signal path with a pair of quadrature mixers and a second local oscillator [56]. An
interesting feature of this 1.9GHz architecture is that no ltering is performed at
the rst IF. This \wide-band IF" is used to make the receiver amenable for use in a
multi-mode radio. The use of a second set of mixers permits the rst local oscillator
to be somewhat removed from the desired RF frequency so that LO leakage back
to the antenna does not present a severe threat. Channel selection is performed
at baseband by a discrete-time switched-capacitor lowpass lter just prior to A/D
conversion. This implementation achieves an image rejection of about 55dB.
50
Chapter 3: Fundamentals of Radio Reception
Demod.
Figure 3.9: A sub-sampling receiver with discrete-time ltering.
A completely dierent approach is illustrated in Figure 3.9, which shows a subsampling receiver architecture in which most of the ltering is performed by discretetime switched-capacitor lters [57]. The 910MHz RF input signal is amplied, ltered and directly sampled before any frequency conversion is performed. By subsampling the signal at 78Ms/s, an aliased image of the RF signal is produced at
26MHz, making the frequency conversion implicit in the sampling process. A sequence of down-sampling discrete-time lters follows, leading ultimately to an A/D
converter.
The primary diculty in this approach is the use of sub-sampling which causes
broadband kT/C noise to alias into the signal band resulting in a very high noise
gure of 47dB. The eect of clock jitter on the receiver noise oor is also exacerbated
as a result of the sub-sampling.
Finally, in a revival of a technique that has found some success in paging receivers
[24], the receiver shown in Figure 3.10 employs a homodyne, or direct-conversion
technique in which the rst (and only) local oscillator is tuned exactly to the RF
carrier frequency [45]. The advantage of this technique is that there is no image
frequency at all, making the architecture very amenable to integration. However,
a signicant problem is that low-frequency 1/f noise and osets in the baseband
section can overload the receiver, thus desensitizing it. One troublesome source of
such osets is LO self-mixing where the local oscillator leaks to the RF port of the
mixer and then self-converts into a DC oset at the mixer output. To prevent this
and other osets from overloading the baseband ampliers, oset cancellation must
51
π/2
4-FSK Detector
3.7: Summary
Figure 3.10: A direct-conversion receiver.
Table 3.1:
Freq. NF
Reference
GHz dB
Crols [55]
0.9 24
Rudell [56]
1.9 14
Shen [57]
0.9 47
Rofougaran [45] 0.9 8.6
CMOS Receiver Summary
IIP3 I.R. Gain Pwr/Vdd Area Tech.
dBm dB dB mW/V mm2
28 46
9
500/5
6 0.7m
-7
55 78 198/3.3 15 0.6m
-16 32 36
90/3.3
3.6 0.6m
-8.3 N/A 140 360/3.3 77 1.0m
be used. The oset cancellation loop must have a very low bandwidth to avoid
interference with the desired signal. This is achieved with a large o-chip 140F
capacitor.
In this direct-conversion receiver, the signaling technique is 4-FSK, which has the
benet that the modulation contains no energy at D.C. so that the oset cancellation
loop does not corrupt the desired signal. Another interesting feature of this receiver
implementation is the use of on-chip suspended spiral inductors with pits etched in
the silicon beneath them. This etching reduces the spiral parasitics in return for a
substantial area penalty.
The performance of the CMOS receivers presented in this section is summarized
in Table 3.1.
52
Chapter 3: Fundamentals of Radio Reception
3.7 Summary
Building on the historical foundation of Chapter 2, this chapter has explored the
mathematical fundamentals of radio reception, including such topics as noise gure,
linearity, dynamic range and frequency planning. In addition, a review of some
recent CMOS radio receivers provides a context for the present work.
Based on the prior art in CMOS radios, the low-IF architecture is the most
appealing approach for channels with radio signals whose modulation contains signicant energy near DC. Such is the case in the GPS system. In addition, there are
other features of the GPS system that lend themselves quite naturally to a low-IF
architectural approach. These motivating factors, and the specic architecture that
results from them, are the primary considerations of the next chapter.
Chapter 4
A Global Positioning System
Receiver Architecture
S
UCCESSFUL radio designs begin with good architectural choices. Unfortunately, there is no radio architecture panacea. Rather, it is essential to select
the approach best suited for the task at hand.
In this chapter, we turn our attention to selecting the GPS radio architecture that
will permit the maximum level of integration while minimizing power consumption.
We begin with the details of the GPS system itself. As will be shown, the GPS
system possesses certain unique features that make it particularly well suited for
integration.
4.1 The Global Positioning System
To motivate the architectural choices described in this chapter, it is important to
consider some details of the received GPS signal spectrum. The GPS system uses a
direct-sequence spread spectrum technique for broadcasting navigation signals. In
such an approach, the navigation data signal is multiplied by a pseudo-random bit
sequence (PRBS) code that runs at a much higher rate than the navigation symbol
rate. This higher rate is commonly referred to as the \chip" rate of the code. The
PRBS codes used in the GPS system are Gold codes that have two possible values
53
54
Chapter 4: A Global Positioning System Receiver Architecture
(1) at any give time. Thus, when a code is multiplied by itself, the result is a
constant value; however, when two dierent codes multiply each other, the result is
another PRBS sequence. This property can be used to separate overlapping received
signals from multiple satellites into distinct data paths for navigation processing.
In principle, by multiplying the received signal by a particular satellite's PRBS
code, the receiver can recover data from that satellite alone while signals from other
satellites pass through with the appearance of pseudo-random noise. Hence, with a
unique PRBS code assigned to each satellite, all satellites can broadcast at the same
frequency without substantially interfering with each other.
The GPS satellites broadcast navigation signals in two bands: the L1 band,
which is centered at 1.57542GHz, and the L2 band, centered at 1.2276GHz. Each
satellite broadcasts two dierent direct-sequence spread-spectrum signals. These are
known as the P code (or precision code) and the C/A code (or coarse acquisition
code). The P code is broadcast in both frequency bands, while the C/A code is
broadcast only in the L1 band. Note that the center frequencies of the L1 and L2
bands are both integer multiples of 10.23MHz, which is the chip rate of the P code
signal. In contrast, the C/A code uses a lower chip rate of 1.023MHz. The P code
is intended for military use and is much more dicult to detect, in part because it
uses a spreading code that only repeats at 1-week intervals. In addition, the P code
is encrypted to restrict its use to authorized (military) users. For this reason, the
C/A code is of primary interest in commercial applications.
Figure 4.1 illustrates the spectrum of the GPS L1 band. In this gure, we see
that the C/A code and the P code occupy the same 20-MHz spectrum allocation,
but their main lobes have dierent bandwidths due to the dierent code chip rates.
In particular, the C/A code has a main lobe width of 2MHz while the P code has
a width of 20MHz. The outlying lobes of the P code are truncated by appropriate
ltering so that the entire GPS broadcast ts neatly within the 20-MHz allocation.
The immunity to interference that is gained when using the spread-spectrum
technique is related to the ratio of the chip rate to the symbol rate. This ratio,
called the processing gain, gives an indication of the improvement in SNR that
4.2: Typical GPS Receiver Architectures
55
Thermal Noise Floor
~ 20dB (Tr = 290K)
GPS C/A Code
111
000
000
111
000
111
000
111
000
111
000
111
000
111
GPS P-Code
000
111
000
111
000
111
000
111
000
111
00
11
000
111
000
111
00
11
000
111
000
111
00
11
000
111
000
111
000
111
000
111
00
11
000
111
000
111
000
111
000
111
000
111
00
11
000
111
000
111
00
11
00
11
000
111
000
111
000
111
000
111
000
111
000
111
00
11
000
111
000
111
00
11
00
11
000
111
000
111
000
111
000
111
00
11
000
111
000
111
00
11
000
111
2
MHz
000
111
000
111
000
111
00
11
000
111
000
111
00
11
000
111
000
111
00
11
000
111
20MHz 111
000
000
111
000
111
000
111
000
111
1.57542
GHz
000
111
000
111
000
111
000
111
000
111
000
111
Figure 4.1: The GPS L1 band signal spectrum.
occurs when a signal is \de-spread". For the GPS C/A code, the symbol rate is a
mere 50Hz. Thus, the processing gain is given by
Gp = 10log ffc = 43dB
b
(4.1)
where fb is the symbol rate of the C/A code, and fc is the chip rate.
The received signal power is typically {130dBm at the antenna of a GPS receiver.
If we assume that we are primarily interested in the 2-MHz main lobe of the C/A
code, the noise power in this 2-MHz bandwidth is simply given by kTB ,111dBm
(T = 290K). Hence, the received SNR at the antenna is about {19dB. Once the signal
from a given satellite is correlated with its PRBS code, the bandwidth is reduced
to only 100Hz. Thus, the postcorrelation SNR improves by the processing gain of
the system. So, with an antenna temperature of 290K and an otherwise noiseless
receiver, the post-correlation SNR would be about 24dB.
56
Chapter 4: A Global Positioning System Receiver Architecture
Dual-Conversion
2
PLL
- OR 1
Off-Chip
Single-Conversion
2
PLL
Off-Chip
Figure 4.2: Typical GPS receiver architectures.
4.2 Typical GPS Receiver Architectures
With the GPS signal spectrum in mind, consider two architectures that are widely
used in commercial GPS receivers today. These are illustrated in Figure 4.2.
The rst, and more widespread, is the dual conversion architecture. In this
approach, the GPS L1 band is translated to a moderate intermediate frequency (IF)
of approximately 100-200MHz where it is ltered o-chip before a second downconversion to a lower IF of around 1-10MHz. There, the signal is ltered a second
time before being amplied to a detectable level.
4.3: Opportunities for a Low-IF Architecture
57
The second approach is the single conversion architecture. As the name implies,
only a single IF is used, generally with o-chip ltering. The IF is directly sampled and then converted to baseband in a subsequent digital step. An alternative
approach sub-samples the IF directly to baseband.
Both architectures have several attributes in common. First, an o-chip LNA or
active antenna is generally postulated, permitting remote placement of the antenna
from the receiver itself. It is also common to have several o-chip lters, including
IF lters, phase-locked loop (PLL) loop lters and/or voltage-controlled oscillator
(VCO) tanks. The rst of these is generally dicult to integrate, although the loop
lter and tank circuitry are easily realized in integrated form. In addition, both
architectures use coarse quantization (1-2 bits) in the signal path, with a modest
AGC being required in the 2-bit case. Such coarse quantization is acceptable because
of the large processing gain of the GPS signal combined with its less-than-unity
received SNR. In fact, there is only a 3-dB loss associated with the use of one bit,
when compared to ne quantization. If two bits are used, the loss is only about
0.7dB [58].
The clear disadvantage of these architectures is that a number of o-chip components are required. The key barrier to integration is the need for high-frequency
(100-MHz) o-chip IF lters.
4.3 Opportunities for a Low-IF Architecture
One alternative would be to implement the receiver with a low intermediate frequency architecture. This architecture suers from the well-documented problem of
limited image rejection due to the need for stringent matching of in-phase (I) and
quadrature (Q) channels [55] [56]. This limitation makes the low-IF approach unsuitable for many applications. However, when we examine the GPS signal spectrum,
an opportunity emerges.
In consumer applications, where the C/A code main lobe is of primary concern,
we can take advantage of the narrow main lobe and relatively wide channel in a lowIF implementation. This concept is illustrated in Figure 4.3, where the L1 band has
58
Chapter 4: A Global Positioning System Receiver Architecture
Thermal Noise Floor
Channel Filter
Subsequent image
rejection suppresses
this sideband.
1111
0000
000
111
0000
1111
000
111
0000
1111
000
111
0000
1111
000
111
GPS C/A Code
0000
1111
000
111
0000
1111
000
111
0000
1111
000
111
0000
1111
000
111
GPS P-Code
0000
1111
000
111
0000
1111
000
111
0000
1111
000
111
0000
1111
000
111
000
111
00
11
00
11
000
111
0000
1111
000
111
000
111
00
11
00
11
000
111
0000
1111
000
111
000
111
00
11
00
11
000
111
000
111
00
11
00
11
000
111
0000
1111
000
111
000
111
00
11
00
11
000
111
00
11
000
111
000
111
00
11
000
111
00
11
00
11
000
111
0000
1111
000
111
000
111
00
11
00
11
000
111
000
111
00
11
00
11
00
11
000
111
00
11
00
11
000
111
00
11
000
111
000
111
00
11
000
111
00
11
00
11
000
111
0000
1111
000
111
000
111
00
11
00
11
000
111
000
111
00
11
00
11
00
11
000
111
00
11
00
11
000
111
00
11
000
111
000
111
00
11
000
111
00
11
00
11
000
111
0000
1111
000
111
000
111
00
11
00
11
00
11
000
111
00
11
00
11
000
111
2
MHz
000
111
00
11
00
11
000
111
0000
1111
000
111
000
111
00
11
00
11
000
111
0000
1111
000
111
000
111
00
11
00
11
000
111
0000
1111
000
111
000
111
00
11
00
11
000
111
0000
1111
000
111
0000
1111
000
111
0000
1111
000
111
0000
1111
000
111
-12 MHz -8 MHz
-2 MHz
2 MHz
8 MHz 12 MHz
0000
1111
000
111
0000
1111
000
111
0000
1111
000
111
0000
1111
000
111
0000
1111
000
111
0000
1111
000
111
0000
1111
000
111
Figure 4.3: The GPS L1 band signal spectrum when downconverted to a 2-MHz
intermediate frequency.
been downconverted to an intermediate frequency of 2MHz. This choice of IF causes
the image signal to lie within the GPS band. Thus, the image signal power is always
comparable to the desired signal power and the required image rejection is only
about 10dB, which is easily attained with ordinary levels of component matching.
In addition, the spectrum from 3MHz to 8MHz can be used as a transition band for
the active IF lter. This permits a reduction of the required lter order that will
lead to improved dynamic range for a given lter power consumption.
These considerations make the low-IF architecture an attractive choice for a
highly integrated GPS receiver.
4.4 GPS Receiver Architecture
A detailed block diagram of a low-IF GPS receiver is shown in Figure 4.4. The
complete analog signal path is implemented, including the LNA, mixers, I and Q
4.4: GPS Receiver Architecture
1.57542GHz
59
2.048MHz
I[n]
Q[n]
Band
Gap
π/2
Signal Path
PLL
fref =157.3374MHz
fLO =1.573374GHz
APD
Figure 4.4: Block diagram of the CMOS GPS receiver.
local oscillator (LO) drivers, IF ampliers (IFAs), active lters, limiting ampliers
(LAs) and 1-bit analog-to-digital (A/D) converters. Additionally included is an
on-chip PLL comprising a VCO, loop-lter, charge pump and phase detectors. The
prescaler is eliminated in favor of aperture phase detectors (APDs) which only operate
at the reference rate, thus reducing power consumption and switching noise. The
PLL is described in detail elsewhere [59].
Most of the receiver is biased with two on-chip bandgap references, with the
exception of the LNA and the I and Q LO drivers. The LNA is biased with a separate
self-referenced constant-gm bias network to eliminate any possible interaction with
other blocks through parasitic bias coupling and to stabilize its gain and input match.
Similarly, the I and Q drivers are biased by another constant-gm network for better
regulation of the I and Q phase and amplitude.
60
Chapter 4: A Global Positioning System Receiver Architecture
4.4.1 Image Noise Cancellation
As in the familiar Weaver SSB modulator [36], the low-IF architecture depends
on image cancellation to suppress the noise of the unwanted sideband. In cases
where the image consists entirely of noise, the cancellation depends on the crosscorrelation of the noise signals in the two channels. However, the limiters in the signal
path will reduce the cross-correlation of the two noise processes, thereby drastically
reducing the amount of cancellation. An analysis of this eect is presented in detail
in Appendix A. This reduction in cross-correlation leads one to ask whether an
image reject architecture makes sense when only 1-bit quantization is used in the I
and Q signal paths.
When a low intermediate frequency is used, the noise powers in the signal band
and the image band are equal. In this special case, it can be shown that the noise
signals at the outputs of the limiters are uncorrelated so that subsequent downconversion and summation leads to a 3-dB SNR improvement compared to the SNR in
each channel. Because this is the same improvement provided by an image-reject
architecture with ne quantization, we conclude that, in this special case, the benet
of image noise rejection can be achieved despite coarse quantization in the signal
path. A detailed mathematical analysis of the cross-correlation between the two
channels at the limiter outputs is also presented in Appendix A for completeness.
4.4.2 Receiver Gain Plan
For the architecture of Figure 4.4, the on-chip active lter has the narrowest dynamic
range of all the signal-path elements. The active circuitry used to implement the
inductive elements in the lter contributes noise and distortion, making the dynamic
range much narrower than an equivalent o-chip passive lter. In particular, the
noise gure of the lter is quite high (about 18dB). Because noise performance is
critical in the GPS system, the receiver gain plan is tailored to suppress the active
lter's contribution to the receiver noise gure.
To achieve acceptable noise performance without sacricing too much dynamic
range, the amplier stages preceding the lter provide just enough power gain to
4.4: GPS Receiver Architecture
Table 4.1: Receiver Gain Plan
Specication
LNA Mixer IFA Filter
Avail. Gain (dB) 16
{4
16 {3
Output Z (k
)
0.4 0.4
2
1
Noise Figure (dB) 2.4
6
7
18
OIP3 (dBm)
7
5
10
0
Total NF (dB)
2.4 2.5 2.8 2.9
ONoise (dBm)
{94 {98 {81 {84
For Ps ={53dBm:
OIM3 (dBm)
{125 {127 {95 {84
SNR (dB)
57
57
56 56
SDR (dB)
88
86
70 56
61
LA
78
60
8
{
2.9
{
{
{
{
manage the high noise gure of the lter. Table 4.1 shows the distribution of
gain, noise gure and third-order intermodulation distortion throughout the receiver.
From this table, it is clear that the on-chip lter is the dynamic range limiting block
because it has the largest noise gure and the smallest output third-order intercept
point (OIP3). Because of the dynamic range limitation imposed by the active lter,
the lter design problem is treated in detail in Chapter 7.
Table 4.1 also demonstrates that the system noise gure is dominated by the
noise gure of the low-noise amplier. For the system noise gure to be less than
3dB, the LNA noise gure must be less than 2.5dB. It is challenging to achieve this
LNA noise gure in a 0.5m CMOS technology at 1.6GHz without consuming an
unacceptable amount of power. Accordingly, Chapter 5 considers how to design the
LNA for minimum noise gure with a given power consumption.
The frequency mixer is another important block in this architecture. It must
have a relatively low noise gure and must not limit the linearity of the receiver.
Note that the mixer in Table 4.1 actually has a conversion loss of about 4dB. By
allowing for conversion loss in the architecture, a simple pair of voltage switches can
be used to implement the mixer. This choice has the welcome benet that the mixer
core consumes no static power. The design of the mixer is the subject of Chapter 6.
62
Chapter 4: A Global Positioning System Receiver Architecture
Finally, the gain plan table gives us an indication of the peak SFDR of the receiver
system. At {53-dBm available source power, the third-order intermodulation (IM3)
products at the lter output have a power that is approximately equal to the noise
power in a 2-MHz bandwidth. Thus, the signal-to-noise ratio is equal to the signal-todistortion ratio. This is the condition for peak spurious-free dynamic range (SFDR),
which is about 56dB.
4.5 Summary
In summary, this chapter has presented a new architecture for a GPS receiver that is
particularly well suited for integration. By taking advantage of the structure of the
GPS L1-band, a low-IF receiver benets from relaxed image rejection requirements
and relaxed lter specications. With relaxed lter order, an active lter can be
used without severely compromising dynamic range. Nonetheless, the lter is still
the dynamic-range limiting receiver block and must be given special attention to
ensure optimized system performance.
The chapters that follow examine the LNA, mixer and lter problems in detail.
Throughout, the unifying goal is the implementation of a low-power receiver system.
Thus, architectural and design decisions are driven primarily by the need for powereciency in every receiver block. We begin by considering the power-constrained
optimization of noise performance of the front-end low-noise amplier.
Chapter 5
Low-Noise Amplication in CMOS
at Radio Frequencies
T
HE rst block in most wireless receivers is the low-noise amplier (LNA). It
is responsible for providing signal amplication while not degrading signal-tonoise ratio, and its noise gure sets a lower bound on the noise gure of the entire
system. It is sobering to note that received GPS signal power levels at the antenna
are around -130dBm and this low level degrades further in the presence of physical
obstructions such as buildings and trees. Hence, a good amplier is also critical for
enabling robust performance in obstructed environments.
One possible threat to low noise operation is the well-documented, but relatively unappreciated, excess thermal noise exhibited by sub-micron CMOS devices
[2][60][61][62]. This noise is believed to arise from hot electron eects in the presence of high electric elds. Despite this excess noise, recent work has demonstrated the viability of CMOS low noise ampliers (LNA's) at frequencies around
900MHz [63][64][65].
To provide some background, Section 5.1 presents a review of recent LNA work in
various technologies in the 900MHz{2GHz frequency range. A thorough mathematical treatment of the LNA architecture that we have chosen is presented in Section
5.2. We consider in particular the eect of induced gate noise in CMOS, which is
rarely cited but nonetheless of fundamental importance in establishing the limits of
63
64
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
Zin
Zin
Zin
Zin
(a)
(b)
(c)
(d)
Figure 5.1: Common LNA Architectures. (a) Resistive Termination. (b) 1=gm
Termination. (c) Shunt-Series Feedback. (d) Inductive Degeneration.
achievable noise performance. Section 5.3 discusses noise gure optimization techniques that permit selection of device geometries to maximize noise performance for
a specied gain or power dissipation. In addition, numerical examples, employing
the analytical techniques developed in this chapter, illustrate some of the salient
features of the LNA architecture.
5.1 Recent LNA Research
Many authors have investigated LNA techniques in the 900MHz{2GHz frequency
range. Table 5.1 summarizes the results of several recent studies dating from 1991{
1998. This table has representative results from various process technologies and
architectures. While the literature is full of examples of LNA work in GaAs and
bipolar technologies, there are relatively few examples of CMOS studies. In addition,
despite a long history of LNA work in GaAs and bipolar technologies, these papers
report a wide variety of noise gures, power dissipations, and gains. The remarkable
spread in published results seems to suggest that a systematic basis for the design of
these ampliers has not been elucidated. However, by examining these results from
an architectural viewpoint, some order emerges.
In the design of low noise ampliers, there are several common goals. These
include minimizing the noise gure of the amplier, providing gain with sucient
5.1: Recent LNA Research
65
Table 5.1: Summary of Recent LNA Results
Author [Ref.]
Chang et al. [66]
Karanicolas et al. [63]
Sheng et al. [65]
Rofougaran et al. [64]
Shin et al. [67]
Vanoppen et al. [68]
Huang et al. [69]
Janssens et al. [70]
Benton et al. [71]
Cio [72]
Nakatsugawa et al. [73]
Heaney et al. [74]
Imai et al. [75]
Sheng et al. [76]
Meyer et al. [77]
Kobayashi et al. [78]
a
b
NF
(dB)
6.0b
2.2
7.5
3.5
5.3
2.2
1.9
3.3
2.7
2.2
2.2
2.0
1.5
2.5
5.7
2.2
2.9
Gain
(dB)
14
15.6
11.0
22
20
17
16
9
28
17.4
19.6
12.2
14.5
11.5
7.8
16
17.5
IP3/-1dBa
(dBm)
na / na
12.4 / na
na / na
na / na
11 / na
na / na
9 / -4
10 / na
na / 8.5
na / na
6 / -3
5.1 / na
11.2 / -1.1
9 / na
23.9 / 11
6 / -4
na / na
Power
(mW)
7
20
36
27
41
1.8
22
10
208
10
10
2
12
14
115
40
480
f0
(GHz)
0.75
0.9
0.9
0.9
0.9
0.9
0.9
0.9
1.6
1.6
1.0
1.9
1.9
1.6
1.0
0.9
1.0
Architecture
Technology
Year
R-Term.
L-Degen.
Shunt-Ser. FB
1=gm -Term.
1=gm -Term.
L-Degen.
L-Degen.
L-Degen.
Shunt-Ser. FB
L-Degen.
L-Degen.
L-Degen.
L-Degen.
L-Degen.
Shunt-Ser. FB
L-Degen.
1=gm -Term. &
Shunt-Ser. FB
2m CMOS
0.5m CMOS
1m CMOS
1m CMOS
0.9m CMOS
0.5m CMOS
0.25m CMOS
0.5m CMOS
GaAs FET
1m GaAs FET
1m GaAs FET
0.3m GaAs FET
1m GaAs FET
0.3m GaAs FET
GaAs HBT
QUBiC BiCMOS
GaAs HBT
1993
1996
1996
1996
1997
1997
1998
1998
1992
1992
1993
1993
1994
1991
1994
1994
IP3 / -1dB compression point are output-referred.
Neglects contribution of termination resistors. See text for discussion.
linearity | typically measured in terms of the third-order intercept point, IP3 |
and providing a stable 50
input impedance to terminate a lter or an unknown
length of transmission line which delivers signal from the antenna to the amplier.
A good input match is particularly critical when a preselect lter precedes the LNA
because such lters are often sensitive to the quality of their terminating impedances.
The additional constraint of low power consumption which is imposed in portable
systems further complicates the design process.
With these goals in mind, we will rst focus on the requirement of providing
a controlled input impedance. The architectures in Table 5.1 can be divided into
four distinct approaches, illustrated in simplied form in Figure 5.1. Each of these
architectures may be used in a single-ended form (as shown), or in a dierential form.
Note that dierential forms require the use of a balun or similar element to transform
the single-ended signal from the antenna into a dierential signal. Practical baluns
introduce extra loss which adds directly to the noise gure of the system.
The rst technique uses resistive termination of the input port to provide a 50
impedance. This approach is used in its dierential form by Chang et al. [66], for
example. Unfortunately, the use of real resistors in this fashion has a deleterious
66
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
eect on the amplier's noise gure. The noise contribution of the terminating
resistors is neglected in that work because an antenna would be mounted directly on
the amplier, perhaps obviating the need for input matching. Hence, the reported
noise gure of 6dB corresponds to a hypothetical \terminationless" amplier.
In general, however, the LNA is driven by a source that is located some distance
away, and one must account for the inuence of the terminating resistor. Specically, we require that the amplier possess a reasonably stable input impedance of
approximately 50
. To evaluate the ecacy of simple resistive input termination,
suppose that a given LNA employing resistive termination has an available power
gain of Ga and an available noise power at the output Pna ;i due to internal noise
sources only; Pna ;i is, to rst order, independent of the source impedance. Then, the
noise gure is found to be1
Total output noise
F =4 Total output
noise due to the source
Pna ;i
i + kTBGa
= 2 + kTBG
= 1 + Pna ;kTBG
a
a
(5.1)
where B is the bandwidth over which the noise is measured. When the amplier
termination is removed, the noise gure expression becomes, approximately,
Pna ;i
F = 1 + 4kTBG
a
(5.2)
where we have assumed a high input impedance relative to the source. From (5.1)
and (5.2), we may surmise that a \terminationless" amplier with a 6dB noise gure
would likely possess an 11.5dB noise gure with the addition of the terminating
resistor. Two eects are responsible for this sharp degradation in noise gure. First,
the added resistor contributes its own noise to the output equal to the contribution
of the source resistance. This additional noise results in a factor of two dierence
in the rst terms of (5.1) and (5.2). Second, the input is attenuated, leading to
the factor of four dierence in the second terms of (5.1) and (5.2). The large noise
1
Evaluated at T = 290K .
5.1: Recent LNA Research
67
penalty resulting from these eects therefore makes this architecture unattractive
for the more common situation where a good input termination is desired.
A second architectural approach, shown in Figure 5.1(b), uses the source or
emitter of a common-gate or common-base stage as the input termination. A simplied analysis of the 1=gm-termination architecture, assuming matched conditions,
yields the following lower bounds on noise gure for the cases of bipolar and CMOS
ampliers:
Bipolar:
CMOS:
F = 23 = 1:76dB
F = 1 + 53 = 2:2dB
where
=4 ggm :
d0
(5.3)
In the CMOS expressions, is the coecient of channel thermal noise, gm is the
device transconductance, and gd0 is the zero-bias drain conductance. For longchannel devices, = 2=3 and = 1. The bipolar expression neglects the eect of
base resistance in bipolar devices, while the value of 2.2dB in the CMOS expression
neglects both short-channel eects ( < 1) and excess thermal noise due to hot
electrons ( > 2=3). Indeed, for short-channel MOS devices, can be signicantly
greater than one, and will be less than one. Accordingly, the minimum theoretically achievable noise gures tend to be around 3dB or greater in practice for this
architecture.
Figure 5.1(c) illustrates yet another topology, which uses resistive shunt and series feedback to set the input and output impedances of the LNA. This approach is
taken in [71], [76] and as the second stage in [78]. It is evident from Table 5.1 that
ampliers using shunt-series feedback often have signicantly higher power dissipation compared to narrowband ampliers with similar noise performance. Intuitively,
the higher power is partially due to the fact that shunt-series ampliers of this type
are naturally broadband, and hence techniques which reduce the power consumption
through L-C tuning are not applicable. For GPS applications, a broadband front end
68
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
vrg2
Rg
Cgs
Cgd
gm vgs
i2d
ro
Figure 5.2: The standard CMOS noise model.
is not required and it is additionally desirable to make use of narrowband techniques
to reduce power and reject out-of-band interfering signals and noise. Furthermore,
the shunt-series architecture requires on-chip resistors of reasonable quality, which
are generally not available in CMOS technologies. For these reasons, the shunt-series
feedback approach is not pursued in this work.
The fourth architecture, and the one that we have used in this design, employs
inductive source or emitter degeneration as shown in Figure 5.1(d) to generate a real
term in the input impedance [79]. Tuning of the amplier input becomes necessary,
making this a narrow band approach. However, this requirement is not a limitation
for a GPS receiver.
Note that inductive source degeneration is the most prevalent method used for
GaAs MESFET ampliers. It has also been used in CMOS ampliers recently at
900MHz [63]. As we will see, the proliferation of this architecture is no accident; it
oers the possibility of achieving the best noise performance of any architecture.
5.2 LNA Architectural Analysis
We will now pursue a careful analysis of the architecture in Figure 5.1(d) to establish
clearly the principle of operation and the limits on noise performance. A brief review
of the standard CMOS noise model will facilitate the analysis.
5.2.1 Standard MOS Noise Model
The standard CMOS noise model is shown in Figure 5.2. The dominant noise source
5.2: LNA Architectural Analysis
69
in CMOS devices is channel thermal noise. This source of noise is commonly modeled
as a shunt current source in the output circuit of the device. The channel noise is
white with a power spectral density given by
i2d = 4kTg
d0
f
(5.4)
where gd0 is the zero-bias drain conductance of the device and is a bias-dependent
factor that, for long-channel devices, satises the inequality
2 1:
3
(5.5)
The value of 2=3 holds when the device is saturated, and the value of 1 is valid
when the drain-source voltage is zero. For short-channel devices, however, does
not satisfy Equation (5.5). In fact, can be much greater than 2/3 for short-channel
devices operating in saturation [2][62]. For 0.7-m channel lengths, may be as high
as 2{3, depending on bias conditions [2].
This excess noise may be attributed to the presence of hot electrons in the channel. The high electric elds in sub-micron MOS devices cause the electron temperature, Te, to exceed the lattice temperature. The excess noise due to carrier heating
was anticipated by van der Ziel as early as 1970 [80].
An additional source of noise in MOS devices is the noise generated by the distributed gate resistance [81]. This noise source can be modeled by a series resistance
in the gate circuit and an accompanying white noise generator. By interdigitating
the device, the contribution of this source of noise can be reduced to insignicant
levels. For noise purposes, the eective gate resistance is given by [82]
Rg = R3n22WL
(5.6)
where R2 is the sheet resistance of the polysilicon, W is the total gate width of the
device, L is the gate length, and n is the number of gate ngers used to lay out the
device. The factor of 1=3 arises from a distributed analysis of the gate, assuming
70
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
that each gate nger is contacted only at one end. By contacting at both ends,
this term reduces to 1=12. In addition, this expression neglects the interconnect
resistance used to connect the multiple gate ngers together. The interconnect can
be routed in a metal layer that possesses signicantly lower sheet resistance, and
hence is easily rendered insignicant.
Though playing a role similar to that of base resistance in bipolar devices, the
gate resistance is much less signicant in CMOS because it can be minimized through
interdigitation without the need for increased power consumption, unlike its bipolar
counterpart. Its signicance is further reduced in silicided CMOS processes which
possess a greatly reduced sheet resistance, R2.
An additional source of noise in CMOS devices is the back-gate epitaxial resistance [67], which can result in an apparent increase in , the coecient of drain
noise. To evaluate the magnitude of the epitaxial resistance noise, we can model
the epitaxial layer as a resistance in series with the bulk terminal of the device [83].
There is a noise voltage associated with this resistance which, together with the
drain current noise of the device, produces a total drain current noise of
i2d = 4kT g + g2 R = 4kT g
d0
e d0
mb epi
f
(5.7)
e + gmbg Repi :
(5.8)
where
2
d0
For the 0.5-m technology used in this work, and for the particular device size and
layout geometry used in the LNA presented in Chapter 8,
0:09 gmb Repi 0:2:
gd0
2
(5.9)
The lower bound uses the approach outlined in [83] for estimating Repi , while the
upper bound uses a much more conservative approach based on a trapezoidal approximation for the epitaxial spreading resistance [84], assuming that substrate contacts
5.2: LNA Architectural Analysis
Zin
71
Lg
Vbias
M2
M1
Ls
Figure 5.3: Common-source input stage.
are distant from the device. With closely-spaced substrate contacts, this number will
be reduced even further. Thus, the epitaxial resistance is of secondary importance
in this case and will be ignored in the analysis that follows.
5.2.2 LNA Architecture
We now proceed to the analysis of the LNA architecture using the standard CMOS
noise model. Figure 5.3 illustrates the input stage of the LNA. A simple analysis of
the input impedance shows that
Zin
= s(Ls + Lg ) + 1 + gm1 Ls
sCgs
Cgs
!T Ls
(at resonance ):
(5.10)
If the eect of the gate-to-drain overlap capacitance is included, then, at resonance
Zin !T LCsgd = !T;e Ls:
1 + 2 Cgs
(5.11)
At the series resonance of the input circuit, the impedance is purely real and proportional to Ls. By choosing Ls appropriately, this real term can be made equal to 50
.
For example, if fT is 10GHz, a 50
impedance requires only 800pH for Ls. This
72
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
Vdd
Lg
vl2
Rl
vrg2 Rg
Iout
M1
Rs
i2d
Ls
vs2
Figure 5.4: Equivalent circuit for input stage noise calculations.
small amount of inductance can easily be obtained with a single bondwire or on-chip
spiral inductor. The gate inductance Lg is used to set the resonance frequency once
Ls is chosen to satisfy the criterion of a 50
input impedance.
The noise gure of the LNA can be computed by analyzing the circuit shown
in Figure 5.4. In this circuit, Rl represents the series resistance of the inductor
Lg , Rg is the gate resistance of the NMOS device, and i2d represents the channel
thermal noise of the device. Analysis based on this circuit neglects the contribution
of subsequent stages to the amplier noise gure. This simplication is justiable
provided that the rst stage possesses sucient gain, and permits us to examine in
detail the salient features of this architecture. Note that the overlap capacitance,
Cgd , has also been neglected in the interest of simplicity. The use of a cascoded rst
stage helps to ensure that this approximation will not introduce serious errors.
Recall that the noise gure for an amplier is dened as2
Total output noise
F =4 Total output
:
noise due to the source
(5.12)
To evaluate the output noise when the amplier is driven by a 50
source, we
rst evaluate the transconductance of the input stage. With the output current
2
Evaluated at a source temperature T = 290K .
5.2: LNA Architectural Analysis
73
proportional to the voltage on Cgs , and noting that the input circuit takes the form
of a series-resonant network,
Gm = gm1 Qin = ! C (Rgm1+ ! L )
0 gs s
T s
!
!
T
T
=
=
!
L
2
!
s
T
0 Rs
!0Rs 1 + Rs
(5.13)
where Qin is the eective Q of the amplier input circuit. In this expression, which
is valid at the series resonance !0, Rl and Rg have been neglected relative to the
source resistance, Rs. Perhaps surprisingly, the transconductance of this circuit
at resonance is independent of gm1 (the device transconductance) as long as the
resonant frequency is maintained constant. If, at constant bias voltages, the width
of the device is adjusted, the transconductance of the stage will remain the same
as long as Lg is adjusted to maintain a xed resonant frequency. This result is
intuitively satisfying, for as the gate width (and thus gm1 ) is reduced, Cgs is also
reduced, resulting in an increased Qin such that the product of gm1 and Qin remains
xed.
Using (5.13), the output noise power density due to the 50
source is
Sa ;src (!0) = Ssrc (!0 )G2m ;e =
4kT!T2
2 :
!
L
2
s
T
!0 Rs 1 + Rs
(5.14)
In a similar fashion, the output noise power density due to Rl and Rg can be expressed as
2
Sa ;Rl ;Rg (!0) = 4kT (Rl + Rg )!T2 :
!02Rs2 1 + !RT Ls s
(5.15)
Equations (5.14) and (5.15) are also valid only at the series resonance of the circuit.
The dominant noise contributor internal to the LNA is the channel current noise
of the rst MOS device. Recalling the expression for the power spectral density of
74
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
this source from (5.4), one can derive that the output noise power density arising
from this source is
i2d
Sa ;id (!0 ) = f
1 + !TRLs s
2
= 4kTgd02 :
1 + !TRLs s
(5.16)
The total output noise power density is the sum of (5.14){(5.16). Assuming a 1Hz
bandwidth and substituting these into Equation (5.12) yields
!0
g
F = 1 + RRl + R
+
g
d0 Rs
!T
s Rs
2
(5.17)
which is the noise gure of the LNA.
This equation for noise gure reveals several important features of this LNA architecture. Note that the dominant term in (5.17) is the last term, which arises from
channel thermal noise. Surprisingly, this term is proportional to gd0 . So, according
to this expression, by reducing gd0 without modifying !T , we can simultaneously
improve noise gure and reduce power dissipation. We can achieve this result by
scaling the width of the device while maintaining constant bias voltages on its terminals and leaving the channel length unchanged. This scaling is consistent with
the condition of constant !T , which depends only on the bias voltages on the device.
Recall, however, that this expression assumes that the amplier is operated at the
series resonance of its input circuit. So, a reduction in gd0 (and, hence in Cgs) must
be compensated by an increase in Lg to maintain a constant resonant frequency.
So, better noise performance and reduced power dissipation can be obtained by
increasing the Q of the input circuit resonance.
By applying device scaling in this fashion to improve noise performance, the
linearity of the amplier will tend to degrade due to increased signal levels across
Cgs . However, short-channel MOS devices operating in velocity saturation have a
relatively constant transconductance with sucient gate overdrive voltage. This
property is one advantage of implementing LNA's with MOS devices.
5.2: LNA Architectural Analysis
+
Vg
,
S
75
i2g
G
Induced Current
D
+
Vd
,
Noisy Channel
Figure 5.5: Induced gate eects in MOS devices.
A second important feature in (5.17) is the inverse dependence on !T2 . Continued improvements in technology will therefore naturally lead to improved noise
performance at a given frequency of operation.
Careful examination of (5.17) reveals a curious feature, however. Although nite
inductor Q's will limit the amount of improvement practically available through
device scaling, Equation (5.17) does not predict a fundamental minimum for F . The
implication is that a 0dB noise gure may be achieved with zero power dissipation,
and this result simply cannot be true. Yet, the expression follows directly from the
MOS noise model that we have assumed.
The conclusion can only be that our noise model is incomplete.
5.2.3 Extended MOS Noise Model
To understand the fundamental limits on noise performance of this architecture, we
must turn our attention to induced gate current noise in MOS devices. Although absent from most texts on CMOS circuit design, gate noise is given detailed treatment
by van der Ziel and others [80] [1] [85] [86] [87].
Figure 5.5 shows the cross-section of a MOS device. If the device is biased so
that the channel is inverted, uctuations in the channel charge will induce a physical
current in the gate due to capacitive coupling. This noise current can be (and has
76
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
+
vgs
,
i2g
gg
+
vg2
rg
Cgs vgs
Cgs
,
(b)
(a)
Figure 5.6: Revised gate circuit model including induced eects. (a) Standard representation, as found in [1]. (b) The equivalent, but more intuitive, Thevenin representation.
been) measured [85], but it is not included in the simple MOS noise model that we
have used in the previous section.
A companion eect that occurs at very high frequencies arises due to the \distributed" nature of the MOS device. At frequencies approaching !T , the gate
impedance of the device exhibits a signicant phase shift from its purely capacitive value at lower frequencies. This shift can be accounted for by including a real
conductance, gg , in the gate circuit. Note that this conductance is distinct from
the polysilicon resistance and is also distinct from the real term that occurs due to
interaction of Cgd with gm3 .
A simple gate circuit model that includes both of these eects is shown in Figure
5.6(a). A shunt noise current i2g and a shunt conductance gg have been added.
Mathematical expressions for these sources are [1]4
i2g
f = 4kTgg
(5.18)
A real conductance with a form similar to gg is generated in cascoded ampliers due to the feedback provided by Cgd . This distinctly dierent eect is also signicant at frequencies approaching
!T .
4 Our notation diers slightly from that found in [1], in which is used in place of . The use
of avoids confusion in cases where represents n Cox W=L, as is the practice in some texts on
MOS devices.
3
5.2: LNA Architectural Analysis
77
!2Cgs2
gg = 5g
d0
(5.19)
where is the coecient of gate noise, classically equal to 4=3 for long-channel
devices. Equations (5.18) and (5.19) are valid when the device is operated in saturation.
Some observations about (5.18) and (5.19) are warranted. Note that the expression for the gate noise power spectral density takes a form similar to that of
Equation (5.4), which describes the drain noise power spectral density. However, in
the gate noise expression, gg is proportional to !2, and hence the gate noise is not
a white noise source. Indeed, it is better described as a \blue" noise source due to
its monotonically increasing power spectral density. It seems mysterious that the
gate and drain noise terms have dierent types of power spectra, given their common progenitor. The mystery is somewhat articial, however, because the circuit
of Figure 5.6(a) can be cast into an equivalent Thevenin representation as shown in
Figure 5.6(b) where
vg2
f = 4kTrg
(5.20)
rg = 5g1 :
(5.21)
d0
We observe that vg is now a white noise source proportional to a constant resistive
term, rg . This formulation of the gate circuit seems more intuitively appealing
because the frequency dependence has been removed for both terms. Figures 5.6(a)
and 5.6(b) are interchangeable for frequencies where the Q of Cgs is suciently large,
i.e.,
5gd0 1
QCgs = !C
gs
(5.22)
78
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
or, equivalently,
! 5Cgd0 = 5!T
gs
(5.23)
where was dened in Equation (5.3) and is always less than one. This condition
is automatically satised in all cases of practical interest.
In addition, we can expect the coecient of gate noise, , to exhibit a dependence
on electric eld just as its counterpart, . To our knowledge, though, there are no
published studies of the high-eld behavior of .
The presence of gate noise complicates the analysis of F signicantly. The gate
noise is partially correlated with the drain noise, with a complex correlation coecient given by [1]
c = qig id 0:395j
i2g i2d
(5.24)
where the value of 0:395j is exact for long-channel devices. The correlation can be
treated by expressing the gate noise as the sum of two components, the rst of which
is fully correlated with the drain noise, and the second of which is uncorrelated with
the drain noise. Hence, the gate noise is re-expressed as
i2g
2
(1 , jcj2}) + |4kTg
g jcj :
{z }
f = 4|kTgg{z
Uncorrelated
(5.25)
Correlated
Because of the correlation, special attention must be paid to the reference polarity
of the correlated component. The value of c is positive for the polarity shown in
Figure 5.6(a).
Having established this additional source of noise in MOS devices, we are now
in a position to re-evaluate the noise gure of the LNA. As we will see, the presence
of gate noise establishes a lower bound on the achievable noise performance of the
amplier.
5.2: LNA Architectural Analysis
79
Vdd
Lg
Rs
vl2
Rl
vrg2
i2out
Rg
i2g;c
i2g;u
Cgs
+
vgs
gm vgs
,
i2d
Ls
vs2
Figure 5.7: Revised small-signal model for LNA noise calculations.
5.2.4 Extended LNA Noise Analysis
To evaluate the noise performance of the LNA in the presence of gate noise eects,
we will employ the circuit of Figure 5.7. In this circuit, we have neglected the
eect of gg under the assumption that the gate impedance is largely capacitive at
the frequency of interest. Equation (5.23) species the condition under which this
approximation holds. The gate noise has been subdivided into two parts. The rst,
i2g;c, represents the portion of the total gate noise that is correlated with the drain
noise. The second, i2g;u, represents the portion that is uncorrelated with the drain
noise.
With the revised small-signal model in mind, we can derive the noise gure of
the LNA. A close examination of Figure 5.7 allows us to anticipate the result of
our analysis. As the Q of the input circuit is increased from zero, the noise gure
will tend to improve in accordance with the earlier expression for F . However, the
impedance at the gate of the device increases simultaneously, and hence the gate
current noise will begin to dominate at some point. A minimum noise gure will
thus be achieved for a particular input Q.
To analyze the circuit mathematically, we can draw on Equations (5.14){(5.16)
from the previous section for the drain noise and resistive losses. However, the
amplitudes of the correlated portion of the gate noise and the drain noise must be
80
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
summed together before the powers of the various contributors are summed. Doing
so yields a term representing the combined eect of the drain noise and the correlated
portion of the gate noise
Sa;id ;ig;c (!0 ) = Sa;id (!0) = 4kTgd02
1 + !RT Ls s
(5.26)
where,
"
s
#2
2
2
2 + 1 + jcj j
c
j
= 5
5 :
(5.27)
Note that if ! 0, then ! 1 and Equation (5.26) then reduces to Equation (5.16).
The last noise term is the contribution of the uncorrelated portion of the gate
noise. This contributor has the following power spectral density:
Sa;ig;u (!0) = Sa;id (!0 ) = 4kTgd02
1 + !TRLs s
(5.28)
= (1 , jcj2)(1 + Q2s )
5
(5.29)
Qs = !0 (LRs + Lg ) = ! R1 C :
(5.30)
where,
2
s
0 s gs
We observe that all of the noise terms contributed by the rst device, M1 , are
proportional to Sa;id (!0), the contribution of the drain noise. Hence, it is convenient
to dene the contribution of M1 as a whole as
Sa;M1 (!0) = Sa;id (!0) = 4kTgd02
1 + !TRLs s
(5.31)
5.3: LNA Design Considerations
81
where, after some slight simplication,
s
2 2
2
= + = 1 + 2jcj 5 + 5 (1 + Qs ):
(5.32)
With Equations (5.31) and (5.32), it is clear that the eect of induced gate noise
is to modify the noise contribution of the device in proportion to . It follows
directly that
g
+ gd0 Rs !0
F = 1 + RRl + R
!T
s Rs
2
(5.33)
where is dened as in (5.32). By factoring out Qs from the expression for , and
noting that
gd0 Qs = gm ! R1 C = !!TR
0 s gs
0 s
(5.34)
we can re-express F as
g !0
F = 1 + RRl + R
+
:
s Rs Qs !T
(5.35)
To understand the implications of this new expression for F , we observe that
includes terms which are constant and terms which are proportional to Q2s . It
follows that (5.35) will contain terms which are proportional to Qs as well as inversely
proportional to Qs. Therefore, a minimum F exists for a particular Qs , as argued
earlier. Selection of the optimum Qs forms the subject of the next section.
5.3 LNA Design Considerations
The analysis of the previous section can now be drawn upon in designing the LNA.
Of primary interest is insight into picking the appropriate device width and bias
point to optimize noise performance given specic objectives for gain and power
dissipation.
82
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
To select the width of M1, we turn to Equations (5.32) and (5.35). Note that all
of the terms are well-dened in these expressions, except for and . Because and both depend on drain bias in an unspecied fashion, it is dicult to account properly
for their contributions. To surmount this diculty, we adopt the assumption that
although each may be a function of bias, the ratio can be expected to show less
variation because and will likely have similar dependence on bias, given their
common progenitor. The reader is cautioned, however, that this assumption is
somewhat arbitrary; it is necessary because the detailed high-eld behavior of and is presently unknown. Modications may be required once further research
yields information about these coecients. The analysis which follows is suciently
general, however, that it can be easily adapted to accommodate new information on
the high-eld natures of and .
In preparation for optimizing the noise performance of the LNA, it will be useful
to formulate the quantities , !T , and Qs in terms of the gate overdrive voltage of
M1 .
5.3.1 A Second-Order MOSFET Model
To quantify these terms, a simple second-order model of the MOSFET transconductance can be employed which accounts for high-eld eects in short-channel devices.
Assume that Id has the form [3]
2
Id = WCox sat V +VodL"
od
sat
(5.36)
Vod = Vgs , VT
(5.37)
with
where Cox is the gate oxide capacitance per unit area, sat is the saturation velocity,
and "sat is the velocity saturation eld strength, dened as the lateral electric eld
5.3: LNA Design Considerations
83
for which the mobility drops to one half of its low-eld value. We can dierentiate
this expression to determine the transconductance, yielding
@Id = C W V 1 + =2
gm = @V
e ox
L od | (1 +{z)2 }
gs
(5.38)
with the denition that
Vod
= L"
sat
(5.39)
where e is the eld-limited electron mobility. The term in square braces is itself.
Having established an expression for Id , we can formulate the power consumption
of the amplier as follows,
2
V
od
PD = Vdd Id = Vdd WCox sat V + L" :
od
sat
(5.40)
Note that the power dissipation is proportional to the device width, W . Another
quantity which depends directly on W is Qs, which has been specied in Equation
(5.30). Combining this equation with (5.40), and noting that Cgs = 23 WLCox , we
can relate Qs to PD with
2
Qs = PP0 1 + (5.41)
P0 = 23 Vdd!satR"sat :
(5.42)
D
where
0 s
Note that for the purposes of our analysis, P0 is a constant determined solely by
physical technological parameters (sat and "sat ) and design target specications
(Vdd , !0, and Rs).
84
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
Another factor required in the design process is !T . This can also be evaluated
with the help of (5.38) to be
!T Cgm =
gs
gm
2 WLC
ox
3
Vod = 3sat :
= 32 e
2
L
L
(5.43)
This expression is approximate because we are neglecting Cgd , the gate-drain overlap
capacitance. This approximation is reasonable if we assume that the LNA input
stage is cascoded. Note that proportionality to limits the !T that can be achieved
with a given device.
5.3.2 Noise Figure Optimization Techniques
With the relevant quantities now dened, we can proceed to optimize the noise
performance of the amplier. In low noise amplier design, determination of the
minimum noise gure is a common and well-understood procedure. Typically, a
small-signal model of the amplier is assumed a priori, an expression for F is formed,
and dierentiation leads to a unique source impedance that optimizes noise performance. The reader is referred to [43] for an excellent treatment of the general
approach. Note that the assumption of a xed small-signal model reects a discrete amplier mindset in which device geometry is not under the designer's control.
There is a signicant distinction, however, between that type of optimization and
the one which we seek to perform here. In an integrated circuit environment, the
device geometry is exible and can be incorporated into the optimization procedure.
Thus, we begin by specifying a desired design parameter, such as gain or power
consumption, under the condition of perfect input matching. Then, we determine
the appropriate small-signal model a posteriori through the optimization procedure.
By selecting Qs and Ls independently, we can determine the device geometry that
yields optimized noise performance with an excellent input match.
There are two approaches to this optimization problem which deserve special
attention. The rst assumes a xed transconductance, Gm , for the amplier. The
second assumes a xed power consumption. To illustrate the second approach, the
5.3: LNA Design Considerations
85
expression for F in Equation (5.35) can be re-cast to make its dependence on power
dissipation (PD ) explicit. It is, however, non-trivial to make the dependence on Gm
explicit. Fortunately, the condition for constant Gm is equivalent to the condition of
constant !T , as is clear from Equation (5.13). To maintain a xed !T , we need only
x the value of . Hence, we will reformulate F in terms of PD and to facilitate
both optimizations.
We can draw on Equations (5.38), (5.41), and (5.43) and substitute into (5.35)
expressions for , Qs, and !T in terms of the relative gate overdrive voltage, . The
result is that
0L
F = 1 + !
3 P (; PD )
sat
(5.44)
in which we have neglected the contributions of the gate resistance and inductor
losses to the noise gure. In this new expression, P (; PD ) is a ratio of two 6th-order
polynomials of given by
P (; PD ) =
PD P () + P0 P ()
P0 1
PD 2
,
2
3
1 + 2 (1 + )
(5.45)
with
s
2
P1() = (1 + )6 + 2jcj 5 1 + 2 (1 + )4 + 5 (1 + )2 1 + 2
2
P2() = 5 1 + 2 4 :
(5.46)
(5.47)
The form of Equation (5.44) suggests that optimization of F proceeds by minimizing
P (; PD ) with respect to one of its arguments, keeping the other one xed. The
complexity of this polynomial will force us to make some simplifying assumptions
when optimizing for a xed power dissipation. Fortunately, the optimization for a
xed Gm can proceed directly from (5.45) without further simplications.
86
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
5.3.2.1 Fixed Gm Optimization
To x the value of the transconductance, Gm , we need only assign a constant value
to . The appropriate value for is easily determined by substituting (5.43) into
the expression for Gm as found in (5.13). The result, which relates Gm to , is
(1 + )
Gm = 2!3Rsat L (1 + )22 :
(5.48)
0 s
Once is determined, we can minimize the noise gure by taking
@P (; PD ) = 0
@PD
(5.49)
which, after some algebraic manipulations, results in
s
PD;opt;Gm = P0
"
r
P3() = P 2 1 + 2jcj 5 + 5
P1() 0 1 + 2 2
#,1=2
:
(5.50)
This expression gives the power dissipation which yields the best noise performance
for a given Gm under the assumption of a matched input impedance. By comparing
(5.50) to (5.41), we see immediately that this optimum occurs when
s
r
5 + 5 2:183:
Qs = Qs ;opt ;Gm = 1 + 2jcj 2 2
(5.51)
Hence, the best noise performance for a given transconductance is achieved at some
specic input Q. Note that the value 2:183 is valid only for long-channel devices.
For short-channel lengths, where < 1, we can expect the optimum Qs to be
somewhat larger. Note that if we substitute Qs ;opt ;Gm into (5.32), the sum of the
second two terms (which are attributed to the presence of gate noise) exceeds unity,
thus indicating that the gate current contributes more noise than the drain current.
5.3: LNA Design Considerations
87
By substituting (5.51) into (5.35), we determine that the minimum noise gure
(neglecting inductor and gate losses) is
r
= 1 + 4 !0
5
!T
s
(
)1=2
2
2
Fmin ;Gm
1 + 2jcj + 5 5
p
!
0
= 1 + 1:235 1 + 1:164 !0 :
!T
!T
(5.52)
Note that the coecient 1:164 is valid only in the long-channel limit and is likely to
be somewhat larger in short-channel devices due to hot-electron eects.
5.3.2.2 Fixed PD Optimization
An alternate method of optimization xes the power dissipation and adjusts to nd
the minimum noise gure. The expression for P (; PD ) is too complex in to yield
a closed form solution for the optimum point. However, we can adopt a simplifying
assumption and check its validity by graphical comparison. If we assume that 1,
then P (; PD ) can be simplied to
P (; PD ) PD
P0
q
1 + 2jcj
5
+
3
5
+ PPD0 5 4
:
(5.53)
This expression is minimized for a xed PD when
@P (; PD ) = 0:
@
(5.54)
The solution of this equation, under the assumption that 1 is
(
r
p
5 + 5
2opt;PD = PPD 3 1 + 2jcj 2 2
0
)1=2
:
(5.55)
88
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
By comparing (5.55) to (5.41), it is clear that this value for is equivalent to an
optimum Qs of
Qs;opt;PD
p
(
r
5 + 5
= 3 1 + 2jcj 2 2
3:781:
)1=2
p
= 3Qs;opt;Gm
(5.56)
So, it is clear that the optimum Qs for a xed power dissipation is larger than the
optimum Qs for a xed Gm. We can now evaluate Equation (5.32) and use the result
in (5.35) to show that
r
= 1 + 16 !0
15
!T
(
s
2
2
1 + 2jcj + Fmin ;PD
5 5
p
!
0
= 1 + 1:426 1 + 1:344 !0
!T
!T
)1=2
(5.57)
where the value of 1:344 is valid only in the long-channel limit; the value will be
somewhat larger for short-channel devices in velocity saturation.
To examine the validity of our simplifying assumption that 1, the noise
gure is plotted in Figure 5.8 for the two cases dened in (5.45) and (5.53). The
solid lines predict the noise gure with (5.45), while the dashed lines predict the
noise gure with (5.53). The agreement is very good near the point of optimum Qs,
thus validating the approximation that 1. Figure 5.8 also illustrates the noise
gure prediction when the induced gate noise is ignored. Without the gate noise,
the model severely underestimates the noise gure.
5.3.3 Comparison with the Classical Approach
The classical approach to minimizing noise gure is presented in detail in Appendix
B. This technique, rst outlined by Haus et al., approaches the problem by assuming
that the device geometry and bias conditions are specied a priori, and proceeds
5.3: LNA Design Considerations
89
7.0
Complete Expression
Simple Expression
Noise Figure (dB)
6.0
5.0
4mW
6mW
8mW
10mW
gate noise
limited
4.0
2mW
3.0
2.0
without gate
noise model
1.0
0.0
1
10
100
Qs
Figure 5.8: Theoretical predictions of noise gure F for several power dissipations.
L = 0:44m, Rs = 50
, !0 = 10Grps,Vdd = 2:5V, = 1:3 [2], = 2:6, jcj =
0:395 [1], sat = 1 105 m/s, and "sat = 4:7 106 V/m [3].
to optimize the source impedance to achieve the minimum noise gure under this
constraint.
For comparison purposes, we repeat the result obtained in the analysis of Appendix B, which is that
q
+ jcj
2:162
1 , jcj2
r
p
4
2
= 1 + !0
5
!T 1 , jcj
p
!
0
= 1 + 0:820 1 + 0:773 !0 :
!T
!T
Qs;opt;C =
Fmin;C
5
2
p
(5.58)
(5.59)
It is interesting to note that the xed-Gm analysis results in an optimum Q that
is very similar to the classical approach. Indeed, the principal dierence between
these two techniques is that the amplier is operated o-resonance in the classical
solution, due to the fact that Yc 6= sCgs . As proven by Haus et al. [43], the minimum
90
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
noise gure for any linear twoport is achieved with a particular source conductance
when the source susceptance cancels the noise correlation susceptance of the network.
Such a condition is commonly referred to as a conjugate noise match. A MOS device
with partially correlated gate noise has a correlation susceptance given by
"
Bcor = sCgs
s
#
2
1 + jcj 5 1:25sCgs :
(5.60)
Hence, the optimum source susceptance is an inductance which resonates with the
gate capacitance at a frequency slightly higher than !0. This is sucient to specify
the imaginary part of Ys. A simple transformation can be used to put the source admittance into a series impedance form which is equivalent at a particular frequency.
This transformation preserves the value of inductance for moderate values of Q,
thus ensuring that the series resonance will occur at nearly the same frequency as
its parallel counterpart. This series equivalent corresponds to the architecture of the
LNA.
Because the analysis presented in this thesis assumes a series resonance at the
frequency of operation, we may conclude that it does not quite yield Fmin for a
particular device. However, the dierence in the optimum series resonance frequency
and !0 is only about 15 percent, which explains the similarity between the xed-Gm
optimization and the classical optimization. Hence, we can expect the proposed
architecture to possess near-optimum noise performance.
The xed-PD analysis, on the other hand, suggests an optimum Q that is quite
dierent from the classical result. This dierence compels us to compare the two
approaches to determine which one to follow. As we will demonstrate, the xed-PD
approach is likely to be preferred in most cases.
The dierence between these two techniques is one of constraints. The powerconstrained approach identies the best MOS device for a specied Rs and power
consumption. In contrast, the classical technique seeks to determine the optimum
Zs for a given MOS device at a specied power level, and though this latter approach
5.3: LNA Design Considerations
91
achieves the best noise performance for a particular device, it may yield a sub-optimal
result for other gures-of-merit (such as input reection coecient).
Additionally, the classical technique reects the bias of a discrete circuit design standpoint by assuming that the device is xed while only the input matching
network is under the designer's control. In contrast, in the context of integrated
circuits, the designer may wish to x the input matching network and tailor the
device geometry to optimize performance. Furthermore, the power-constrained approach permits power consumption to be considered as an explicit parameter, which
is useful in low-power systems where this is often an important design constraint.
It is important to emphasize that, although a comparison of (5.57) and (5.59)
seems to suggest that the classical approach always yields superior noise performance, these expressions are not directly comparable because !T may be dierent
in the two cases. This observation is relevant because the higher Q of the powerconstrained result leads to a narrower optimum device with higher current density
for a given power consumption. In fact, it is relatively easy to calculate the !T ratio
for the two cases.
!T;p = gm;p Cgs ;c Qs;opt;PD
!T;c gm;c Cgs ;p
Qs;opt;C
3=2
= 2:28:
(5.61)
In this expression, the subscript p refers to power-constrained optimization, and c
refers to the classical optimization. The resulting minimum noise gures can be
directly compared as follows:
Fmin;PD , 1 = 1:426 !T;c = 0:763:
Fmin , 1 0:820 !T;p
(5.62)
Hence, for a given power consumption, the power-constrained optimization yields superior noise performance and also provides an impedance match, which is a desirable
design goal in many cases.
To clarify this point further, consider Figure 5.9, which illustrates the LNA design
space for a constant power consumption. In this gure, the solid arcs represent xedPD optimizations, while the dashed arcs represent optimizations where Rs is modied
92
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
Noise Figure
Optimum Rs ,
Given !T
W0 ,Rs0
Gm
Gm
W1 ,Rs0
W1 ,Rs1
W2 ,Rs2
Qopt ;Gm
Optimum !T ,
Given Rs
W2 ,Rs1
W3 ,Rs2
Qs
Decrease W
Fix Rs
Increase Rs
Fix W
Optimum !T
Optimum Rs
Qopt ;PD
Figure 5.9: Noise gure optimization experiment illustrating the signicance of
Qopt ;Gm and Qopt ;Pd . Note that the curves shown represent constant-PD .
to noise-match the given device. Suppose that we begin with a device which has been
optimized using the xed-Gm analysis for a particular Rs0 , resulting in a device width
W0 . Although Rs is nearly optimally matched to this particular device, superior
noise performance can be obtained at the same power dissipation by decreasing the
device width to W1, following the xed-PD arc. The noise performance improves
in this procedure despite the non-optimal source resistance because !T improves as
the scaling is performed. This increase osets the loss in noise match until Qopt ;PD
is reached. At this point, the gate noise dominates the output noise of the device.
So, degrading the noise match in favor of the gate noise permits operation at an
elevated !T ; the net result is improved noise performance. Also note that the gain,
Gm , actually improves in this procedure.
Of course, once the new width, W1 , is determined, an increased source resistance
can be found which is noise-matched to this new device. This procedure takes the
design back along the dashed arc, yielding improved noise performance until Qopt ;Gm
is reached. However, there is a signicant penalty in Gm which is incurred by this
increase in Rs (recall that Gm is inversely proportional to Rs). Nonetheless, this
procedure could be repeated (at the expense of Gm ) as long as it is reasonable to
5.3: LNA Design Considerations
93
increase Rs and decrease W , maintaining Qs to lie within the white region of Figure
5.9.
The question is: at what point (and at which Qs) should the ultimate design be
placed? Assuming that a maximum realistic Rs can be specied, it seems reasonable always to design the LNA to operate at Qopt ;PD because this design point will
always possess a larger Gm than its lower-Q counterpart. The result is that the best
LNA design operates at a Qs which is dierent from the value corresponding to the
conjugate noise match. A noise mismatch is tolerated in return for a higher !T at
the same power dissipation.
We conclude that the optimization procedures given here, though not yielding
Fmin precisely as outlined in [43], permit selection of the best device for two constraints simultaneously: perfect input match, and a specic gain; or perfect input
match, and a specic power dissipation. Of these, the second set of constraints
yields the best combination of noise, power, and gain. There is only one device in a
given technology that optimizes noise performance while satisfying either set of two
of these specications for a particular Rs.
Finally, it is clear that, in all cases, the minimum noise gure improves as !T
increases with advances in technology. This fact, taken in conjunction with the
experimental results of this study, signies that CMOS low noise ampliers will
soon achieve noise performance at GPS frequencies that is largely parasitic-limited,
making CMOS an attractive alternative to more costly silicon bipolar and GaAs
technologies.
5.3.4 A Note on MOS Noise Simulation Models
The preceding analysis facilitates the design of CMOS low-noise ampliers using this
topology. It is important to note, however, that existing MOS noise models | as
implemented in circuit simulators such as HSPICE | do not adequately account for
hot-electron eects or induced gate eects. The options available for level 13, 28,
and 39 MOS models (BSIM-I, Modied BSIM-I, and BSIM-II, respectively) do not
account for even the most elementary of short-channel noise eects, much less the
94
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
more advanced considerations of the previous section. This situation is particularly
disturbing, given that the optimal LNA design will undoubtedly be limited by the
gate noise of the device.
Some strides have been made recently with the adoption of the BSIM-III model.
This model makes use of an alternative formulation for channel thermal noise in
which the noise power is treated as proportional to the total inversion layer charge
[88]. This is the same model proposed by Wang et al. [62]. Short-channel eects can
be included in the formulation of the inversion layer charge, and hence in the noise
power. However, even this model discounts the possibility that elevated carrier temperature is an important factor. The assumption of a uniform carrier temperature
along the entire channel length may explain the departure of the model's predictions
from measured data for relatively short-channel devices [89].
To circumvent the absence of a gate noise model in modern CMOS device simulators, there are two courses of action. The rst course is to modify the device model
equations to include the gate noise term. This modication is possible in some simulation environments where the simulator code is accessible to the designer. In such
cases, the gate noise can easily be included if it is represented as a noisy charge
uctuation that is added to the total gate charge in the model. In this case,
Q2g
Cgs2
=
4
kT
f
5gd0 :
(5.63)
This is the approach that was taken for the GPS receiver implementation described
in Chapter 8.
A second technique employs a macromodel in Spice to generate a gate noise
current with the right power spectral density that roughly tracks variations in gm so
that the designer is free to consider device geometry tradeos. Figure 5.10 illustrates
this technique, which is applicable to any MOS simulator. Device M1 is the device
that we wish to model. Its drain current is measured and reproduced in two replica
devices, M2 and M3, through the use of current feedback loops, implemented in
Spice by current-controlled current sources. By replicating the terminal voltages of
M1 in biasing M2 and M3, we can ensure that all three devices conduct precisely
5.3: LNA Design Considerations
Main Device
95
Replica #1
Vd
Vd
id1
Rg
K(ig2 , ig3 )
Replica #2
id2
Vg
M1
-1
Vd
id2
ig2
M2
id1
id3
-1
id3
ig3
M3
id1
Feedback
Vs
Vs
Vs
Figure 5.10: Modied NMOS noise model that includes the eects of induced gate
noise and gate polysilicon resistance.
the same current. Thus, the resulting gate voltages of M2 and M3 are exactly equal
to Vg , except for one thing. Because M1, M2 and M3 generate thermal noise, the
fed-back gate voltages are noisy. In fact, the gate voltage of M2 will have a noise
power of precisely
vg22 = 8kTB
g
m
(5.64)
assuming, for simplicity, that gm gd0 . The reason for the factor of 8 instead of the
usual 4 is that both M1 and M2 contribute equally to the noise voltage. Note that,
mathematically, this voltage has the same expression as twice the input-referred
squared noise voltage of the device. This voltage causes a current to ow in the gate
of the device. The current, ig2 , is given by
i2g2
2
8
kTB
[
!
(
C
gs + Cgd )]
=
:
gm
(5.65)
Now, because half of this current is due to the drain noise of M1, these two sources
are partially correlated. The same is true of ig3 , so that if we subtract ig3 from ig2 ,
the correlated parts cancel, leaving a noise current that has no correlation with the
96
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
drain current of M1. This current is fed back to the gate of M1 as K (ig2 , ig3 ).
The constant, K , is selected by comparing the expression for the induced gate noise
i2g
2
4
kTB
(
!C
gs )
=
5gm
(5.66)
with equation (5.65). If we assume that 2 , then we can solve for K .
1 :
5 1 + CCgdgs
K=p
(5.67)
With this choice for K , we have a model that produces an equivalent gate noise
with the right magnitude and frequency dependence that properly tracks variations
in device geometry and bias. In addition, by subtracting ig3 from ig2 , any signal
currents due to M1 cancel as well, thus ensuring that the feedback does not interfere
with the operation of the device.
5.3.5 Additional Design Considerations
The noise performance of a complete LNA is fundamentally limited by the noise
gure of the amplier input stage, as described in detail in the preceding sections.
However, optimizing the input stage is a necessary, but insucient step to guarantee
optimal noise performance for the whole amplier. This section describes a number
of techniques that will help to maximize LNA performance and avoid unnecessary
and costly design oversights. Additional detail is available in Appendix C which
presents experimental results for both a single-ended and a dierential CMOS LNA.
The preceding sections provide a thorough analysis of the common-source LNA
input stage, which aords the best possible noise performance of any architecture.
In this analysis, the eect of the gate-drain overlap capacitance Cgs was neglected
for simplicity. However, the inuence of Cgs cannot be neglected in practice. From
simulations of CMOS LNA circuits, including the eect of the induced gate noise,
it has been found that the power-constrained optimum Qs remains approximately
constant for realistic values of Cgs , assuming that a cascode input stage is used to
5.3: LNA Design Considerations
97
reduce the Miller eect. Based on this observation, a useful rule-of-thumb is that
the optimum device width is inversely proportional to frequency. That is,
Wopt f
0
(5.68)
where = 500m-GHz, based on simulations in a 0.5-m technology. Note that
because the capacitance per unit gate width is relatively constant as technologies
scale, this value for should remain approximately the same for shorter channel
lengths.
In addition to selecting the correct device width, it is important to consider
whether to use a single-ended or dierential design. Single-ended ampliers will
consume half the power and die area for a given theoretical noise performance when
compared to dierential ampliers. Furthermore, dierential ampliers typically require an o-chip balun that introduces additional loss, thereby degrading the overall
noise gure. On the other hand, single-ended ampliers are much more sensitive
to ground inductance and substrate impedances than are dierential ampliers. In
particular, the common substrate inductance can severely compromise reverse isolation and even amplier stability, as demostrated by the experimental results in
Appendix C. Furthermore, a single-ended LNA will be more susceptible to substrate and supply noise, which is an important issue for single-chip receivers. In
contrast, dierential ampliers possess a degree of common-mode rejection, and the
substrate impedance is of secondary concern. These advantages of the dierential
approach greatly simplify the design of a complete receiver system.
A number of additional principles that constitute good LNA design practice can
be enumerated. In particular,
The use of a cascode input stage leads to improved gain and improved amplier
stability by eliminating interaction between the input matching circuit and
the output tuned circuit. It is important, however, to minimize the noise
contribution of the cascode device by minimizing the capacitance at its source.
Merging the source of the cascode device with the drain of the input device
proves to be an eective technique for reducing this capacitance.
98
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
When selecting Ls to generate a 50
real term in the input impedance, it is
important to ensure that one does not inadvertently use too little inductance.
Doing so will lead to a severe noise penalty, as shown in Appendix C.
The input devices should be laid out with multiple gate ngers to reduce the
total polysilicon gate resistance, and the device should be surrounded with
substrate contacts to reduce the eective back-gate resistance.
Although it is tempting to perform the input matching on-chip with simple
inductive tuning, the resistive losses associated with spiral inductors are typically prohibitively large for this purpose because of the noise gure degradation
that they introduce.
One should be careful to shield the LNA input pads from the substrate to
eliminate unnecessary loss. In addition, the use of patterned ground shields
beneath the spiral inductors greatly reduces the energy lost to the substrate
[52].
Clearly, a number of important considerations play a direct role in determining
the ultimate LNA performance that is achieved. Fortunately, none of them represents a fundamental barrier and all can be mitigated with sucient attention to
detail in the design and layout of the amplier.
5.4 Summary
We have presented a thorough analysis of the design of CMOS low noise ampliers
in this chapter. With a corrected MOS noise model in hand, the power-constrained
optimization procedure leads to simple design criteria that yield the best combination
of noise gure, input power match and gain.
Theoretical analysis of the amplier architecture has demonstrated the fundamental role of induced gate noise, which is essential in dening the minimum noise
gure. That in many practical cases this source of noise may dominate the output
noise of the amplier underscores the critical need for improved MOS noise models.
5.4: Summary
99
Given the intense interest in RF CMOS, it is likely that improved models will be
developed in the near future.
Experimentally, as detailed in Appendix C, we have demonstrated a single-ended
30mW low noise amplier in a 0.6-m CMOS process that is suitable as a rst
amplier in a GPS receiver. The amplier's noise gure of 3.5dB was the lowest
reported for a CMOS LNA in this frequency range when it was rst published. A
second experimental LNA was presented that achieves a 3.8dB noise gure with
only 12mW of power consumption in a 0.35-m CMOS process. This result is
most directly comparable to a single-ended design that consumes 6mW, and thus
represents a substantial improvement over the rst LNA. The low power consumption
of this architecture is a result of aggressive current conservation through currentreuse in the input and output stages.
In the nal implementation of the GPS receiver in Chapter 8, we will demonstrate a dierential LNA that achieves a 2.4-dB noise gure with 12-mW power
consumption in a 0.5-m CMOS process. This result represents a signicant advance in CMOS low noise ampliers, and is directly enabled by the theoretical basis
presented in this chapter.
100
Chapter 5: Low-Noise Amplication in CMOS at Radio Frequencies
Chapter 6
CMOS Mixers
A
N essential element in all modern radio receivers is the mixer, which is responsible for frequency translation or \heterodyning". Historically, a family
of techniques have developed for performing frequency translation, including the
double-balanced diode-ring mixer and the Gilbert multiplier, among others. More
recently, research has been focused on extending these techniques for use in CMOS
technologies and on developing new techniques that are uniquely suited for CMOS.
This chapter begins in section 6.1 with a review of commutating mixer techniques.
In section 6.2, we present a double-balanced CMOS voltage mixer that has been selected for use in this work. A detailed analysis of the mixer reveals some unexpected
conversion gain behaviors that arise due to the linear time-variant (LTV) nature of
the mixer when its output is capacitively loaded. In addition, we will address the
topics of noise gure and linearity to illustrate the merits of this architecture.
6.1 Review of Mixer Architectures
The predominant class of mixers that nd use in modern radio receivers is the timevarying or \commutating" class of mixers. Unlike nonlinear mixers that employ
cross-modulation to perform mixing, commutating mixers employ switching mechanisms to change periodically the sign of the input signal under the control of a local
oscillator. Because the RF and IF ports are linearly related (at least in principle),
101
102
Chapter 6: CMOS Mixers
such mixers generally exhibit improved distortion characteristics compared to their
nonlinear counterparts.
Commutation can be performed in the voltage or current domains. Figure 6.1
illustrates three mixer examples; two that use a diode ring for voltage switching,
and one that uses bipolar current switches. In Figure 6.1(a), the local oscillator is
coupled to the center taps of the two transformers to control which pair of diodes
is forward biased. When the outer pair is forward biased, the input and output
ports are connected in phase; when the inner pair is forward biased, the ports are
connected out of phase. Because the LO is coupled to the center taps, it does
not couple to either of the other two ports. In addition, the symmetric switching
prevents input signal frequencies from appearing directly at the output. Because of
these isolation properties, the diode ring mixer is called a double-balanced mixer.
Figure 6.1(b) illustrates a dierent mode of operation for the diode ring mixer in
which the LO drive is transformer-coupled to the ring. In this case, a dierent pair
of diodes is activated on each phase of the LO that couples the other transformer
to the center taps of the two secondaries. This connection is widely used when the
RF and LO signals are at high frequencies and the IF output is at a relatively low
frequency. Center tapping the IF port permits the use of smaller self inductances
in the transformer secondaries, which only need to present large impedances at the
LO and RF frequencies.
While diode ring mixers operate on a voltage switching principle, the Gilbert
mixer operates on a current switching principle. As shown in Figure 6.1(c), the mixer
employs two bipolar current switches whose outputs are connected in opposition. On
one phase of the LO, the input current ows to the output through the outer pair
of devices, while on the opposite phase, the input current is diverted to the opposite
outputs via the inner pair of devices. If the bases of the transistors are driven
symmetrically, the emitters lie at points of symmetry so that, in principle, no local
oscillator signal couples to the input or output ports. So, just as in the diode ring
case, the Gilbert mixer is nominally a double-balanced mixer.
The Gilbert mixer owes its success in part to the fact that bipolar devices make
excellent current switches. By analogy, MOS devices are excellent voltage switches,
6.1: The Double-Balanced CMOS Voltage Mixer
+
-
103
-
+
(a)
-
+
+
-
(b)
+
-
-
+
(c)
Figure 6.1: Commutating mixer architectures, illustrating the switching principle
employed in each. (a) Diode ring with center-tapped LO drive. (b) Diode ring with
transformer-coupled LO drive. (c) Gilbert mixer.
104
Chapter 6: CMOS Mixers
Mixer
LO Driver
RFp
LOp
LOm
LOp
RFm
IFA
LOm
Vb
Ibias
Figure 6.2: CMOS voltage mixer and LO driver.
and this observation motivates an investigation of the CMOS voltage mixer presented
in the next section.
6.2 The Double-Balanced CMOS Voltage Mixer
A mixer topology consisting of a pair of dierential voltage switches is illustrated in
Figure 6.2. The gates of the switches are driven by a tuned LO driver whose output
inductive loads resonate with the gate capacitance of the switches to provide a high
impedance at the resonance frequency, thereby reducing the power consumption in
the driver.
In this mixer, two switches are controlled by the positive phase of the local
oscillator, and the other two are controlled by the negative phase, which lags by
180. Thus, the mixer connects its RF port to its IF port through these switches
with a polarity that alternates at the LO frequency. It is this alternation of polarity
that establishes mixing.
The receiver uses two of these mixers, driven by quadrature local oscillators. To
generate the quadrature LO, one of the LO drivers is modied as shown in Figure
6.3. With the Miller feedback capacitance, the amplier has a transconductance of
6.2: The Double-Balanced CMOS Voltage Mixer
105
jw
LOp
90
LOm
s
Vb
Ibias
Figure 6.3: Quadrature generation with the Miller capacitance.
sC=gm :
Gm = gm 11 ,
+ sC=g
m
(6.1)
This expression has a LHP pole and a RHP zero, resulting in an all-pass characteristic with a phase shift of 90 at ! = gm=C . To regulate the pole/zero frequency,
a constant-gm bias source generates Ibias . This technique is suitable for use in this
particular receiver due to the relaxed requirements for I/Q matching.
In the following sections, we examine in detail the conversion gain properties,
noise gure and linearity of this mixer architecture.
6.2.1 Basic Mixer Conversion Gain
The conversion gain of the mixer can be determined by a careful analysis with special
attention paid to the time-varying nature of the mixer. There are several types of
LO drive that might be applied to the switches in the mixer, as shown in Figure 6.4.
106
Chapter 6: CMOS Mixers
vlo
vlo
Vth
Vth
t
t
(a) Square wave drive
(b) Sinusoidal drive
vlo
vlo
Vth
t
Vth
(c) Break-before-make
t
(d) Make-before-break
Figure 6.4: Four LO signals investigated
The simplest of these is a square wave with 50% duty cycle, illustrated in Figure 6.4(a). The LO voltage for a square wave drive can be expressed mathematically
as follows:
vlo (t) = ALO (2t=TLO ) 1
X
(t , nTLO )
n=,1
(6.2)
where ALO is the local oscillator amplitude, (t) is the rectangle function, and TLO
is the local oscillator period. This LO signal will serve as a reference for comparison
with other types of LO signals.
In practice, a square wave drive is dicult to achieve at radio frequencies. A
more practical and power ecient method is to resonate the gate capacitances and
drive the gates sinusoidally, as shown in Figures 6.4(b){6.4(d). In this case,
vlo (t) = ALO cos (2fLO t + LO ) + BLO
(6.3)
where BLO is the DC level on the gates. The choice of BLO determines whether or
not the two switch pairs will conduct during overlapping portions of the LO period.
6.2: The Double-Balanced CMOS Voltage Mixer
g(t)
vrf (t)
CL
g(t , T2LO )
g(t ,
TLO )
2
g(t)
107
gT (t)
vT (t)
CL
+
vif (t)
-
(b)
(a)
Figure 6.5: Mixer core. (a) Time-varying conductance model, and (b) Thevenin
equivalent circuit.
In Figure 6.4(b), BLO equals the switch threshold voltage, Vth ; in 6.4(c), BLO < Vth ,
resulting in break-before-make switching action, while in 6.4(d), BLO > Vth , resulting
in make-before-break action.
The switches in the mixer are simply time varying conductances, as shown in
Figure 6.5(a). Therefore, we can replace the switch network with a Thevenin equivalent network, as shown in Figure 6.5(b). The open circuit voltage is then given
by
g(t , TLO =2) v (t) = m(t)v (t)
vT (t) = gg((tt)) ,
rf
+ g(t , T =2) rf
LO
(6.4)
and the Thevenin impedance, written as a conductance, is
gT (t) = g(t) + g(t2, TLO =2) :
(6.5)
In equation (6.4), m(t) represents the eective mixing function of the network. For
example, when the LO drive is a square wave, m(t) is a square wave with zero DC
value and unit amplitude. This multiplies the input voltage, vrf (t), to yield a mixed
open circuit voltage, vT (t). Figure 6.6 illustrates the mixing function:
g(t , TLO =2)
m(t) = gg((tt)) ,
+ g(t , T =2)
LO
and gT (t), for the four types of LO drive presented in Figure 6.4.
(6.6)
108
Chapter 6: CMOS Mixers
m
1
0
-1
gT
t
0
t
(a) Square wave drive
m
1
0
-1
gT
t
0
t
(b) Sinusoidal drive
m
1
0
-1
gT
t
0
t
(c) Break-before-make
m
1
0
-1
gT
t
0
t
(d) Make-before-break
Figure 6.6: Mixing function and Thevenin conductance for the four cases
6.2: The Double-Balanced CMOS Voltage Mixer
109
Table 6.1: Gc for the four types of LO drive.
Square wave drive
Sinusoidal drive
Break-before-make
Make-before-break
(
2=
2p=
(2=p) 1 , r2
,
1
sin (r)=r+ 1,r2 0 r 1
1=(2r)
1r<1
r = jVthA,LOBLO j
Both m(t) and gT (t) exhibit important properties. The mixing function m(t) has
no DC component, is periodic with a period of TLO , and has half wave symmetry,
implying that it only has odd frequency content (nfLO , where n is an odd integer).
The absence of a DC component in the mixing function indicates that the RF voltage
is isolated from the IF port of the mixer. In contrast, the conductance gT (t) has a
DC component and is periodic with period TLO =2. The average conductance plays
an important role in setting the IF bandwidth of the mixer, as will be shown shortly.
If we assume that CL = 0, then vif (t) = vT (t). To nd the conversion gain from
the RF port to the IF port, we evaluate the magnitude of the Fourier transform of
the mixing function at fLO . The resulting conversion gain, Gc, is shown in Table 6.1
for the four types of LO drive. It is interesting to note that Gc in the last two cases
involves a single parameter, r, that characterizes the choice of BLO and ALO .
6.2.2 LTV Conversion Gain Analysis
In general, CL does not equal zero. To solve for the conversion gain in this case,
we must determine the time-varying impulse response of the network and apply the
superposition integral to nd vif (t) as a function of vrf (t). In doing so, we will
demonstrate that capacitive loading can be used to actually increase the conversion
gain of the mixer above the classical limit of -3.92dB.
110
Chapter 6: CMOS Mixers
To evaluate the impulse response, we apply an impulse to the circuit in Figure 6.5(b) at time , vT (t) = (t , ). The initial voltage produced on CL can
most readily be determined by transforming the Thevenin equivalent circuit in Figure 6.5(b) into its Norton form with the following short circuit current:
iN (t) = gT (t)vT (t) = gT ( )(t , ):
(6.7)
The total charge delivered to the capacitor as a result of this impulse in current is
gT ( ) coulombs. This charge produces an initial voltage of gT ( )=CL volts on CL at
time . The following dierential equation describes the circuit's response to this
initial condition:
if (t)
= ,gT (t)vif (t):
CL dvdt
(6.8)
The solution has the form h(t) = Ae,f (t) . Combining the initial condition with this
solution, and noting that the system is causal, yields the network impulse response:
h(t; ) = gTC( ) e,
L
gT (s)
CL ds u(t
Rt
, )
(6.9)
where u(t) is the unit step function. To determine the response at the IF port of the
mixer, we simply apply the superposition integral for this impulse response with an
input voltage of m( )vrf ( ). The result is that
Z t
R
g
T ( ) , t gTCL(s) ds
e
m( )vrf ( )d:
vif (t) =
,1 CL
(6.10)
To simplify this expression, it is useful to express gT (t) as a Fourier series
gT (t) = gT +
1
X
n=1
an cos (n2!LO t + n) = gT + gfT (t)
(6.11)
6.2: The Double-Balanced CMOS Voltage Mixer
111
where gT is the DC level of gT (t) and gfT (t) is the time-varying portion of gT (t).
Furthermore, we dene the integral of gfT (t)=CL to be
ffT (t)
=
gT
1
X
ansin (n2!LO t + n)
2!LO CL n=1
ngT
+K
(6.12)
where K is an arbitrary constant. With these denitions, we can re-express the
superposition integral in (6.10) as follows:
vif
(t) = effT (t)
Z t
gT e, CgTL (t, ) e,ffT ( ) gT ( ) m( )v ( )d:
rf
gT
,1 CL
(6.13)
Equation (6.13) can be simplied by paying attention to the form of ffT . Note
that from equation (6.12), ffT is proportional to a normalizing coecient
gT
2!LO CL
(6.14)
which is the ratio of the average bandwidth of the network to twice the local oscillator
frequency. Thus, when CL is suciently large that the average bandwidth is much
less than the local oscillator frequency, the exponential terms involving ffT reduce to
unity, and (6.13) can be simplied, yielding
vif (t) =
Z t
gT e, CgTL (t, ) gT ( ) m( )v ( )d:
rf
gT
,1 CL
(6.15)
We can identify the function of each term in (6.15) to clarify the inuence of
the load capacitance, CL on the mixer's operation. First, the RF port voltage is
multiplied by a modied mixing function, which is conveniently dened to be
m0 (t) = ggT (t) m(t):
Tmax
(6.16)
In this expression, gTmax is the peak conductance of gT (t), which normalizes m0 (t)
to vary between 1. This modied mixing function appears in Figure 6.7 for the
four LO drive signals analyzed previously. Second, by introducing gTmax , we can
112
Chapter 6: CMOS Mixers
m0
1
0
-1
m0
1
t 0
-1
(a) Square wave drive
t
(b) Sinusoidal drive
m0
1
t 0
-1
m0
1
0
-1
(c) Break-before-make
t
(d) Make-before-break
Figure 6.7: Modied mixing functions for the four cases
also dene an eective gain
A = gTmax
g
T
(6.17)
which is the ratio of the peak conductance to the average conductance. Finally, the
remaining terms simply describe a lowpass lter with bandwidth gT =CL. Combining
these concepts, (6.15) can be expressed as
vif (t) = hlpf (t) [Am0 (t)vrf (t)] :
(6.18)
An equivalent block diagram representation of this expression appears in Figure 6.8.
The total voltage conversion gain is just AG0cjHlpf (fIF )j, where G0c is the conversion
gain associated with m0 (t), and jHlpf (fIF )j is the gain of the eective low-pass lter
at the IF frequency.
It is interesting to compare the conversion gain for a sinusoidal LO drive of the
capacitively terminated mixer to that of the reference square wave drive. For a
sinusoidal drive, G0c = 1=2, whereas for a square wave drive, G0c = 2=. But in the
6.2: The Double-Balanced CMOS Voltage Mixer
113
T (t)
m(t)
m0 (t) = ggTmax
A = gTmax
gT
!3dB = CgTL
vrf (t)
vif (t)
Figure 6.8: Equivalent block diagram for core conversion gain
square wave case, the peak-to-average conductance is unity, while in the sinusoidal
case it is =2. Thus, the voltage conversion gain for a sinusoidal drive with capacitive
loading is actually =4 (-2.1dB), which exceeds the 2= (-3.9dB) value for a square
wave drive.
The analysis can be taken one step further by considering the conversion gain
for a break-before-make drive. It is possible, though slightly involved, to express
conversion gain as
p
cos ,1(r) , r 1 , r2
c= p
2[
1 , r2 , rcos ,1(r)]
1 , 4 r + 4
AG0
(6.19)
where r = (Vth , BLO )=ALO . Figure 6.9 plots (6.19) as a function of r. Surprisingly,
the voltage conversion gain actually approaches unity as r ! 1, which corresponds
to the extreme condition of the break-before-make drive where each switch is on
for a single instant of the LO cycle. Thus, in principle, by adjusting the switching
point of the mixer switches, the conversion loss can be made arbitrarily small. However, as r approaches unity, linearity suers greatly, making this mode of operation
impractical.
As shown in this section, the conversion gain for a capacitively loaded CMOS
voltage mixer can be increased by using a sinusoidal LO drive. This eect is a direct
result of the time-varying lter formed by the switch on-resistance and the load
capacitance. In the GPS receiver of this work, this eect is exploited to improve the
114
Chapter 6: CMOS Mixers
1
0.95
AG0c
0.9
0.85
0.8
0.75
0
0.2
0.4
r
0.6
0.8
1
Figure 6.9: AG0c vs. r for a break-before-make LO drive.
conversion gain of the mixers by using the input capacitance of the IF amplier as
the terminating capacitance.
6.2.3 Mixer Noise Figure
Although the mixer core consumes negligible power, the LO driver consumes power
to drive the input capacitance of the mixer. Thus, the sizing of the mixer devices
is linked to the design of the LO driver. The size of these devices and the LO drive
level also determine the noise gure of the mixer. So, the mixer noise gure and LO
driver power consumption are intimately linked.
As demonstrated in Chapter 3, the SSB noise gure of an ideal mixer (one that
has no internal resistive losses) is given by
F = Lc
(6.20)
6.2: The Double-Balanced CMOS Voltage Mixer
115
where Lc is the power conversion loss of the mixer. This equation can be modied
to include the on-resistance of the mixer switches, which appears in series with the
source resistance. Thus,
F = Lc 1 + 2RRm
s
(6.21)
where Rm is the average on-resistance of a single switch.
To determine Rm , we can assume that
Rm = g1 =
ds
L
e Cox WVod
(6.22)
where Vod is the average overdrive voltage supplied by the LO driver. This voltage
is related to the power consumption in the LO driver, the frequency of operation
and the Q of the spiral inductors that are used. The choice of spiral inductor is also
constrained by the requirement that it resonate with the input capacitance of the
mixer plus other parasitic capacitances, including the spiral's own self-capacitance.
If the LO driver has a tail current of I0, the amplitude of one of the LO driver
outputs is given by
ALO = 2I!I0 QCL
(6.23)
LO
where QL is the Q of the load inductors, and C is the total load capacitance on
the LO driver output. The parameter I accounts for the fact that not all of the
bias current is available at the output, due to parasitic losses in the LO driver itself.
The capacitance, C , comprises two switch gate capacitances plus the spiral's selfcapacitance. If the driver has a certain self-resonant frequency, !SR , then the allowed
switch capacitance is given by
2
Cox WL = C2 1 , !!LO
2 :
SR
(6.24)
116
Chapter 6: CMOS Mixers
Finally, combining equations (6.21) through (6.24), we nd an approximate formula for the mixer noise gure:
F = Lc 1 + !LO =!C 2
1 , (!LO =!SR )
(6.25)
where !SR is the self-resonant frequency of the spiral inductors, and !C is a critical
frequency given by
e I I0
!C = RsQ8LL
2
(6.26)
beyond which the achievable noise gure begins to degrade rapidly. For a reasonable
choice of self-resonant frequency, the noise gure is degraded by 3dB when !LO = !C .
As a brief example, suppose that !LO = 10Grps, !SR = 30Grps, Rs = 100
,
QL=5, e = 250cm2=Vs, I = 0:75, I0 = 4mA and L = 0:5m. Then !C 6Grps,
and F = 2:9Lc, resulting in a loss of 4.6dB over the ideal (internally lossless) mixer.
If Rs is increased to 400
, then F = 1:5Lc, which is a loss of 1.7dB when compared
to the ideal case.
Although this analysis is greatly simplied, the result yields some intuition about
fundamental tradeos. In particular, the performance of this type of mixer should
improve dramatically as technology scales due to the 1=L2 factor in !C . For a given
bias current, the noise performance is strongly inuenced by the QL of the spiral
inductor loads. In addition, the self-resonant frequency should be no lower than
about 3!LO to avoid a sharp degradation in noise gure.
Notably absent from the result is any dependence on the switch size. As one
reduces the switch size (and increases the load inductance value), the voltage swing
at the gate of the switch increases so that the average on resistance, Rm , remains
roughly constant. So, the size of the switch is a relatively free parameter that can
be optimized for maximum linearity.
There is one additional merit of the CMOS voltage mixer structure that is worth
mentioning. Because there is no DC current through the switches, they contribute
no 1=f noise to the mixer output. This consideration is particularly important in
6.3: Summary
117
direct conversion architectures where low-frequency noise and osets at the mixer
output are of concern.
For a more thorough treatment of the general subject of noise in mixers, the
interested reader can refer to [90].
6.2.4 Mixer Linearity
There are two major sources of distortion in the mixer: device nonlinearities and
phase modulation of the switching instants.
To improve the linearity of the transistors, it is most important to keep the
current through the switches small to reduce nonlinear voltage drops across the
devices [91]. This criterion is satised with the use of a small capacitive load, which
presents a high impedance to the output. Note, however, that this requirement is
at odds with the use of capacitive loading to boost the conversion gain of the mixer.
The remaining nonlinearities consist of parasitic junction capacitances, which are
weak nonlinearities.
A second source of distortion arises from phase modulation of the mixing function
by the RF voltage, an eect which is also found in diode-ring modulators [92]. This
distortion becomes more pronounced as the amplitude of the RF voltage approaches
that of the LO drive voltage. In this situation, the instant at which switching occurs
exhibits a signicant dependence on the RF voltage itself. Hence, the eective
mixing function depends directly on the RF voltage and this dependence introduces
distortion. Borrowing from the research on diode ring mixers, we may expect this
type of distortion to diminish if larger LO drive levels are used to steepen the LO
waveform's slope as it passes through zero. A corollary is that square wave drives
will typically lead to improved linearity over sinusoidal drives. References [91] and
[92] contain more detailed treatments of this type of distortion in diode ring mixers.
118
Chapter 6: CMOS Mixers
6.3 Summary
This chapter has presented a thorough analysis of the double-balanced CMOS voltage mixer, which uses four CMOS voltage switches to implement a mixer with no
static power consumption. When reactively loaded, this mixer exhibits some unusual conversion gain properties that are only predictable by treating the mixer as a
bandwidth-limited linear time-variant (LTV) system. In particular, the conversion
gain can exceed the classical limit of 2= when the mixer is capacitively loaded.
In addition, we have presented a noise analysis of the mixer that demonstrates
its potential for low-noise operation. Combined with the fact that a large voltage
headroom is available due to the simplicity of the mixer topology, this architecture
oers the promise of wide dynamic range, as long as the LO drive is suciently
strong.
The mixer is the last block in the signal path that processes RF signals. As we
move on to analyze the IF chain, we enter the world of baseband amplier techniques.
The need for large \inductances" in the frequency-selective blocks operating at these
lower frequencies forms the principal motivation for the considerations of the next
chapter. In particular, we will explore how to maximize the dynamic range of one
of the most vexing subsystems in an integrated receiver: the on-chip active lter.
Chapter 7
Power-Ecient Active Filters
T
HE channel lter of an integrated receiver is arguably one of the most important signal path blocks, and one of the most dicult to realize in integrated
form. It is responsible for attenuation of out-of-band interference that might desensitize the receiver, and thus it must possess a large stop-band rejection. In integrated form, the realization of high-Q lters is complicated by the lack of suitable
integrated inductors. Although active circuit techniques can provide the necessary
reactance through feedback, the relatively large noise and low dynamic range of
active inductors limits their use substantially.
In this chapter, we begin by reviewing some techniques for implementing integrated lowpass lters. Then, in section 7.2, we pursue a thorough analysis of one
of these techniques, the Gm-C technique, in which active inductors (or gyrators)
are used to obtain complex poles and zeros. The limitations of this approach are
made explicit by the analysis, and design guidelines are elucidated. In particular, a
gure of merit for active transconductor architectures is derived that permits a fair
comparison of dierent approaches. Section 7.3 presents a survey of transconductor
architectures based on this gure of merit, arriving nally at a new transconductor
that is both power-ecient and linear.
119
120
Chapter 7: Power-Ecient Active Filters
Z1
Z1
Z2
Z1
Z2
Z2
Figure 7.1: Generic structure of the \electric wave-lter", or ladder lter.
7.1 Passive and Active Filter Techniques
The passive L-C ladder lter that enjoys widespread use today was invented in 1915
nearly simultaneously by Wagner in Germany and Campbell in the U.S. [32] [33]. It
appears that Wagner had priority, but his work was suppressed by German military
authorities during World War I. The basic lter topology invented by Wagner is
shown in Figure 7.1. In its original incarnation, the \electric wave-lter" comprised
a chain of identical, repeating sections. However, the lter theory was soon extended
to allow for sections of diering impedances [34]. Later theoretical developments
enabled the realization of a variety of frequency and phase responses.
Figure 7.2 illustrates several common lowpass lter types that are realizable
with a nite number of ladder sections. The Butterworth lter has a maximally
at passband, while the other ltershapes provide sharper cutos with equal ripple
either in the passband (Chebyshev Type I), the stopband (Chebyshev Type II), or
both (elliptical). For the present work, the elliptical lter is signicant because it
possesses the sharpest transition band of any lter topology for a given order and
is therefore the most selective of all the lters. It also has the most severe phase
distortion. However, for the GPS system, the phase distortion is not of primary
concern due to the large processing gain.
Passive ladder lters can be implemented using discrete inductors and capacitors,
by exploiting mechanical resonance in quartz crystals, or by using acoustic waves in
7.1: Passive and Active Filter Techniques
121
Butterworth
Elliptical
Chebyshev Type I
Chebyshev Type II
Figure 7.2: Four common types of lowpass lters.
ceramic materials. In integrated receivers, one can also employ passive spiral inductors and capacitors, but the low quality factor and small inductance of integrated
inductors severely limits their utility [93]. Recently, there has been some interest
in micromechanical lters in silicon that operate at frequencies as high as 70MHz
[94]. Using micromachined resonators, one can achieve very high quality factors.
However, these lters presently suer from a number of important problems that
remain to be solved. These include poor component tolerances, tiny dynamic range,
and the need to operate in a near vacuum to realize reasonable quality factors. Until
these problems are resolved, micromechanical lters are not an attractive alternative
to o-chip passive lters.
Due to the lack of suitable passive components, integrated lters that operate
in the low-MHz range of frequencies must be implemented using active circuit techniques. There are, however, several tradeos that must be considered when determining whether or not to integrate a lter. Integrated active lters consume power,
122
Chapter 7: Power-Ecient Active Filters
Figure 7.3: A Sallen and Key lowpass lter.
produce distortion and noise, and consume die area. These factors place integrated
lters at an immediate disadvantage compared to o-chip discrete lters. All the
same, there are a few good reasons for integrating the lters in a radio receiver.
One reason for using integrated lters is the reduction of board cost and component
count that accompanies their use. A second reason is the reduction in electromagnetic interference that may occur due to board level coupling from other integrated
circuits. Finally, in the case of GPS receivers, complete system integration helps to
enable embedded applications where GPS functionality can easily be integrated into
more complex systems, such as cellular phones. For these reasons, integration of the
IF lters has been pursued in this work.
To realize integrated active lters, there are a number of techniques to consider.
One family of lters, known as Sallen and Key lters [95], uses a network of resistors
and capacitors and a single feedback amplier. Because RC networks only produce
real poles, feedback is required to realize complex poles. An example of a Sallen
and Key approach is shown in Figure 7.3. This circuit implements a second order
transfer function of the form
h
H (s) = s2 + ds
+ 1:
(7.1)
Although lters of this sort are very simple, their principal limitation is an extreme
sensitivity to process variations [96].
There are other active lters that use integrators as fundamental building blocks.
Complex lter responses can be obtained by enclosing several integrators in various
7.1: Dynamic Range of the Active Gm-C Filter
(a)
123
(b)
Figure 7.4: Integrators for the (a) MOSFET-C lter and (b) Gm-C lter.
types of feedback loops. Filters that use this approach include MOSFET-C lters
and Gm -C lters. The basic integrator element of each lter type is illustrated in
Figure 7.4.
In the MOSFET-C integrator, a simple operational amplier integrator is used
with two FET's acting as variable resistors. Tuning is accomplished by adjusting the gate voltages of the two FET's. In contrast, the Gm-C integrator uses a
transconductor driving a load capacitance. Tuning is then accomplished by setting
the transconductance. There are various methods for automatically tuning these
lters that have been extensively studied in the literature. A discussion of tuning
techniques is beyond the scope of this work, but the interested reader can consult
[97] for numerous examples.
In the present work, which emphasizes low power for portability, the MOSFETC technique stands at a disadvantage due to the need for operational ampliers.
Though typically less linear, Gm-C lters oer reduced power consumption due to
their ecient use of supply current. Because of this, the Gm-C technique was selected
for this work.
The following sections examine the limitations of Gm-C lters in some detail
to determine how to maximize dynamic range for a given power consumption. In
particular, we will look at a subclass of Gm-C lters called gyrator lters that directly
124
Chapter 7: Power-Ecient Active Filters
implement the inductive elements of an LC ladder using gyrator circuits of the type
shown in Figure 7.6.
7.2 Dynamic Range of the Active Gm-C Filter
Figure 7.5 illustrates a block diagram of the on-chip active lter and its equivalent
half-circuit. The intermediate-frequency amplier (IFA) drives the input of the lter
directly, and the load resistors in the IFA output stage also terminate the lter input.
Similarly, a real resistor provides the output termination, permitting a reduction in
power consumption.
As shown in Table 4.1, the lter is the dynamic range limiting block in the system.
Previous studies have typically examined the dynamic range problem in active lters
by assuming that the largest acceptable signal voltage is a xed parameter [98], often
expressed as a simple fraction of the supply voltage [53]. One problem with such
an approach is that it partly obscures the dependence of dynamic range on power
consumption and choice of transconductor architecture. In previous work where
the dynamic range is formulated explicitly without such assumptions, the analysis
is typically limited to the specic architecture under discussion, and is therefore
lacking in generality [99] [100].
In the following discussion, we derive an expression for dynamic range with power
consumption as an explicit constraint that is broadly applicable to Gm -C lters, independent of transconductor architecture. In doing so, we will identify a transconductor gure of merit that can be applied to aid the selection of an architecture that
maximizes the dynamic range of the lter for a given power consumption.
We begin by deriving the minimum noise gure of the lter.
7.2.1 Noise Figure
To determine the noise gure, we construct a noise model of each gyrator to understand how its internal ampliers contribute noise to the system.
7.2: Dynamic Range of the Active Gm-C Filter
IFA
125
Gm-C Filter (LC Ladder Prototype)
Gy
Gm
Gy
Gy
Gy
Replica Bias Circuit
Gyrators (2 Transconductors, ea.)
(a)
1k
1.23p
3.29p
86u
83u
50p
104p
49p
1k
(b)
Figure 7.5: Block diagram of the on-chip Gm-C lter and its equivalent half-circuit.
126
Chapter 7: Power-Ecient Active Filters
,gm1
gm1
,gm2
2
vn1
gm2
L
i2n2
C
2
vn1
i2n2
(b)
(a)
Figure 7.6: A simple gyrator and its equivalent circuit with noise sources.
Figure 7.6(a) shows an equivalent circuit of a simple gyrator that implements a
oating inductor. Each transconductor generates thermal noise at its output that
degrades the noise gure of the lter. By referring the transconductor noise sources
to the external terminals of the gyrator, one arrives at the equivalent circuit shown
in Figure 7.6(b), where
L = g Cg
m1 m2
(7.2)
2
4kT
vn1
=
f gm1
(7.3)
i2n2 = 4kTg
m2
f
(7.4)
where > 1 is a factor describing the amount of excess noise generated by a transconductor cell when compared to a real conductance of the same value.
7.2: Dynamic Range of the Active Gm-C Filter
127
At low frequencies, the inductor presents a short, and the voltage and current
noise sources contributed by all of the gyrators in the lter sum together so that
2
vn2 = 2NLvn1
(7.5)
i2n = 2NLi2n2
(7.6)
where NL is the number of inductors in the lter. The corresponding minimum spot
noise gure is
Fmin = 2 1 + 2NL
r
gm2 4N r gm2
L
gm1
gm1
(7.7)
which occurs for an optimum terminating resistance of
Rt = pg 1 g :
m1 m2
(7.8)
It is interesting to note that the minimum noise gure depends primarily on
the order of the lter (through NL ) and on the architecture of the transconductor
(through ). In fact, the minimum noise gure does not depend on the choice of
Rt , implying that a xed power gain is required preceding the lter to minimize
its contribution to the system noise gure. Some improvement can be obtained
by adjusting the relative magnitudes of gm1 and gm2 , but this degree of freedom
is constrained by the need for good distortion performance, as shown in the next
section.
7.2.2 3rd-Order Intermodulation Distortion
The analysis of distortion mechanisms in the lter is considerably more complex than
the noise analysis of the previous section. In a communications system, however,
certain simplications can be made by restricting the analysis to 3rd-order intermodulation (IM3) distortion and ignoring the more dicult case of harmonic distortion.
128
Chapter 7: Power-Ecient Active Filters
The virtue of IM3 distortion for analytical purposes is that the distortion products
lie close to the fundamental products as long as the fundamental tones are close to
one another. In what follows, we will assume that the fundamental frequencies are
arbitrarily close to one another.
To begin, we adopt the assumption of small levels of distortion. With this assumption, we can model the distortion of a given transconductor in one of two ways.
In the rst method, we replace the nonlinear transconductor with a linear one and
attribute the distortion products to an additive current source in the output of the
transconductor. Alternatively, we can refer the output distortion current to the input as an equivalent input-referred distortion voltage. The distortion current and
voltage have magnitudes given by
2
j
V
j
jvd j = jV j V
IP3
(7.9)
2
j
I
j
jidj = jI j I
(7.10)
IIP3 = gmVIP3
(7.11)
IP3
where
is a measure of the third-order intercept point of the transconductor. The voltage
and current intercept points are related by gm because they are extrapolated from
low-amplitude distortion measurements, below the onset of gain compression.
Using both of these transconductor distortion models in a simple gyrator results
in the circuit shown in Figure 7.7. This construction illustrates that it is important
to consider both the voltage swing across the gyrator input gm1 as well as the current
swing through the feedback transconductor gm2 .
The greatest distortion will occur when the largest signal voltage appears across
the gyrator. This condition corresponds to the resonance of the inductor with the
other lter elements. Because the inductor voltage and current are in quadrature
7.2: Dynamic Range of the Active Gm-C Filter
2
vd1
129
gm1
2
vd1
,gm2
I
V
i2d2
C
i2d2
(a)
L
(b)
Figure 7.7: Distortion models for a gyrator. (a) Full gyrator. (b) Equivalent circuit.
with one another, and because the fundamental frequencies are arbitrarily close
to each other, we can assume that the resulting distortion products are also in
quadrature. Thus, the total distortion voltage appearing across the inductor at
resonance is
jvdt j2 = jvd1 j2 + (!0LQr )2jid2 j2
(7.12)
where Qr is the Q of the resonance.
Noting that jV j = !0LjI j, and combining (7.8){(7.12), we can express the total
distortion voltage as
jvdt
j2
"
2 g 2
6
Q
j
V
j
= V 4 1 + Qr4 gm1
m2
t
IP3
#
(7.13)
where we have dened
Qt = !R0 L = !0Lpgm1 gm2 :
t
(7.14)
130
Chapter 7: Power-Ecient Active Filters
L
2Rt
Is
L
C
(a)
Re
Ie
(b)
Figure 7.8: Equivalent circuit presented by the lter network to the inductor (a) at
dc, and (b) at resonance.
Finally, to relate the magnitude of the inductor voltage, jV j, to the source voltage,
Vs, consider Figure 7.8, which illustrates the equivalent circuits presented by the lter
to the inductor at dc and at resonance. The lter acts as an impedance transforming
network, causing the termination resistance 2Rt to be transformed to an eective
parallel resistance Re at resonance. The source current Is is also transformed to
an eective current Ie by the inverse square root of the impedance transformation
ratio. Thus,
r
jV j = Ie Re = Re
Vs Is 2Rt
2Rt
(7.15)
or, in terms of Qr and Qt ,
r
jV j = Qr Qt :
Vs
(7.16)
2
By substituting (7.16) into equation (7.13), we can relate the distortion voltage to
the source voltage.
"
#
2 g 2
6
j
V
Q
s j6 Q3r Q3t
2
jvdt j = V 4 8 1 + Q4r gm1 = Vj4Vsj
m2
t
IP3
IP3 ;e
(7.17)
7.2: Dynamic Range of the Active Gm-C Filter
131
where VIP3 ;e is the eective IIP3 voltage, referred to the input of the lter.
This analysis has, so far, assumed that only one inductor is present. With multiple inductors, the analysis becomes more complex. However, we can form a pessimistic bound by assuming that the NL inductors contribute equal amounts of
distortion power. With this assumption, the IIP3 available power is
IIP3 =
2
2
VIP3
VIP3
;e 1
1 :
8Rt NL2 R N 12 (2Q Q ) 23 1 + Q2r gm1 2 2
t L
r t
Q4t gm2
(7.18)
Although this expression is approximate, it yields some insight on how the IIP3 will
depend on the relative magnitudes of various parameters. In particular, NL, Qr
and Qt are set by the desired lter characteristic, and are thus relatively inexible
parameters. Also, note that reducing the impedance level of the lter will result
in improved distortion because voltage levels are reduced for a given signal power.
Finally, the ratio of gm1 and gm2 strongly inuences the linearity because this ratio
determines the current-handling capability of the active inductor.
In the next section we will explore how to optimize the dynamic range of the
lter, based on these results for noise gure and IIP3.
7.2.3 Optimizing Dynamic Range
The condition for minimum noise gure expressed in equation (7.8) determines the
product of gm1 and gm2 . The ratio of these transconductances is a free parameter
that can be used to maximize dynamic range. The peak spurious-free dynamic range
(SFDR) is the dynamic range for which IM3 distortion products and the in-band
noise power are equal. In terms of F and IIP3, we have
IIP 3
SFDR =
FktB
2=3
:
(7.19)
132
Chapter 7: Power-Ecient Active Filters
Using (7.7) and (7.18), we can formulate the SFDR as
2
SFDR = 64
32
3
2
VIP3
4kTB (2NLQr Qt )
3
2
h
Rt ggm2
m1
+
7
i1 5
Q2r gm1 2
Q4t gm2
:
(7.20)
Maximizing this expression is equivalent to minimizing
2g
r m1
Rt ggm2 + Q
Q4t gm2
m1
1
2
:
(7.21)
The condition for minimum noise gure is expressed in equation (7.8). Substituting
this for Rt in (7.21) yields
1 + 1 Q2r
2
2 Q4
gm1
gm2
t
12
:
(7.22)
We can minimize (7.22) subject to a constant-power constraint if we set
D
gm1 + gm2 = P
2N = PD
L
(7.23)
where PD is the power dissipation per gyrator, and is the transconductance per
unit power dissipated in the gyrator. Taking the derivative of (7.22) and setting it
equal to zero yields the condition for maximizing dynamic range, which is that
gm2 = Q2r=3 :
gm1 Q4t =3
(7.24)
So, in general, it is not optimal to have gm1 = gm2 . This is particularly true of highQ lters, which tend to have a larger optimum ratio of the two transconductances
due to larger circulating currents in the inductors at resonance.
7.3: Power-Ecient Transconductors
133
Combining (7.23) and (7.24) with (7.20), we can express the peak SFDR as
h
SFDRpk =
2 i3
PD VIP3
4kTB h
2=3 i :
2NLQr Qt 1 + QQr4=3
t
2
(7.25)
This expression for dynamic range deserves close attention. The denominator is
determined entirely by the lter architecture. In particular, the higher the Q and
the greater the number of inductors, the lower the dynamic range will be, assuming
all other factors are held constant. So, architectures that relax the required lter
order and Q will benet from increased dynamic range. The numerator of the
expression is determined by the transconductor architecture, including PD , the power
dissipated per gyrator. Note that expending more power increases the dynamic
range by lowering the optimum terminating impedance. The form of the numerator
suggests that a good gure of merit for a transconductor architecture is
,m = VIP3
2
(7.26)
which is a dimensionless quantity because has units of V,2 . To maximize ,m, it
is important to select a transconductor architecture that is power-ecient (high ),
linear (high VIP3 ) and low-noise (small ). Choosing such an architecture forms the
subject of the next section.
7.3 Power-Ecient Transconductors
The gyrator transconductor architecture sets the overall performance of the lter.
To implement a low-power lter, it is essential to select a transconductor architecture
that is linear and that maximizes the Gm =Ibias ratio, thereby maximizing .
Class-A techniques are fundamentally limited in their power eciency, as shown
in Figure 7.9. This gure illustrates two possible transconductance curves for a
hypothetical class-A transconductor. The input voltage range can be increased at
134
Chapter 7: Power-Ecient Active Filters
Gm
Gm1
Gm2
V1
V2
V
Figure 7.9: Illustration of the class-A Gm for linearity tradeo.
the expense of Gm by using simple feedback, such as source degeneration. However,
in both cases the maximum input voltage is limited by
Gm1 V1 = Gm2 V2 / Ibias :
(7.27)
In words, the area under the Gm curve is approximately constant. This tradeo
between Gm and linear input voltage range makes class-A techniques unattractive
because the only recourse for increasing the linear range for a given Gm is to increase
the power consumption.
In contrast, class-AB techniques are more exible because the bias current increases in the presence of large signal excitations. Thus, the standing power can be
smaller while maintaining large-signal linearity.
7.3.1 A Class-AB Transconductor
One approach to implementing a power-ecient, linear transconductor in a CMOS
technology is to take advantage of the square-law behavior of the devices themselves.
7.3: Power-Ecient Transconductors
135
I
V1
+
Vb
V2
(a)
Ip
+
+
Vm
Vb
Vb
Im
Vp
(b)
Figure 7.10: A class-AB transconductor. (a) Square-law prototype. (b) Linear
prototype.
If a dierential amplier is constructed out of two square-law ampliers, the resulting
dierential gain is linear. For two such transconductors, with dierential input v,
0 (v + Vb )2 , 0 (,v + Vb )2 = 40 Vbv:
(7.28)
Thus, the output is linearly proportional to the input.
To implement a square-law transconductance characteristic, one might consider
the circuit of Figure 7.10(a). In this circuit, the input voltage, V1 , V2 , is level-shifted
and placed across an NMOS device. To the extent that the NMOS follows a squarelaw, the overall transconductor is square-law. Using two of these transconductors
as shown in Figure 7.10(b), we can construct a linear dierential transconductor.
However, due to velocity saturation and vertical eld mobility degradation, the
136
Chapter 7: Power-Ecient Active Filters
I
V
V
A
I
R
R
(a)
(b)
Figure 7.11: Mobility degradation modeled as series feedback. (a) Equivalent circuit.
(b) System view.
NMOS will exhibit sub-square-law behavior. Velocity saturation can be mitigated
by adopting a longer channel length, but vertical eld mobility degradation depends
on oxide thickness, which is not a exible parameter.
To understand the role of mobility degradation, one can model this eect with
an ideal square-law device and simple series feedback, as shown in Figure 7.11. If
the mobility-degraded current is given by
2
0 (Vgs , VT )
I = 1 + (V , V )
gs
T
(7.29)
then one may model the degradation as the result of an ideal square-law device
degenerated by a resistor of value
R = 2 :
0
(7.30)
In the equivalent system model, the resistor appears as a negative feedback term,
with the forward path, A, representing the desired squaring operation
I = 0 (V )2 :
(7.31)
7.3: Power-Ecient Transconductors
137
1
gm
I
V1
V2
V
k
A
I 0 + kI
I
R
(a)
(b)
Figure 7.12: Cancelling mobility degradation with positive feedback. (a) Modied
transconductance cell. (b) System view.
When viewed from this perspective, it is clear that one remedy for mobility
degradation is positive feedback, as shown in Figure 7.12. The proper amount of
positive feedback can be selected by setting k to
k gmR = g2m = Vod 1 + Vod =22
(1 + Vod )
0
(7.32)
where Vod = Vgs , VT with the inputs balanced. In reality, k must be adjusted
to compensate for second order eects due to other non-idealities, such as channellength modulation and body eect. Thus, equation (7.32) is only approximate. Note
that a practical value of k for this process is about 0.2. As a result, this small amount
of positive feedback does not pose a stability threat.
In contrast to linearization by negative feedback in the class-A case, this approach
linearizes by positive feedback, increasing both Gm and the linear input range with
negligible additional static power consumption.
138
Chapter 7: Power-Ecient Active Filters
7.3.2 A Survey of Transconductor Architectures
To evaluate the merit of this proposed transconductor architecture, we survey several
common transconductors and compare their gures-of-merit. For a fair comparison,
the same tail current (I0 = 1mA) biases each transconductor cell, and relevant
design parameters are swept in simulation to determine what gures-of-merit are
possible with each architecture. Devices with 2-m channel lengths are used in all
simulations. The technology is 0.5-m CMOS.
The ,m parameter can be calculated for each case, using
= GP m
D
i2n;out
= 4kTBG
m
4
2
VIP3
= 3 1
3
(7.33)
(7.34)
(7.35)
where
1 = @@VI V =0
3
3 = @@VI3 :
V =0
(7.36)
(7.37)
The rst of these is the simple dierential pair, shown in Figure 7.13(a) To
improve ,m for a dierential pair, one should either use resistive degeneration or
operate with high current densities. The maximum current density will be set by
the available voltage headroom. For example, with a width of 10m and a tail current
of 1mA, the device in this simulation has a Vgs of about 1.8V. Even with such a high
Vgs , the dierential pair has only a modest gure of merit, ,m , as shown in Figure
7.14. This plot illustrates the diculty in obtaining a ,m of greater than unity,
even with substantial degeneration. Also, note that decreases as ,m improves, so
that the lter impedance increases for a given power dissipation. This increase is
undesirable, because larger signal voltages are implied for a higher impedance level.
7.3: Power-Ecient Transconductors
139
Ip
Ip
Im
Im
Vp
Vm
Vp
Vm
R
I0/2
I0/2
I0/2
I0/2
(a)
(b)
Figure 7.13: Two class-A transconductor architectures. (a) Standard dierential
pair with resistive degeneration. (b) MOSFET-degenerated dierential pair.
Differential Pair FOM
1.6
1.4
R=0
R=500
R=1k
R=1.5k
Gamma
1.2
1.0
0.8
0.6
0.4
0.2
0.0
10
20
30
40 50 60 70
Device Width (um)
80
90 100
Figure 7.14: Figure of merit for a simple dierential pair with source degeneration.
140
Chapter 7: Power-Ecient Active Filters
MOS Degenerated Transconductor FOM
W=50um
W=100um
Gamma
100.0
10.0
1.0
0.1
0.5
1.0
k/k0
1.5
Figure 7.15: Figure of merit for the MOSFET-degenerated dierential pair.
Another approach, rst outlined in [101], is the MOSFET-degenerated dierential pair of Figure 7.13(b). This circuit uses variable conductances in the form of
triode MOSFET devices to degenerate the dierential pair. The simulated ,m for
this architecture is plotted in Figure 7.15. The degenerating devices are k times the
width of the input devices, and the gure shows ,m versus k for two device widths.
It is interesting that this architecture oers, in principle, virtually unbounded ,m
with the proper selection of k. This observation stems from the fact that the thirdorder nonlinearity can be completely cancelled and, since VIP3 is projected from
small amplitudes, it can be made innite. Of course, in reality, the transconductor
will eventually distort, but such large-signal compression behavior is not captured
by ,m .
The class-AB transconductor detailed in the previous section is shown in Figure
7.16. Its gures-of-merit are plotted in Figure 7.17. In this gure, k is the positive feedback factor. The simulations show values of ,m for two dierent device
7.3: Power-Ecient Transconductors
141
Ip
Im
Vp
Vm
I 0 /4 + kIp
I 0 /4 + kIm
Figure 7.16: The mobility-compensated class-AB transconductor.
Class-AB Transconductor FOM
W=50um
W=100um
Gamma
100.0
10.0
1.0
0.1
0.50
1.00
k/k0
1.50
Figure 7.17: Figure of merit for the class-AB transconductor.
142
Chapter 7: Power-Ecient Active Filters
M5
I0
M3
Outp
Inp
M1
M2
Inm
Outm
M4
Figure 7.18: A linearized class-AB transconductor.
widths. Qualitatively, this architecture bears many similarities to the MOSFETdegenerated architecture. The third-order non-linearity can be completely cancelled
with proper selection of k. Note, however, that in this case, the skirts of ,m are
much broader, leading to a larger gure-of-merit if k is misadjusted by a given percentage. Furthermore, the power-eciency, , of the class-AB transconductor is 2-3
times larger, leading to lower lter impedance levels for a given power consumption.
This impedance reduction benets large-signal handling capability in the lter by
reducing the signal voltages for a given source power. Accordingly, we conclude
that the class-AB transconductor oers superior performance compared to simple
resistive degeneration or MOSFET-degeneration.
7.3.3 Transconductor Implementation
A transconductor that applies positive feedback to the task of compensating for
vertical eld mobility degradation is illustrated in Figure 7.18. The voltage buer
7.4: Summary
143
Simulated Gyrator Transconductance
1.10
Relative Gm
1.05
With Positive FB (M5)
Without Positive FB
+/- 10% M5 Variation
1.00
0.95
0.90
-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2
DC Input Voltage (V)
0.3
0.4
Figure 7.19: Normalized transconductance characteristic, with and without positive
feedback.
of Figure 7.12 is implemented with M2{M4, which form a linearized, level-shifting
buer, similar to that used in the IFA. Thus, M1 is the transconducting NMOS device, and M5 implements the positive feedback path by sampling the output current
of M1 and adjusting the bias current to M2.
Figure 7.19 demonstrates the benets of positive feedback in this architecture.
The lower curve shows the nonlinearity in Gm when positive feedback is omitted.
The bowing is nearly eliminated with the addition of device M5, and is relatively
insensitive to reasonable variation in the length of that device.
Eight of these transconductors are used in the on-chip lter, which has a total
power consumption of 9.7mW and a dierential terminating impedance of 2k
. The
lter achieves a peak SFDR of greater than 60dB.
144
Chapter 7: Power-Ecient Active Filters
7.4 Summary
Active lters pose a number of design challenges that have been addressed in this
chapter. The goal of wide dynamic range competes directly with the need for selectivity, as has been demonstrated through a dynamic range analysis of the Gm-C
architecture. Hence, architectural decisions that relax the required lter order and
Q are essential if wide dynamic range is desired on low power consumption.
Much of the dynamic range burden falls naturally on the transconductor that implements the active inductors in the lter. A side eect of the dynamic range analysis
is the formulation of a gure of merit for transconductors that elucidates eective
approaches to maximizing power-eciency. Using this gure of merit as a guide, we
have developed a new transconductor architecture that employs positive feedback
to linearize the transconductance characteristic in a Class-AB transconductor. This
development enables the realization of a 10-mW lter that has 60-dB spurious-free
dynamic range and a bandwidth of 3MHz. Although the lter has a relatively large
dynamic range, it nonetheless limits the dynamic range of the receiver as a whole.
In the next chapter, we present the nal implementation of the complete integrated GPS receiver. As will be shown, this receiver achieves a level of performance
that compares favorably with existing commercial solutions in superior process technologies.
Chapter 8
An Experimental CMOS Global
Positioning System Receiver
T
HE previous chapters present design methodologies for some of the critical
building blocks in a CMOS radio receiver. To put these ideas into practice,
we have implemented a complete GPS receiver that comprises the LNA, mixers,
active lters, limiting ampliers and comparators necessary to render the complete
receiver signal path. In addition, the receiver includes an on-chip phase-locked loop
(PLL) for synthesis of the rst local oscillator. The details of the PLL are presented
elsewhere [59].
In this chapter, we explore the implementation and testing of the receiver signal
path. A comprehensive description of the signal path and biasing circuit design is
presented in Sections 8.1{8.6. Then, complete experimental results are presented in
Section 8.7. The chapter concludes with a summary in Section 8.8.
8.1 Low-Noise Amplier
The rst block in the signal path is the low-noise amplier. Figure 8.1 shows the
complete schematic of the LNA, including biasing circuitry.
The LNA uses a dierential architecture to increase its immunity to commonmode interference from substrate or supply perturbations. The input stage, M1{M8,
145
146
Chapter 8: An Experimental CMOS Global Positioning System Receiver
LNA
CMFB
gm-Bias
M20
R8
L5
L6
Outp
C4
C1
C3
M23
M24
M22
Outm
M9
L3
M21
R9
M18
M19
R11
M10
L4
C2
R1
M25
M5
M7
R2
R4
M8
M14
M6
R5
R6
R7
Inp
M26
M16
M17
Inm
R3
M27
M1
M3
L1
M29
M15
L2
M4 M2
M11
M28
R10
M12
M13
Figure 8.1: The low-noise amplier.
Table 8.1: LNA Elements
Device
M1{M2
M5{M6
M9{M10
M12{M13
M16{M17
M20{M21
M25{M26
M28
M30
R2{R5
R8{R9
R11
C3{C4
L3{L4
Total Power
Value
240/0.5m
240/0.5m
240/0.5m
30/1.2m
60/1.2m
30/1.55m
90/1.55m
240/0.5m
30/0.5m
5k
5k
20k
8pF
5.5nH
15.75mW
Device
M3{M4
M7{M8
M11
M14{M15
M18{M19
M22{M24
M27
M29
R1
R6{R7
R10
C1{C2
L1{L2
L5{L6
Bias Power
Value
20/0.5m
20/0.5m
540/1.2m
120/1.2m
120/1.2m
120/1.55m
30/0.5m
45/1.55m
2.5k
51k
500
2pF
1.2nH
5.8nH
3.5mW
M30
8.1: Low-Noise Amplier
147
is a cascode amplier that delivers its output current into a tuned load formed by
spiral inductors L3{L4 and the gate capacitances of the second stage, M9{M10.
AC coupling between the stages via C1{C2 allows for the bias current in the input
stage to be shared with the output stage, thereby reducing power consumption. The
second stage drives another pair of tuned loads formed by L5{L6 and the parasitic
capacitances at the output nodes.
To bias the LNA, a common-mode feedback (CMFB) circuit drives the voltage at
the gates of the cascoding devices, M5{M8, to a desired level. The cascode common
mode voltage is measured by R4{R5 and compared to a reference voltage generated
by resistive divider R2{R3. These two voltages are equalized by feedback action
of an operational amplier, M14{M21. The resistive divider senses the gate-source
voltage of the input devices through resistors R6{R7. Thus, the nal drain-source
voltages of the input devices are proportional to their own gate-source voltages.
Capacitor C3 bypasses this resistor network to the supply at radio frequencies.
Because the CMFB technique requires measurement of the source voltages of
the cascoding devices, the cascode is split into two parallel branches on each side
of the amplier. This partitioning permits reduced source-drain parasitics in the
outer branches because a contact is not required between the input devices and
their cascoding counterparts. Thus, the common-mode sensing inner branches use
smaller device widths. This reduction in capacitance benets the noise performance
by increasing the high-frequency output impedance of the input devices, in turn
reducing the noise contribution of the cascode devices.
Note that all of the voltages in the LNA core are set with respect to the positive
supply, so that variations in supply voltage do not aect the quiescent currents in the
amplier. The gates of M9{M10 are set at supply potential so that they can swing
above the supply when signal is applied, thus making ecient use of the available
voltage headroom. The outputs also swing above the supply due to the inductive
biasing of the drains of M9{M10.
The bias current for the LNA is provided by a dedicated bias circuit formed
by M23{M30 and R10{R11. This type of reference generates a bias current that
makes the transconductance, gm27 , proportional to a reference conductance, 1/R10.
148
Chapter 8: An Experimental CMOS Global Positioning System Receiver
To illustrate the principle of operation, assume that M27 and M28 are square-law
devices and that M28 is much wider than M27 so that it operates on a very small
overdrive voltage. The positive feedback loop implemented by the current mirror
formed by M23-M26 ensures that both M27 and M28 conduct the same current. If
we equate the currents in the two branches, we nd that
1 C W27 (V , V )2 = Vgs 27 , Vgs 28 :
2 n ox L27 gs 27 T
R10
(8.1)
Now, if M28 is a wide device, then it's gate to source voltage is approximately equal
to VT . Then, (8.1) can be simplied:
2 :
27
nCox W
(
V
gs 27 , VT ) =
L
R
27
10
(8.2)
The lefthand side of this equation is the transconductance of M27. So, the bias
circuit generates the necessary current for the transconductance of M27 to follow
2/R10. This circuit is useful for reducing the variation of the LNA gain and input
matching over supply and temperature. In addition, the use of a separate bias cell
prevents bias lines from degrading isolation between the PLL and the LNA inputs.
Devices M29{M30 and R11 provide a simple startup circuit to eliminate an undesired
zero-current state.
8.2 Voltage-Switching Mixer and LO Drivers
The LNA output drives the inputs of two voltage-switching mixers, driven by quadrature phases of the local oscillator. One of these mixers is shown in Figure 8.2,
accompanied by its LO driver.
As discussed in Chapter 6, the mixer uses four MOS voltage switches that connect
the RF input to the IF output with alternating polarity. The change in polarity is
controlled by the local oscillator via the LO driver circuit.
This circuit is a simple cascode amplier, formed by M1{M4, with inductive loads
L1{L2 that resonate the total capacitance at the driver output nodes, including the
8.2: Voltage-Switching Mixer and LO Drivers
Mixer
149
gm-Bias
LO Driver
M5
M6
M11
M12
R7
L1
RFp
LOp
LOp
LOm
LOm
M3
C1
RFm
M4
C3
R1
IFA
M10
L2
C2
R2
Inm
M13 M14
M18
Inp
R3
M2
M1
R4
M7
C4
M8
M15 M16
M9
R5
R6
Figure 8.2: Mixer and quadrature LO driver.
Table 8.2: Mixer/LO Driver Elements
Device
Value
Device
M1{M4
80/0.5m M5
M6
192/1.2m M7
M8
768/1.2m M9
M10{M12 120/1.55m M13{M14
M15
30/0.5m M16
M17
30/0.5m M18
R1{R2
20k
R3{R4
R5
20k
R6
R7
20k
C1{C2
C3
2pF
C4
L1{L2
14.2nH
Total Power 6.83mW Bias Power
Value
384/1.2m
48/1.2m
96/1.2m
90/1.55m
240/0.5m
45/1.55m
40k
500
0.92pF
6pF
1.67mW
M17
150
Chapter 8: An Experimental CMOS Global Positioning System Receiver
input capacitance of the four switches in the mixer. Figure 8.2 shows the quadrature
version of the LO driver, with C1 and C2 serving to establish the LHP pole and RHP
zero that result in a 90 phase shift. The in-phase version of the LO driver omits
C1 and C2, and the inputs of the two drivers are directly connected to each other.
Because the pole/zero locations depend on gm, it is important to regulate gm
to be relatively constant so that a constant phase shift is obtained. Thus, the LO
driver also uses a self-biased constant-gm circuit, identical to the one in the LNA.
The driver accepts the bias current via a current mirror formed by M7{M9. M9 is
relatively wide so that its gate voltage is approximately equal to VT . Hence, the
current through M7 is proportional to VT . This current provides the bias for the
cascode and input devices through a pair of resistor dividers, R1{R4, so that all bias
voltages track VT , thus providing a measure of bias stability. Capacitor C3 bypasses
the cascode at radio frequencies.
8.3 Intermediate Frequency Amplier
The output of the mixer is directly connected to the input of the intermediate
frequency amplier (IFA). To minimize signal currents owing in the mixer switches,
the IFA should present a relatively high input impedance. In addition, the output
impedance of the IFA should be well-dened for use as a termination resistor for
the active lter that follows. Finally, the IFA should make ecient use of its bias
current while providing a linear transfer characteristic, as discussed in Chapter 7.
Figure 8.3 shows an amplier that meets these requirements. Devices M1-M8
form a linearized voltage buer that, through feedback action, causes a constant
current to ow from drain to source in devices M1{M2. Thus, the input voltage
experiences a nearly constant level shift and is placed across the input resistors,
R3{R4. This remains true for any input amplitude until the peak current owing in
the resistors is equal to the bias current supplied by M22{M25. Beyond this point,
the feedback breaks down, and the amplier saturates.
Because the linear signal current through R3{R4 must ow in devices M5{M6, it
is a simple matter to mirror this current to the output loads with devices M9{M10.
8.3: Intermediate Frequency Amplier
151
M22
M24
M23
M25
M26
C2
M27
I0
R5
Inp
R1
R3
M11
M7
M9
M14
M5
M15
R2
R7
M4
M13
M1
Outp
R6
C1
M3
M2
Outm
Inm
R8
R4
M12
M8
M17
M21
C3
M10
M6
M16
M20
M18
Figure 8.3: Intermediate frequency amplier.
Table 8.3: IFA Elements
Device
M1{M6
M9{M10
M13
M15
M17{M21
R1{R2
R5{R6
R8
C2{C3
Total Power
Value
96/1.2m
192/1.2m
60/0.5m
48/1.2m
48/1.2m
15k
1k
2k
1pF
6.18mW
Device
M7{M8
M11{M12
M14
M16
M22{M27
R3{R4
R7
C1
I0
Bias Power
Value
48/1.2m
96/1.2m
12/1.2m
12/1.2m
192/1.2m
250
1.5k
4pF
243A
1.2mW
M19
152
Chapter 8: An Experimental CMOS Global Positioning System Receiver
Simulated IFA Available Power Gain
Available Power Gain (dB)
30
20
10
0
-10
-20
-30
-40
-0.2
-0.1
0.0
0.1
DC Input Voltage (V)
0.2
Figure 8.4: Simulated gain characteristic of the IFA.
The feedback results in a very linear gain characteristic with a sharp saturation
behavior, as illustrated in Figure 8.4, which shows the simulated available power
gain of the amplier. Because there is only one pair of high-impedance nodes in the
current feedback loop, the amplier does not require frequency compensation, and
its step response exhibits no overshoot.
Note that, because the mixer is dc coupled to the IFA input, the bias circuit
that sets the dc voltage for devices M1{M2 also serves to set the dc potential for
the mixer devices in Figure 8.2. Device M13 in Figure 8.3 conducts a small current
so that the mixer devices are biased approximately one threshold voltage below the
positive supply. The choice of bias voltage optimizes the switching point of the mixer
devices, BLO , as described in Chapter 6. Capacitor C1 bypasses the bias device at
high frequencies.
8.4: Active Filter
Inp
153
C3
C7
C11
C13
Outp
C1
C5
C9
C2
C6
C10
R1
Inm
C12
C14
C4
C8
Outm
Figure 8.5: Active Gm {C lter. The missing input termination resistor is supplied
by the output resistance of the preceding IFA stage.
8.4 Active Filter
The output of the IFA directly drives the input of the active lter, whose schematic
is shown in Figure 8.5. In this gure, the required common-mode feedback circuitry
has been omitted for clarity. Each pair of dierential nodes in the lter, with the
exception of the two input nodes, requires common-mode regulation, as will be
discussed shortly.
The lter is based on an elliptical L-C ladder prototype with a cuto frequency
of 3.5MHz. The inductive elements of the lter are implemented with dual gyrators
and capacitors C11{C14. All of the capacitors in the lter, with the exception of
bridging capacitors C3{C4 and C7{C8, are tied to ground so that they can serve as
common-mode feedback compensation.
The transconductor used for the gyrators is shown in Figure 8.6. Devices M1{
M2 are the square-law transconductors that are driven by linearized level-shifting
buers M3{M8. The output currents from M1{M2 are sampled and fed-back to the
buers via M15{M16. The feedback factor is adjusted to approximately cancel the
mobility degradation nonlinearity in M1{M2, thus linearizing the transconductor.
The linearized output currents are mirrored to the transconductor outputs via
M11-M12. In addition, the signal currents in M7{M8 are mirrored to pull-down
devices M13{M14. This push-pull action boosts the transconductance by a factor
154
Chapter 8: An Experimental CMOS Global Positioning System Receiver
Table 8.4: Filter Capacitors
Capacitors 600fF Units (ea.) Value (ea.)
C1{C2
84
50.4pF
C3{C4
2
1.2pF
C5{C6
173
103.8pF
C7{C8
5
3.0pF
C9{C10
81
48.6pF
C11{C12
144
86.4pF
C13{C14
139
83.4pF
Total
1256
753.6pF
Table 8.5: Transconductor Elements
Device
M1{M4
M7{M8
M13{M14
M17
M20
M23{M25
C1{C2
Total Power
Value
5/1.55m
50/1.2m
50/1.2m
18/1.2m
18/1.2m
25/1.2m
0.8pF
1.07mW
Device
M5{M6
M9{M12
M15{M16
M18{M19
M21{M22
R1{R2
C3{C4
Bias Power
Value
25/1.2m
25/1.2m
5/1.2m
15/1.2m
15/1.2m
1k
5pF
0.18mW
of two without additional power consumption. Devices M19 and M21 provide static
bias current to reduce the standing current in M7 and M8, thereby adjusting the
static imbalance in the currents in the output drivers, M11{M12 and M13{M14.
This dierential transconductor requires common-mode feedback. A simple CMFB
circuit is shown in Figure 8.7. The common-mode voltage at the transconductor
outputs is measured with two dierential pairs, M1{M4, whose output currents are
summed. Dierential outputs produce cancelling error currents in the two transconductors; thus, only common-mode disturbances produce a net error. This error is fed
back to the gates of PMOS devices M8{M9, adjusting the total pull-up current of
8.4: Active Filter
M11
155
M9
M15
M23
M24
M6
C1
C2
R1
R2
I0
Inp
Inm
M1
M3
M4
M7
Outm
M2
M8
M20
M13
M22
M12
M25
C4
M5
Outp
M10
M16
M21
M14
M19
C3
M18
M17
Figure 8.6: Gyrator transconductor.
M5
M7
M6
R1
M8
I0
M9
M1
M3
M4
M2
Outp
Outm
I1
M12
M11
M10
Figure 8.7: Common-mode feedback circuit for the transconductor.
156
Chapter 8: An Experimental CMOS Global Positioning System Receiver
Table 8.6: Transconductor CMFB Elements
Device
M1{M4
M7
M10
R1
Total Power
Value
5/0.5m
20/1.2m
10/2.6m
33.75k
81W
Device
Value
M5{M6
10/1.2m
M8{M9
80/1.2m
M11{M12 20/2.6m
I1
27A
Bias Power 16W
the transconductor to regulate the common-mode voltage. The reference voltage for
this circuit is derived from a bandgap-reference current, I1, which produces a nearly
constant voltage across resistor R1. To frequency-compensate the CMFB circuit,
the lter capacitors are referenced to ground so that a dominant pole is established
at the CMFB output nodes.
To generate the appropriate bias current for the lter, we can borrow the concept
of using positive feedback to slave gm to a reference resistor. In this case, however, a
replica transconductor is used in a feedback loop so that its total transconductance,
Gm , is slaved to a reference resistor, R. A circuit that achieves this purpose is shown
in Figure 8.8.
This circuit accepts a single reference current, I0, from the bandgap reference,
and produces two output currents, Ibg and Igm. The rst of these is just a scaled
version of the bandgap current for use in the CMFB circuitry in the lter. The
second has a more complex origin that requires a detailed explanation.
Devices M1{M10 are a half-circuit replica of a single transconductance stage in
the lter. This replica is in a positive feedback loop with M11 and R1, and the loop
is closed with devices M12{M13, which set the bias current for the whole circuit.
Due to the positive feedback, this circuit nds a stable operating point when the
total bias current reaches a level that causes the transconductance of the replica to
be proportional to the reference resistor, R1. Note that resistor R2 sets the gate
potential of M1 and M4 to the nominal common-mode voltage of the lter, so that
body eect is accounted for. The resulting bias current is supplied to the lter
8.4: Active Filter
157
M5
I0
C1
M6
M12
M7
M13
R2
Igm
M2
R4
Ibg
M14
M4
M15
M1
M11
R3
R1
M23
M19
M24
M20
M21
M3
M22
C2
M16
M17
C3
M10
M9
M18
M8
Figure 8.8: Replica biasing of the lter transconductor.
Table 8.7: Replica Bias Elements
Device
M1
M3
M5
M7
M9{M10
M12{M14
M17
M19{M24
R2
R4
C2{C3
Total Power
Value
5/1.55m
50/1.2m
25/1.2m
25/1.2m
15/1.2m
25/1.2m
12/1.2m
12/1.2m
33.75k
20k
20pF
911W
Device
M2
M4
M6
M8
M11
M15{M16
M18
R1
R3
C1
I0
Bias Power
Value
25/1.2m
5/1.55m
5/1.2m
18/1.2m
40/1.55m
50/1.2m
15/1.2m
5.8k
40k
40pF
27A
|
158
Chapter 8: An Experimental CMOS Global Positioning System Receiver
transconductors via current mirror taps, as shown with M14 in the gure. Because
the termination resistors in the lter are made of the same material as the reference
resistor, the lter shape is well regulated by this circuit. There will, however, be
variation in the resulting lter cuto frequency as the RC product changes with
process. Because the RC product may change by 15%, the lter must be designed
to have a slightly larger nominal bandwidth than absolutely necessary. In this design,
the lter actually has a nominal bandwidth of 3.5MHz. With process variations, the
bandwidth may drop as low as 3.0MHz or rise as high as 4.0MHz. The minimum
sampling frequency is thus 8MHz to ensure that no unwanted aliasing occurs.
The replica bias circuit has an undesirable stable state in which the drain of M7
sits at the positive supply potential, thereby shutting o the output current, Igm.
Startup circuitry comprising M15{M18 detects and eliminates this unwanted state.
Device M16 is a switch that connects a fraction of the reference bandgap current
via M17 to the source of M11 during startup. In the zero-current state, the gate
of M15 is at the positive supply potential, and M18 is o. Thus, M15 pulls up
on the gate of M16, turning it on and passing current from M17 to the source of
M11. As M17 pulls down on M11, the circuit begins to start up. Once a stable
state has been reached, M18 pulls down on the gate of M16 through R3, shutting
o M16 and depriving M11 of the bandgap current. This action eectively removes
the startup circuit from operation, leaving the replica circuit unperturbed after the
startup period is complete.
8.5 Limiting Amplier and Comparator
The nal two stages in the receiver signal path are the limiting amplier and output
comparator, shown in Figure 8.9.
The limiting amplier is a ve-stage amplier that uses simple dierential pairs.
The stages are ac coupled to one another to prevent the propagation of dc osets
through the chain, with the exception of the very rst stage, which is dc coupled
to the lter output. With a 2-MHz IF frequency, the lower pole of the ac coupling
should be somewhat below 1MHz to prevent distortion of the C/A code main lobe.
8.5: Biasing Details
159
In
D Q
Limiting Amplifier Chain
Out
CLK
Figure 8.9: Five-stage limiting amplier and output comparator.
Table 8.8: Limiting Amplier Elements
Device
M1{M2
M4{M5
M8
R3{R4
C1{C2
Total Power
Value
24/1m
5/2m
5/2m
90k
3pF
305W
Device
M3
M6{M7
R1{R2
R5
I0
Bias Power
Value
90/2m
8/2m
30k
100k
5A
9.2W
The limiting amplier nominally provides 96dB of voltage gain and 78dB of available
power gain, which is more than sucient to amplify system thermal noise up to a
detectable level for the comparator that follows. Any gain in excess of this value
would be wasted. A schematic of one of the limiting amplier stages is shown in
Figure 8.10.
The comparator is a standard Yukawa latch [102] that accepts a single clock
supplied from o chip and that is driven directly by the output stage of the limiting
amplier. The comparator is clocked at about 16MHz for an oversampling factor of
about two. The output of the comparator drives a dierential output driver with
on-chip 400
loads. The small dierential swings at the driver outputs mitigate
possible interaction between the output driver and the sensitive LNA input due to
substrate coupling. The schematic of the comparator and output driver is shown in
Figure 8.11
160
Chapter 8: An Experimental CMOS Global Positioning System Receiver
M6
M8
M7
R1
R2
Outm
I0
Outp
C1
C2
Inp
Inm
M1
R3
M2
M5
R4
M4
M3
R5
Figure 8.10: A single stage of the limiting amplier.
Yukawa Latch
M1
M17
M3
M4
Output Driver
M2
Inm
M11
R1
Inp
M5
Outp
M6
CLK
R3
Outm
M13
CLK
M18
R2
M14
I0
CLK
M7
M8
M9
M10
M12
M15
Figure 8.11: The output latch and output driver.
I1
M16
8.6: Biasing Details
161
Table 8.9: Latch / Output Driver Elements
Device
M1{M2
M5{M6
M8{M9
M11
M13{M14
M16
M18
R3
Total Power
Value
48/1.55m
100/1.55m
32/1.55m
10/1.55m
150/1.55m
30/1.55m
5/1.55m
38.5k
3.05mW
Device
M3{M4
M7
M10
M12
M15
M17
R1{R2
I1
Bias Power
Value
40/1.55m
20/1.55m
20/1.55m
5/1.55m
120/1.55m
10/1.55m
400
243A
0.6mW
Note that although the vast majority of system gain occurs in these two blocks,
they occupy less than one eighth of the total die area of the chip. No signs of
instability were observed, despite the large gain.
8.6 Biasing Details
With the exception of the LNA, lter and LO drivers, all of the receiver blocks derive
their bias from one of two on-chip bandgap references. A simplied circuit diagram
of the bandgap reference is shown in Figure 8.12.
Two substrate PNP devices, Q1{Q2, arrayed with 8:1 emitter area ratios, provide a proportional-to-average-temperature (PTAT) voltage reference that causes
a PTAT current to ow in resistors R1 and R2. An active current mirror, using
devices M1{M6, ensures that the two current branches conduct identical PTAT currents. This structure is preferable to a passive current mirror, which suers from
inherent current osets, thus degrading the stability of the reference. In this circuit, as long as M3{M6 possess the same current densities, the amplier will have
no systematic oset. This condition is ensured by devices M8{M10, which bias the
operational amplier with the same PTAT current produced by the bandgap. All
systematic osets are thereby eliminated. Because this is a self-biased technique,
162
Chapter 8: An Experimental CMOS Global Positioning System Receiver
Bandgap Core
M3
Buffer Amplifier
M4
M13
M14
M15
M16
C1
M8
M5
M6
C2
R7
M17 M18 M19
M7
R4
R3
M1
R1
M2
R5
R6
R2
M20 M21 M22
M25
Ib
M10
M9
Q1
Q2
M11
M12
M24
R8
M23
Figure 8.12: Bandgap reference circuit.
Table 8.10: Bandgap Reference Elements
Device
M1{M6
M8
M10
M13{M18
M20{M21
M23
R1
R3{R4
R7
C1{C2
Total Power
Value
80/1.2m
80/1.2m
80/1.2m
60/1.2m
60/1.2m
20/1.2m
6.25k
4.5k
150
16pF
1.87mW
Device
M7
M9
M11{M12
M19
M22
M24
R2
R5{R6
R8
Ib
Bias Power
Value
60/0.5m
40/1.2m
40/1.2m
180/1.2m
180/1.2m
40/1.2m
6.92k
6k
15k
243A
|
8.7: Experimental Results
163
the threat of a zero-current state must be removed by appropriate startup circuitry.
Device M7 and resistor R3 serve this purpose, and resistor R4 balances the amplier
so that the drain voltages of M5{M6 are nominally equal.
The voltage appearing at the gate of M2 is the sum of one Vbe , which is complementary-to-average-temperature (CTAT), and a PTAT voltage across R2. By proper
ratioing of R1 and R2, the resulting voltage is constant with temperature. The
static supply rejection of this circuit is comparable to the temperature variation of
the bandgap voltage due to the balance maintained by the active current mirror.
A buer amplier accepts the bandgap voltage as an input and buers it across
a resistor, R8, thus producing a current that is proportional to the bandgap voltage
that can be supplied to various receiver circuit blocks. Just as in the bandgap core
itself, attention to systematic osets is crucial for providing a stable current.
Again, to balance out any systematic osets, the buer amplier uses its own
output current as its tail current. Thus, M13{M19 can be designed to conduct
identical current densities, equalizing the drain voltages of M15{M16. Resistor R5
provides a level shift to generate the cascode gate voltages for M20{M22, and R6
serves to equalize the drain voltages of M11 and M12. Due to the use of self-biasing
in this amplier, a startup circuit is again required, and a simple solution is found in
M25, which initializes current ow through R8 and pulls down on the gate of M17
to start the amplier. Elements C1{C2 and R7 provide loop stability compensation
for the bandgap core and buer amplier.
This bandgap circuit provides 27-A and 243-A bias current taps for distribution throughout the receiver.
8.7 Experimental Results
The GPS receiver has been implemented in a 0.5-m CMOS process and a die
micrograph is shown in Figure 8.13. The layout occupies 11.2mm2 and uses 16
spiral inductors in the RF and PLL sections. These spirals use patterned ground
shields for improved quality factor and reduced crosstalk between spirals [52]. A
comparison between simulations and measurements of the spiral inductors is shown
164
Chapter 8: An Experimental CMOS Global Positioning System Receiver
Gm-C Filter
B
G
R
Lim.
Amp.
C
Lim.
Amp.
C
IFA
Mix.
LOI
LNA
Mix.
IFA
PLL
LOQ
Gm-C Filter
B
G
R
Figure 8.13: Die micrograph of the GPS receiver.
8.7: Experimental Results
165
Table 8.11: Spiral Inductors
Simulated
Measured
Inductance Q Inductance Q
1.2 nH 6.7 1.4 nH 6.8
5.6 nH 7.6 4.8 nH 6.6
5.9 nH 7.4 5.6 nH 6.6
6.9 nH 7.0 6.6 nH 6.8
10.0 nH 4.7 9.5 nH 4.5
10.0 nH 6.3 10.3 nH 6.0
14.3 nH 5.1 14.5 nH 5.2
in Table 8.11, indicating excellent agreement. The discrepancies for the second and
third inductors in the table arise mostly from inconvenient connecting stubs on the
test structures whose parasitic contributions are not de-embedded. The simulation
model used in this work is described in [103].
The entire signal path of the chip is dierential, and careful attention is paid
to symmetry throughout the layout. The I and Q channels are also symmetrically
placed about the horizontal centerline of the chip. To reduce interaction between
the LNA and PLL circuitry, separate supplies are run from the outer supply ring,
where extensive on-chip capacitive bypassing is used (about 1.2nF, in all).
The LNA is also laid out as a separate test structure so that its noise gure can
be measured independently. The result is shown in Figure 8.14. The LNA has a
noise gure of 2.4dB at 1.575GHz with 4.9mA of bias current in the amplier core,
suggesting that an equivalent single-ended amplier would consume 2.45mA of bias
current. The input return loss was better than 20dB for this noise gure measurement. Based on simulations of the LNA with models that include the induced gate
noise and that have been veried against S-parameter measurements, this noise gure corresponds to a of approximately 1.2. Note that this value of , while greater
than the long-channel value of 2/3, is actually smaller than values reported in [2].
One possible explanation is that lightly-doped drain (LDD) structures in modern
166
Chapter 8: An Experimental CMOS Global Positioning System Receiver
Measured LNA Noise Figure
3.0
NF = 2.4dB @ 1575MHz
Noise Figure (dB)
2.8
Ibias = 4.9mA
2.6
2.4
2.2
2.0
1550
1560
1570
1580
Frequency (MHz)
1590
1600
Figure 8.14: Measured LNA noise gure.
MOSFET devices help to reduce the electron temperature near the drain end of the
channel, thereby controlling the increase in [87].
Several test points are located on the die for measuring intermediate points along
the signal path. In particular, an output buer amplier permits signal path measurements after the lter and before the limiting amplier. Most of the signal path
data are based on measurements at this test point.
Figure 8.15 shows the signal path frequency response as measured before the
limiting amplier. The simulated and measured responses agree very well. The
lter exhibits about 77dB of stopband rejection and less than 1dB of passband
peaking. Mismatch in I and Q amplitudes is observed, some of which is attributed
to board components. Unfortunately, a direct measurement of the on-chip I and Q
matching is not possible, but the success or failure of image rejection can be readily
ascertained by measuring the post-detection SNR.
A spot noise gure of 2.8dB is also measured at the output of the lter. This
number is in good agreement with the predicted value of 2.9dB from design simulations of the individual receiver blocks. The use of a 1-bit quantizer causes an
8.7: Experimental Results
167
Signal Path Frequency Response
Passband Detail
Frequency Response (dB)
0
1
0
-20
-3
1.0
-40
3.5
I Channel
Q Channel
Simulated
-60
-80
0
5
10
15
Frequency (MHz)
20
Figure 8.15: Measured signal path frequency response.
SNR degradation that can be accounted for by increasing the eective noise gure
to 4.5dB.
To determine the linearity of the system, two tests are performed: a two-tone
IM3 test, and a 1-dB blocking desensitization test. These are shown in Figures 8.16
and 8.17.
For the IM3 test, two in-band test tones are applied to the system at 1.57562GHz
and 1.57542GHz. Note that the classical behavior of the IM3 products breaks down
above an available source power of {51dBm. The subsequent rise in distortion may
be attributed to the rapid increase in Gm observable in the lter transconductor
characteristic of Figure 7.19 when the input amplitude exceeds a certain value. Because the received signal power in the GPS system is very low, an extrapolation
from low source powers is most relevant, yielding a {25-dBm input referred IP3.
This number is set almost entirely by distortion in the active lter and could thus
be improved at the expense of increased lter power consumption.
A more relevant performance measure for this system is the 1-dB blocking point.
In Figure 8.17, a single out-of-band blocker is applied to the system, and its power
Chapter 8: An Experimental CMOS Global Positioning System Receiver
Signal Path 3rd Order Intermodulation
20
Output Power (dBm)
0
-20
3
e=
op
-40
Sl
-60
-80
-100
-60
-50
-40
-30
Input Power (dBm)
-20
Figure 8.16: Results of a two-tone IM3 test.
Receiver 1-dB Blocking De-Sensitization
(No Front-End RF Filter)
-20
Blocking Source Power (dBm)
168
-30
-40
-50
-60
INMARSAT
UPLINK BAND
8
10
20
30
40
Offset Frequency (MHz)
50 60
Figure 8.17: Measured 1-dB blocking desensitization point.
8.7: Experimental Results
169
Receiver Output Spectrum
(Pre-Correlation)
0
Magnitude (dBFS)
-20
HP8664A
Spur
-40
-60
-80
-100
-120
0
1
2
3
4
5
Frequency (MHz)
6
7
8
Figure 8.18: FFT of the I channel output bit sequence.
is increased until a 1-dB reduction in the in-band SNR is observed. The band of
frequencies that presents the greatest blocking threat is the INMARSAT uplink
band, positioned at an oset of 35-MHz to 55-MHz from the GPS center frequency
of 1.575GHz. At the lower edge of this band, the receiver has a 1-dB blocking point
of {35-dBm available source power. Note that no external RF ltering is used in
making this measurement. With a reasonable lter, this number would improve by
15{20dB in the nal system. The measured blocking performance is consistent with
a PLL phase noise of better than {135dBc/Hz at 35-MHz oset.
With the signal path and PLL veried separately, the full receiver is nally
tested with a simulated GPS signal applied to the input at {130-dBm available
source power. The 1-bit digital output stream is captured for the I and Q channels
and digitally downconverted using a noncoherent back end to reduce the computational complexity. The use of a noncoherent back end causes an additional SNR
degradation that elevates the eective noise gure to about 6.7dB.
A fast Fourier transform (FFT) of the I channel is shown in Figure 8.18. Despite
the de-correlating eects of the limiter, the lter characteristic is still visible as an
170
Chapter 8: An Experimental CMOS Global Positioning System Receiver
Normalized Cross-Correlation Magnitude
Non-Coherent Receiver Output
Gold Code Cross-Correlation
0.025
0.020
SNR = 17dB
0.015
0.010
0.005
0.000
-512 -384 -256 -128 0 128 256 384 512
Code Phase
Figure 8.19: Cross-correlation at the receiver output.
increase in the noise oor from 1{3MHz. The spectrum is free of spurs, with the
exception of a single spur attributable to one of the bench-top references used for
the PLL.
The downconverted bit sequences are correlated with a reference copy of the
GPS spreading code and the resulting cross-correlation as a function of code phase
is plotted in Figure 8.19. By comparing the magnitude of the correlation peak with
the variance of the o-peak cross-correlation, one concludes that the output SNR is
about 17dB. Recalling that a received SNR of {19dB is expected, with a processing
gain of 43dB and an eective noise gure of 6.7dB, we expect
SNR = ,19dB + 43dB , 6:7dB = 17:3dB
(8.3)
which agrees very well with the measured result of 17dB. The conclusion is that the
I/Q matching in the system is sucient for eective cancellation of the image noise.
Table 8.13 summarizes the receiver performance.
8.8: Summary
171
Table 8.12: Comparison with Commercial GPS Receivers.
Sony
GEC Plessy
SiRF
Specication
This Work
(JSSC Apr'97)
GP2010
GRF-1
LNA NF
2.4dB (int)
2dB (ext)
2dB (ext)
(ext)
Chip NF
2.9dB
6.1dB
10dB
|
IIP3
-25dBm
-14.5dBm
|
|
Avail. Gain
103dB
107dB
106dB
|
ADC
1-bit
1-bit
2-bit
2-bit
Power
115mW @ 2.5V 81mW @ 3V 200mW @ 3V 500mW @ 5V
Technology 0.5m CMOS 15GHz Bipolar
Bipolar
|
Missing
|
2 Filters
2 Filters,
Filter, LNA
LNA, PLL LF LNA, PLL LF
In addition, Table 8.12 presents a comparison between the experimental results
of the present work and several commercial GPS receivers that are available today.
This comparison illustrates that the CMOS GPS receiver achieves similar or better
performance in a less expensive technology with more complete system integration
onto a single chip.
8.8 Summary
In summary, this chapter describes the implementation of a complete CMOS GPS
receiver that includes all necessary active blocks in the RF and analog signal path,
plus a PLL for LO synthesis. The details of the PLL are presented elsewhere [59].
The signal path successfully applies the low-IF architecture by exploiting details of
the GPS signal structure to permit a reduction in the I/Q matching requirements
and a relaxation of the channel ltering problem.
The nal system consumes 115mW from a 2.5-V power supply and occupies
11.2mm2 of die area in a 0.5-m CMOS process. It is capable of detecting a {130dBm GPS signal with a noncoherent back-end SNR of 17dB.
172
Chapter 8: An Experimental CMOS Global Positioning System Receiver
Table 8.13: Measured GPS receiver performance.
Signal Path Performance
LNA Noise Figure
LNA S11
Coherent Receiver NF
IIP3 (Filter-limited)
Peak SFDR
Filter Cuto Frequency
Filter Passband Peaking
Filter Stopband Attenuation
2.4dB
{20dB
2.8dB
{25dBm @ {51dBm Ps
56dB
3.5MHz
1dB
52dB @ 8MHz
68dB @ 10MHz
Pre-Filter Avail. Power Gain 28dB
Pre-Filter Voltage Gain
41dB
Total Avail. Power Gain
103dB
Total Voltage Gain
131dB
Non-Coherent Output SNR 17dB
LO Leakage @ LNA Input
< {72dBm
Power Dissipation
Signal Path
PLL / VCO
Supply Voltage
79mW
36mW
2.5V
Implementation
Die Area
Technology
11.2mm2
0.5-m CMOS
Chapter 9
Conclusions
T
HIS dissertation has examined in detail a number of issues related to integrated radio receivers, particularly in the context of CMOS technologies. The
techniques presented in earlier chapters have enabled the implementation of a lowpower, high-performance CMOS GPS receiver in a 0.5m technology. This receiver
consumes less power and yields comparable or better performance with a higher level
of integration than most commercial receivers available today. This demonstrates
that CMOS technologies are viable alternatives to more expensive silicon bipolar
and GaAs MESFET technologies commonly employed for integrated receiver applications.
To conclude, we now briey summarize the key contributions presented in the
previous chapters.
9.1 Summary
The vast majority of integrated GPS receivers use a standard superheterodyne architecture with a number of o-chip components, particularly passive IF lters. In
Chapter 4, it was demonstrated how the detailed nature of the GPS signal spectrum
presents an opportunity for a low-IF receiver architecture that oers the benet of
173
174
Chapter 9: Conclusions
complete integration of the receiver signal path. Because the I/Q matching requirements are relaxed in this architecture, adequate image rejection is readily obtained
without trimming or calibration.
With the goal of minimum power consumption in mind, subsequent chapters set
out in detail how to optimize the design of the signal path elements. Beginning
with the low-noise amplier, Chapter 5 demonstrates the theoretical limits to lownoise operation in CMOS by including an oft-neglected noise source: induced gate
noise. By optimizing the device geometry under the constraint of a good input
match and constant power consumption, the conditions for minimum noise gure
were derived. This \power-constrained" optimization demonstrates that excellent
noise performance can be achieved in CMOS with small numbers of milliwatts while
delivering a good input impedance match to the o-chip 50
world. This theoretical
development enables a 2.4dB noise gure for a dierential LNA with only 4.9mA of
bias current.
The design of the second signal path element, the mixer, is the subject of the
next chapter. The double-balanced CMOS voltage mixer consumes exceptionally
little power with no bias current required in the mixer core. Although conversion
gain is a concern in this architecture, a careful analysis demonstrates that higher
conversion gains can be obtained by reactively terminating the IF port of the mixer.
A noise gure analysis further demonstrated that SSB noise gures on the order of
6dB are easy to obtain. Finally, the linearity of the mixer is primarily limited by the
magnitude of the LO drive. Thus, the CMOS voltage mixer achieves wide dynamic
range and excellent noise gure with no static power consumption.
The next critical signal path block is the on-chip active lter. Because active
lters are automatically at a disadvantage compared to o-chip passive lters, it
is important to understand how to optimize their performance for a given power
budget. By considering the dynamic range limitations of the Gm-C architecture
in Chapter 7, we derived a gure of merit for transconductors that is useful as
a design aid. With attention to the gure of merit, a survey of several types of
transconductors demonstrated the merits of a new architecture that is linearized
by positive feedback. Applying this approach to a 5th-order lowpass elliptical lter
9.2: Recommendations for Future Work
175
results in an active lter with over 60dB peak SFDR and 3.5MHz bandwidth with
only 10mW of power consumption.
Combining the LNA, mixer and lter concepts, a complete GPS receiver was
described in Chapter 8 that includes all of the signal path elements from LNA to
bits. The receiver has a pre-limiter noise gure of only 2.8dB, resulting in an output
post-correlation SNR for a noncoherent digital back end of 17dB when processing
an input signal of -130dBm available source power. The total power consumption is
115mW from a single 2.5V supply.
9.2 Recommendations for Future Work
There are a number of issues that await exploration in future research studies. In
particular, the area of CMOS modeling for RF applications is ripe for research.
The behavior of the drain and gate noise coecients ( and ) with respect to
bias voltage and the details of MOSFET device structure is poorly understood at
present. Unfortunately, the lack of a good noise model presents a substantial barrier
to the implementation of CMOS receivers. A thorough experimental and theoretical
investigation of noise modeling for CMOS devices would greatly reduce this barrier.
Another area that needs further investigation is the subject of substrate noise
coupling in integrated radio receivers. So far, there are virtually no published reports of substantial co-integration of DSP and radio front-end components. This
lack is likely due to the extreme complexities involved in modeling noise coupling
mechanisms in mixed signal systems. Design techniques that can mitigate or reduce interference between digital and radio blocks are needed. A study of substrate
coupling in a radio context will be necessary to enable the achievement of a true
\single-chip radio".
In the future, process scaling may necessitate a reduction in supply voltage for
integrated radio receivers. This trend will present a number of challenges for wide
dynamic range receiver design. Thus, an investigation into low-voltage radio techniques would also be an interesting and timely topic.
176
Chapter 9: Conclusions
Appendix A
Cross-correlation Properties of
Limited Gaussian Noise Channels
L
IMITERS are widely used in wireless receiver systems in cases where amplitude
information is not essential. In the context of the GPS channel, the noise
power dominates before correlation, and it is important to understand the eect of
limiting on the noise statistics, particularly the eect on autocorrelation and crosscorrelation. Because the former of these can be treated as a special case of the
latter, this appendix analyzes the eect of limiting on the cross-correlation of two
Gaussian noise processes. With this analysis as a tool, the specic case of the Weaver
architecture with signal-path limiters is then considered.
A.1 Limited Gaussian Noise
Let n1 , n2 and n3 be independent Gaussian random variables with variance 2 = 1.
Furthermore, dene
p
p
x = cn1 + 1 , cn2
p
p
y = cn1 + 1 , cn3
177
(A.1)
(A.2)
178 Appendix A: Cross-correlation Properties of Limited Gaussian Noise Channels
so that
E x2 = E y2 = 1
E [xy] = c
(A.3)
(A.4)
Hence, c is the cross-correlation coecient of the two noise processes x and y. We
can dene two new processes that result from hard-limiting of x and y
x~ = sgn[x]
y~ = sgn[y]
(A.5)
(A.6)
The goal of this appendix is, then, to determine E [~xy~].
Making use of the expressions for x and y, we can write
E [~xy~] = E sgn
pcn + p1 , cn sgn ,pcn + p1 , cn 1
2
1
3
,
(A.7)
Using nested expectations, we can temporarily x n1 and expand the expression as
follows,
E [~xy~] = E E sgn
pcn + p1 , cn jn E sgn ,pcn + p1 , cn jn 1
2
1
1
3
1
,
(A.8)
With n1 temporarily xed as a constant in the two inner expectations, we can
evaluate these expectations directly using the probability density function (PDF)
p
for a Gaussian with mean cn1 and variance 1 , c. Thus,
Z 1
p
p
sgn(u) e,(u,pcn1)2 =2(1,c) du
p
E sgn cn1 + 1 , cn2 jn1 =
,1 2 (1 , c)
,
(A.9)
We can simplify this expression through a change of variables. Let
p
u , cn1
v=p
2(1 , c)
(A.10)
A.1: Limited Gaussian Noise
179
Then, equation (A.9) becomes
Z 1
i
hp
p
p
p
1
E sgn cn1 + 1 , cn2 jn1 = p
sgn 2(1 , c)v + cn1 e,v2 dv
,
,1
(A.11)
The sgn function is a two-valued function that is +1 when its argument is positive,
and ,1 when its argument is negative. The argument of the sgn function in (A.11)
is zero when
r
v = v0 = ,n1 2(1 c, c)
(A.12)
With this denition of v0, we can decompose (A.11) into two separate integrals.
Thus,
Z 1
Z v0
p
p
1
1
2
,
v
E sgn cn1 + 1 , cn2 jn1 = p
e dv , p
e,v2 dv
,
,1
v0
(A.13)
Now, because
Z 1
2
,v2 dv
erfc (x) = 1 , erf (x) = p
e
x
(A.14)
we can re-express (A.14) as
p
p
erfc (v0 )
erfc (v0 )
E sgn cn1 + 1 , cn2 jn1 = 2 , 1 , 2
= ,erf (v0) (A.15)
,
We can use this result in (A.8) to write
E [~xy~] = E erf 2(v0)
(A.16)
which expands to
Z 1
r
1
c
2
,u2 =2 du
p
E [~xy~] =
erf ,u
e
2(1 , c)
,1 2
(A.17)
180 Appendix A: Cross-correlation Properties of Limited Gaussian Noise Channels
With a change of variables, we can simplify this expression somewhat. If we let
p
u = , 2v, then
r
Z 1
c e,v2 dv
1
p
E [~xy~] = erf 2 v
1,c
,1
(A.18)
In general, we have Rxy = c. Therefore, the nal expression for the crosscorrelation of two limited gaussian noise processes is
" s
#
Z 1
1
Rxy e,v2 dv
erf 2 v
Rx~y~ = E [~xy~] = p
1 , Rxy
,1
(A.19)
Equation (A.19) expresses how two Gaussian processes with a particular crosscorrelation, Rxy , will produce limited Gaussian processes with cross-correlation, Rx~y~.
The same expression holds for the autocorrelation of a single Gaussian process that
is applied to a limiter. Figure A.1 shows a plot of equation (A.19). Clearly, limiters
have a de-correlating eect on their input noise processes.
A.2 Cross-Correlation in the Weaver Receiver
Having determined the eect of limiters on the autocorrelation and cross-correlation
properties of gaussian noise, we turn our attention to the specic case of the Weaver
architecture, illustrated in Figure A.2. This architecture is exactly that presented
in the historical review of Chapter 2, with the exception that limiters have been
introduced in the two signal paths.
Let n(t) be a Gaussian noise process with autocorrelation Rnn (t). We can
evaluate the cross-correlation at point A in Figure A.2 as follows
RIQ (t; s) = E [n(t)cos (!t)n(s)sin (!s)]
(A.20)
A.2: Cross-Correlation in the Weaver Receiver
181
1.0
Output Correlation
0.8
0.7
0.5
0.3
0.2
0.0
0.0
0.2
0.3
0.5
0.7
Input Correlation
0.8
1.0
Figure A.1: The eect of a limiter on the cross-correlation or autocorrelation of a
Gaussian noise process.
A
I
B
I
+
n(t)
Q
Q
Figure A.2: Simplied block diagram of the CMOS GPS receiver, including a coherent back-end demodulation to baseband.
182 Appendix A: Cross-correlation Properties of Limited Gaussian Noise Channels
which simplies to
RIQ (t; s) = Rnn2(t) [sin (!s + !t) + sin (!t)]
(A.21)
So that if Rnn (t) = n2 (t) then
RIQ (t) = 2n sin (2!t)
2
(A.22)
where t = s , t. Hence, if n(t) is a white noise process, the cross-correlation
between the two channels alternates sign at twice the LO frequency.
Similarly, we can calculate the cross-correlation at point B, after the low-pass
lter. If the two lters are matched and each has an impulse response h(t), then
RIQ (t; s) =
E f[(n(t)cos (!t)) h(t)] [(n(s)sin (!s)) h(s)]g
(A.23)
which can be expanded to
Z 1Z 1
1 1
cos (!x)sin (!y)h(t , x)h(s , y )Rnn (x , y)dxdy
(A.24)
Now, if we assume that Rnn (t) = n2 (t) and if we restrict ourselves to the case
where s = t, then after some simplications
RIQ (t) = 12 sin (2!t) h2(t)
(A.25)
From this expression, if h(t) is a low-pass lter, and if ! is the local oscillator
frequency and is much greater than the cuto frequency of the lter, then RIQ (t) = 0.
Thus, the two channels are de-correlated by the action of the low-pass lters.
Note that complete decorrelation does not occur in general, but rather depends
on the assumption of a white input noise process. More generally, it is sucient for
the image and desired sidebands to have equal noise powers and to be white only
within the bandwidth of the lter, h(t). These constraints are satised in a low-IF
A.2: Cross-Correlation in the Weaver Receiver
183
architecture, due to the narrow lter bandwidth and the proximity of the desired
and image frequencies.
Because the two channels are uncorrelated before quantization, they remain so
after quantization so that no distortion of the cross-correlation occurs. Subsequent
summation of the I and Q channels therefore leads to a 3-dB SNR improvement,
which is precisely the result expected if the image noise were cancelled.
184 Appendix A: Cross-correlation Properties of Limited Gaussian Noise Channels
Appendix B
Classical MOSFET Noise Analysis
T
HIS appendix presents the classical approach to formulating the minimum
noise gure of a MOSFET device. The presentation here draws heavily on
the work in [43], to which the reader is referred for a complete treatment of the
classical theory.
Many texts on CMOS amplier design indicate that the MOSFET device has
a single dominant noise source: channel thermal noise. This source is commonly
modeled as shown in Figure B.1(a) and has a power spectral density of
i2d = 4kTBgd0 :
(B.1)
The MOSFET also has an additional source of noise arising from capacitive coupling
to the noisy channel that causes a noise current to ow in the gate. This induced
gate current noise is easily modeled as a shunt current source in the gate circuit of
the device, as shown in Figure B.1(a), and has a power spectral density of
i2g = 4kTBgg
!2C 2
gg = 50g gs :
d0
(B.2)
(B.3)
Note that this source of noise is not a white noise source. It has an increasing power
spectral density proportional to !02 and is perhaps better described as "blue", to
185
186
Appendix B: Classical MOSFET Noise Analysis
2
veq
i2d
i2eq
i2g
i2g
(b)
(a)
Figure B.1: Equivalent noise models for a MOSFET device with drain and gate
current noise. (a) Physical model. (b) Equivalent model with input-referred sources.
retain the optical analogy. In addition, the induced gate noise is partially correlated
with the drain noise. To account for this correlation, the gate current noise is divided
into two terms: i0g (which is fully correlated with the drain current noise), and i00g
(which is uncorrelated with the drain current noise). The degree of correlation is
then conveniently expressed with a correlation coecient, c, dened as
c = ig id 1 :
i2g i2d 2
(B.4)
Using c, we express ig as
,
,
i2g = i0g + i00g 2 = 4kTBgg jcj2 + 4kTBgg 1 , jcj2 :
(B.5)
The noise gure can be evaluated using equations from [43] if the drain current
noise is referred to the input, as shown in Figure B.1(b). A simple analysis shows
that
2
d0
veq2 = gi2d = 4kTBg
2
g
m
m
(B.6)
Appendix B: Classical MOSFET Noise Analysis
187
and
i2 !2C 2 4kTBgd0 !02Cgs2
i2eq = d g02 gs =
= veq2 (!0Cgs )2
2
g
m
m
(B.7)
where gd0 is the zero-bias drain conductance of the MOSFET device. Because veq2
and i2eq are derived from network transformations on the same noise source, they are
fully correlated.
We can now evaluate the minimum noise gure of the MOSFET device, including
the eects of induced gate noise. The most dicult part, mathematically, is the
evaluation of the correlation admittance, Yc, which relates the correlated portions of
the total equivalent input noise current and voltage:
ieq + i0g
i0g
Yc = v = sCgs + gm i :
eq
d
(B.8)
Multiplying the second term's numerator and denominator by id and averaging,
i0g id
Yc = sCgs + gm 2 = sCgs + gm ig2id :
id
id
(B.9)
The second step in Equation (B.9) is true because i00g is uncorrelated with id , and
hence does not contribute to the cross-correlation term. We can re-express (B.9) as
follows
i2
Yc = sCgs + gm ig id 1 g2
i2g i2d 2 id
!1
2
:
(B.10)
We now can recognize the denition of c from Equation (B.4). Substituting expressions for i2g and i2d from Equations (B.3) and (B.1), respectively, we nd that
s
!02Cgs2
Yc = sCgs + gmc 5g
2
d0
(B.11)
188
Appendix B: Classical MOSFET Noise Analysis
An analysis by van der Ziel [1] has shown that the correlation coecient, c, is
imaginary, and has a value of j 0:395. Using this fact, (B.11) can be simplied.
s
"
Yc = Gc + jBc = j!0Cgs
1 + jcj 5
#
(B.12)
where
= ggm :
(B.13)
d0
Note that Yc 6= sCgs . This inequality means that the source impedance required
for maximum power transfer (a conjugate impedance match where Bs = ,sCgs ) is
dierent than that which is required for minimum noise gure (Bs = ,Bc). Thus,
one cannot have a perfect input match and minimum noise gure simultaneously.
We can dene a term called the equivalent noise resistance that describes the
equivalent noise voltage power in terms of a resistor. It is dened to be
veq2
= gg2d0 :
Rn = 4kTB
m
(B.14)
Similarly, we dene the equivalent uncorrelated noise conductance to describe the
equivalent noise power of the uncorrelated portion of the gate current noise. Hence,
ig 002 = !02Cgs2 (1 , jcj2) :
Gu = 4kTB
5g
d0
(B.15)
With these denitions, we can directly apply the theory outlined in [43] to determine the minimum noise gure. The optimum source admittance is
Yopt = Gopt + jBopt
(B.16)
Appendix B: Classical MOSFET Noise Analysis
189
where
r
u
Gopt = G2c + G
Rn
Bopt = ,Bc:
(B.17)
(B.18)
In this case, substitution of Rn, Gc, Gu and Bc results in
s
Yopt = Gopt + jBopt = !0 Cgs
s
"
#
2 (1 , jcj2) , j! C 1 + jcj : (B.19)
0 gs
5
5
With this optimum source admittance, the corresponding minimum noise gure is
Fmin
r
= 1 + 2Rn (Gopt + Gc) = 1 + 45 !!0
T
1 + 0:773 !!0
T
p
(1 , jcj2)
(B.20)
(B.21)
where the coecient 0:773 is only valid in the long-channel limit.
A few observations are in order. Note that, when induced gate noise is included,
Fmin is well-dened, and Fmin > 1 (0dB). Secondly, the optimum source admittance
is a parallel R-L circuit. As a result, we can dene an optimum Q which corresponds
to the optimum source admittance. Hence,
Qopt =
Bopt G opt
q
=
+ jcj
2:162:
1 , jcj2
5
2
p
(B.22)
Note that this optimum Q is very similar to QL;opt;Gm . Because (B.22) only depends
on the ratio of and , it is reasonable to expect that short channel phenomena will
have only a second-order eect on Qopt.
190
Appendix B: Classical MOSFET Noise Analysis
Appendix C
Experimental CMOS Low-Noise
Ampliers
T
HIS appendix presents the results of two experiments with low-noise ampliers in CMOS. The rst experiment is with a single-ended design in a 0.6m
process, and the second is with a dierential design in a 0.35m process.
C.1 An Experimental Single-Ended LNA
To probe further the ability of CMOS to deliver low noise amplication at 1.57542GHz,
we have implemented a LNA in a 0.6m CMOS technology provided through the
MOSIS service (0.35m Le ). The only information about the technology available
at the time of design referred to interlayer dielectric thicknesses, sheet resistances,
and diusion capacitances. Thankfully, the value of tox was also available, making
possible a crude extrapolation from 0.8m models to provide some basis for simulation. The success of the implementation demonstrates that knowledge of device
capacitances is the most important factor in the design of tuned ampliers.
191
192
Appendix C: Experimental CMOS Low-Noise Ampliers
C.1.1 Implementation
The width of the input device was initially chosen without regard to the induced gate
noise term because the detailed nature of gate noise was unknown to the authors
at design time. It will prove useful to know the optimum width for this technology
so that we can determine whether our performance is limited by the induced gate
noise or by the drain current noise. From Figure 5.8, the optimum QL for a power
dissipation of 7.5mW (which corresponds to the measured PD of the rst stage of
our LNA) is about 4.5, with a corresponding Fmin;PD of 2.1dB. We can immediately
determine the optimum width to be
,1
2
WM1;opt ;PD = 3 !0LCox RsQL;opt;PD 496m
(C.1)
where !0 = 10Grps, L = 0:35m, Cox = 3:84mF=m2, and Rs = 50
. The actual
width of M1 , as implemented, is about 403m, which corresponds to a QL of 5.5,
still very close to the minimum noise gure point for 7.5mW of power dissipation.
Because our QL is greater than the optimum, we expect that our measured performance will be limited by the gate noise. Note, however, that the predicted F neglects
any contribution to the noise gure by parasitic losses, particularly those due to onchip spiral inductors, which inuence the noise gure of the LNA. Accordingly, the
amplier will possess a noise gure which is greater than 2.1dB.
The complete schematic of the LNA is shown in Figure C.1. The amplier is a
two-stage, cascoded architecture. The drain of M2 is tuned by a 7nH on-chip spiral
inductor, Ld. This inductor resonates with the total capacitance at the drain of M2,
including Cgs of M3. Transistor M3 serves as an open-drain output driver providing
4.6dB of gain, and the amplier uses the test instrument itself as the load. Note
that M3 has a gate width of about 200m, or half of M1.
Four of the inductors shown (Ls, Lgnd, Lvdd and Lout) are formed by bondwire
inductances. Of these four, Ls is the only one whose specic value is signicant in the
operation of the amplier, since it sets the input impedance of the LNA. Lgnd and
Lout are unwanted parasitics, so their values are minimized by proper die bonding.
C.1: An Experimental Single-Ended LNA
193
Vdd
Lvdd
Input Bias Tee
Vbias
Lb1
Rs
Vs
Cb1
M4
O-Chip Matching
Tm
Lg
Cm
Vdd Output
Bias Tee
Lb2
Cb2
Ld
Lout
M2
M3
To Spectrum
Analyzer
M1
Ls
Lgnd
Figure C.1: Complete schematic of the LNA, including o-chip elements.
Lvdd aids in supply ltering with M4, which acts as a supply bypass capacitor.
Because a large value of inductance is benecial for this use, Lvdd is formed from a
relatively long bondwire.
Due to the lack of simulation models before fabrication, a exible topology was
chosen which would permit post-fabrication adjustment of the bias points of M1
and M2. The input matching is accomplished with the aid of an o-chip network.
O-chip tuning was required because the necessary value of Lg was prohibitively
large for on-chip fabrication. However, a 4nH inductor was integrated on-chip in
series with the gate of M1. This inductor, together with the input bondwire inductance, reduces the matching burden of the o-chip network. Unfortunately, it
also introduces additional resistive losses which degrade the noise performance of
the LNA.
A die photo of the LNA is shown in Figure C.2. The two spiral inductors are
clearly visible. The input pad is on the lower left corner of the die. The spiral on
the left is a 4nH inductor which forms a portion of Lg. The spiral on the right is a
194
Appendix C: Experimental CMOS Low-Noise Ampliers
Figure C.2: Die photo of the LNA.
7nH inductor that tunes the output of the rst stage. The spirals are fabricated in
metal-3, which permits Q's of about 3 to be achieved. This value of Q is typical of
on-chip spiral inductors that have been reported in the literature [51]. To improve
the Q slightly, the inductors are tapered so that the outer spirals use wider metal
lines than the inner spirals. The goal of this tapering is to distribute the loss to
yield a roughly constant loss per turn. A magnetic eld solver, FastHenry, was used
during the design of the LNA to predict the values of inductance and the winding
loss associated with various geometries. From these simulations, we determined that
tapering provides a slight, but welcome, increase in Q (approximately 20%).
C.1.2 Experimental Results
To test the LNA, the die was mounted in a high-frequency package and bonded. The
measured gain (S21) of the amplier appears in Figure C.3. The gain has a peak
value of 22dB at 1.46GHz and remains above 20dB to almost 1.6GHz. The bandpass
nature of the amplier is evident from the plot. The input reection coecient (S11)
is also plotted in Figure C.4. The input VSWR at 1.5GHz is quite good (about
1.4) with the addition of o-chip tuning elements.
C.1: An Experimental Single-Ended LNA
Figure C.3: Measured S21 of the LNA
Figure C.4: Measured S11 of the LNA
195
196
Appendix C: Experimental CMOS Low-Noise Ampliers
Figure C.5: Measured S12 of the LNA
It is interesting that both plots exhibit some anomalies at about 1.4GHz. On
the S21 curve, the gain begins to dip sharply, whereas the S11 plot shows a bump
in the reection coecient. This point is indicated by marker 2 on both plots.
An examination of the reverse gain of the amplier (S12) in Figure C.5 provides
a plausible explanation for these anomalies. Marker 2 is positioned at the same
frequency as in the two previous plots. Note that it coincides with a pronounced
peak in the reverse gain. Indeed, the approximate loop gain magnitude of the LNA
at marker 2 is -6dB. This value is insucient to cause oscillation of the amplier, but
is nonetheless substantial. Accordingly, we are compelled to attribute the formerly
mentioned anomalies to this reverse isolation problem.
Another feature of the S12 characteristic is a sharp null at 1.5GHz. This null is
a clue to the source of our troubles. In Figure C.6, a partial schematic of the LNA
is shown along with various signicant parasitic capacitances. The substrate of the
die was connected to the lowest inductance signal ground, Lgnd. As shown in the
diagram, this choice degrades the reverse isolation by allowing signal currents in the
output driver to couple back to the input through the large parasitic capacitance of
C.1: An Experimental Single-Ended LNA
Ld
Lg
Cg1
Cg2
197
1
Cgd3
Lout
2
M3
M2
M1
Ls
Cd
Cpad
Lgnd
Figure C.6: Detailed LNA schematic showing parasitic reverse paths.
198
Appendix C: Experimental CMOS Low-Noise Ampliers
Noise Figure / S21
10.0
30.0
S21
9.0
25.0
8.0
20.0
15.0
6.0
5.0
10.0
4.0
NF
5.0
3.0
2.0
1.0
S21 (dB)
NF (dB)
7.0
1.2
1.4
1.6
Supply Voltage (V)
1.8
0.0
2.0
Figure C.7: Noise gure and forward gain of the LNA.
the gate inductance and its bond pad. There are actually two signicant paths for
this to occur, opening the possibility of cancellation at a particular frequency. Indeed, a signicant phase shift along path 1 in the diagram occurs near the resonance
of Ld and Cd. A null in the reverse gain could thus occur near this frequency. This
problem could be mitigated by terminating the substrate dierently, or by moving
to a dierential structure.
The noise gure and gain of the LNA are plotted in Figure C.7. From this plot,
we can see that at Vdd=1.5V, the LNA exhibits a 3.5dB noise gure with 22dB of
forward gain. The power dissipation is 30mW total. Of this power, only 7.5mW is
consumed by the rst amplier stage. The other 22.5mW is used to drive 50
with
the open-drain output driver. This added power could be nearly eliminated if the
LNA were to drive an on-chip mixer rather than an o-chip transmission line.
Although the measured noise gure exceeds the theoretical minimum of 2.1dB,
it is a simple matter to account for the dierence. In particular, our theoretical
predictions must be modied to include the loss of the 4nH spiral inductor, which
contributes signicantly to the noise gure, and to account for the actual impedance
C.2: An Experimental Dierential LNA
199
Third-Order Intercept (IP3)
Two-Tone Test, f0=1.5GHz, f1=1.49GHz
30.0
20.0
10.0
Output Power (dBm)
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-40.0
-30.0
-20.0
Source Power (dBm)
-10.0
0.0
Figure C.8: Results of two-tone IP3 measurement.
level at the LNA input, as determined by !T Ls . In the nal amplier, !T Ls was less
than 50
. In fact, the real portion of the input impedance, before matching, was
about 35
. If we assume that the 4nH inductor possesses a Q of about three, then it
would contribute about 0.38 to F in a 35
environment. In addition, the theoretical
minimum increases to about 2.5dB when Rs is 35
. These two eects therefore
elevate the predicted noise gure from 2.1dB to 3.3dB. The remaining 0.2dB may
be attributed to the second stage of the amplier.
A two-tone IP3 measurement was performed on the LNA and the results are
shown in Figure C.8. The two tones were applied with equal power levels at 1.49GHz
and 1.5GHz. The measurement indicates a -9.3dBm input-referred third-order intercept point (+12.7dBm output-referred). The linearity is primarily limited by M3,
due to the gain which precedes it.
The measured performance of the LNA is summarized in Table C.1.
200
Appendix C: Experimental CMOS Low-Noise Ampliers
Table C.1: Single-ended LNA Performance Summary
Frequency
Noise Figure
S21
IP3 (Output)
1dB Compression (Output)
1.5GHz
3.5dB
22dB
12.7dBm
0dBm
Supply Voltage
Power Dissipation
(First Stage)
1.5V
30mW
7.5mW
Technology
Die Area
0.6m CMOS
0.12mm2
C.2 An Experimental Dierential LNA
As an alternative to a single-ended LNA, one might select a dierential architecture.
As demonstrated in the single-ended LNA experiment, the inuence of substrate
parasitics can be pernicious. Dierential architectures will be somewhat immune to
such common-mode impedances due to the dierential symmetry. In addition, in the
context of a complete integrated receiver system, rejection of common-mode noise is
important. Because the LNA is the most sensitive signal block in the receive path,
it is important to minimize coupling between other blocks and the LNA input, for
stability reasons as well as supply and substrate noise reasons.
The penalty for selecting a dierential architecture, however, is that twice the
power must be consumed to achieve the same noise performance. Furthermore, an
o-chip balun will be required for interfacing to a single-ended RF lter and antenna,
and this balun will introduce loss, thereby degrading the noise gure of the system.
For modern ceramic hybrid baluns in this frequency range, a loss of about 0.5dB
can be expected. In some applications, the balun can be eliminated through the use
of a balanced antenna and RF lter.
C.2: An Experimental Dierential LNA
R6 R7
Op
M7
M5
L3
M11
Inp
M3
M9
R8 R9
Om
M8
R5
R4
M1 L1
M20
M6
M14
M17
L4
R3
R1
201
R2
M15
M16
M4
M10
L2 M2
M12
M13
Inm
M19
M18
Figure C.9: Dierential LNA circuit diagram
C.2.1 Implementation
Figure C.9 shows a circuit level description of the dierential LNA. It consists of
two stages: the input stage, formed by transistors M1 through M4, and the output
stage, formed by transistors M7 and M8. The input stage is cascoded for a number
of reasons. The rst is to reduce the inuence of the gate to drain overlap capacitance, Cgd , on the LNA's input impedance. Specically, the Miller eect tends to
lower the input impedance substantially, complicating the task of matching to the
input. In addition to mitigating the Miller eect, the use of a cascode improves
the LNA's reverse isolation, which is important in the present application for suppressing local oscillator (LO) feedthrough from the mixer back to the LNA's radio
frequency (RF) input. Furthermore, because the output of the rst stage is tuned
with spiral inductors, L3 and L4, the LNA's stability might be compromised without
the cascode, due to interaction between the inductive load and the input matching
network through Cgd . It should be noted, however, that a noise penalty is incurred
202
Appendix C: Experimental CMOS Low-Noise Ampliers
VDD
R5
R3
M7
M3
M1
R4
Figure C.10: Single-ended version of the DC biasing technique
when using a cascode. But, with proper attention to the layout of the devices, the
additional noise can be minimized. For input matching purposes, the LNA uses
inductive source degeneration via two on-chip spirals, L1 and L2.
The bias current of the input stage is reused in the output stage, decreasing the
power by a factor of two. The low threshold voltage of this process permits four
devices to be stacked, provided that adequate bias control is included. The goal is
to use the minimum Vds to keep devices M1 and M2 in saturation, while leaving
some room for signal swing. This will also, hopefully, benet the noise performance
by limiting the peak electric eld in the input devices.
Figure C.10 illustrates the active common-mode feedback technique that permits
the amplier to operate reliably on a 1.5V supply, independent of process, supply,
and temperature variations. Resistors R3 and R4 sense a fraction of the input
devices' common-mode Vgs level. This fraction becomes the reference to which the
input devices' common-mode Vds level is servoed. An operational amplier, formed
by transistors M12 through M15, is used to close the biasing loop, with adjustments
to the input devices' common-mode Vds level being made via the gate voltage on the
cascode devices. Resistor R5 permits extra headroom at the drains of M3 and M4,
since the signal swing at these nodes can be large.
C.2: An Experimental Dierential LNA
203
Figure C.11: Die photo
The implemented width is only 290m, because the detailed nature of the gate
noise was unknown to the authors when this amplier was designed. However,
the noise gure curve has a broad minimum, so the achievable noise gure is little
aected by using transistors of this width, at least in principle.
C.2.2 Experimental Results
The LNA was integrated in a 0.35m CMOS technology with only two metal layers.
A die photograph is shown in Figure C.11. The aspect ratio of the silicon is somewhat
unusual because this project was designed to t in the scribe lane of a wafer that
was primarily devoted to other dice. Accordingly, the dimensions are 350m x
2.4mm. The results of experimental measurements are summarized in Table C.2
and discussed in detail below.
The test board for the LNA used a low-loss dielectric, and contained auxiliary
test structures, to permit measurement of the insertion loss of board traces, baluns,
and connectors. As a result, the noise gure of the LNA could be measured with a
precision of 0:2dB.
The theoretical noise gure for this amplier is plotted as a function of device
width in Figure C.12. The theoretical noise gure for power-matched devices with a
100-
impedance level is shown by the lower curve, with a predicted noise gure of
1.8dB. The measured noise gure diverges from this number substantially. In part,
this dierence is due to the fact that the complete amplier has more than one noise
contributor; however this is not sucient to account for the discrepancy.
204
Appendix C: Experimental CMOS Low-Noise Ampliers
Table C.2: Dierential LNA Performance Summary
Frequency
Noise Figure
S21
S12
IP3 (Input)
1dB Compression (Input)
1.57542GHz
3.8dB
17.0dB
-52dB
-6dBm
-20dBm
Power Dissipation
12mW
Supply Voltage
Technology
Die Area
1.5V
0.35m CMOS
0.84mm2
A measurement of the input impedance of the LNA revealed the primary reason
for the dierence. The real part of the input impedance was found to be only
40
dierential, rather than the desired 100
dierential. This gross dierence is
partially due to the inuence of the overlap capacitance of the input devices, which
lowers the impedance seen at the gates of those devices. This behavior was observed
in simulations of the LNA's input impedance, but unfortunately, the impact of
the reduced impedance on the noise gure was not fully appreciated at the time.
Furthermore, increasing the inductance of the source spiral inductors, L1 and L2,
which is necessary to combat this eect, would reduce the LNA's gain, leading to
an increase in the mixer's relative noise contribution.
The noise gure curve of the earlier section can be re-plotted in light of this
information. Because we are matching to a lower impedance, one might expect the
noise contribution of the input devices to be more signicant relative to this reduced
impedance. Indeed, this is the case, as is evident in the plot of Figure C.12. Both
noise gure plots represent predictions for the performance of an isolated device of
the stated width, assuming 12mW power consumption in the nal amplier. As
can be seen, the chosen width of 290m is substantially removed from the optimum
C.2: An Experimental Dierential LNA
205
4.0
<[Zin ] = 100
Noise Figure (dB)
3.5
3.2dB
3.0
<[Zin ] = 40
2.5
1.8dB
2.0
1.5
1.0
0
500
1000
1500
2000
2500
3000
Width (m)
Figure C.12: Noise gure vs. device width for Rin = 100
and Rin = 40
point on the 40
curve. Also, the optimum point on this new curve is itself 0.7dB
higher than on the 100
curve. These compounding eects illustrate the penalty in
undershooting the desired input impedance.
The revised prediction anticipates a 3.2dB noise gure from the input pair alone.
Thus, the observed total noise gure of 3.8dB is reasonable, given that other devices
in the circuit contribute noise in a second-order fashion. For example, the cascode
devices, the load inductors, and the output stage transistors all have noise, which
contributes some small amount to the noise gure. The forward gain (S21) and noise
gure are plotted in Figure C.13.
One salient feature of the dierential LNA architecture that should be mentioned
is its reverse gain (S12), which was measured to be less than -52dB between 1GHz
and 2GHz. Good reverse isolation is required to attenuate local oscillator leakage
from the mixer back to the RF input of the LNA. The use of a cascode structure
in the LNA's input stage helps to reduce reverse feedthrough, and this good reverse
isolation is augmented by the fact that the substrate appears as an incremental
ground, to rst order, for dierential signals.
206
Appendix C: Experimental CMOS Low-Noise Ampliers
S21
18.0
16.0
7.0
14.0
5.0
NF
12.0
3.0
10.0
1100.0 1200.0 1300.0 1400.0 1500.0 1600.0 1700.0
Frequency (MHz)
Figure C.13: LNA noise gure/S21 measurement
S21 (dB)
Noise Figure (dB)
9.0
Appendix D
Measurement Techniques
T
HIS appendix describes in detail the experimental setups that are used to
gather the data presented in Chapter 8. The rst section presents the noise
gure measurement technique for the low-noise amplier. The next section presents
techniques for determining the noise gure, linearity and frequency response of the
receiver, as measured at a test point just before the limiting amplier chain. Finally, the last section describes how the entire receiver is tested with a pseudo-noise
modulated carrier to emulate the GPS signal.
D.1 LNA Noise Figure Measurements
To measure the noise gure of the low-noise amplier in the GPS receiver, a separate
LNA test structure is implemented. The only dierence between the test structure
and the LNA in the receiver itself is that the test structure has an open-drain
output driver for driving the 50
test instrument. Because it drives the instrument
directly, the test LNA has less available power gain than the receiver LNA. However,
the available power gain is suciently high (15dB) for noise measurement purposes.
Figure D.1 shows the experimental setup used for LNA noise gure measurements. The four layer test board is implemented on a low-loss dielectric material
called RO-4003, available from Rogers Corp. A thin, 8-mil dielectric reduces the
conductor width necessary for a 50
microstripline to only 15 mills.
207
208
Appendix D: Measurement Techniques
HP 346B
Noise Source
HP 8970B
Noise Figure Meter
Murata
LDB20C101A1600
Murata
LDB20C101A1600
120p
C
1n
1n
120p
Pre-DUT Loss Calibration Structure
LNA Input Matching Network Layout
C
Figure D.1: Experimental setup for LNA noise gure measurements.
D.2: Pre-Limiter Receiver Measurements
209
A key part of this setup is the input matching network and balun. The balun
is a ceramic hybrid balun available from Murata. Its insertion loss is of primary
importance in noise measurements because this loss adds directly to the measured
noise gure. The Murata balun provides about 0.5dB of insertion loss, typically.
To calibrate out the losses preceding the LNA, a special test structure is built on
the same board with two back-to-back connector/balun assemblies. This calibration
assembly is critical for making accurate measurements because pre-DUT insertion
losses can easily exceed 1dB.
The input matching network consists of two transmission lines and a single SMD
capacitor bridging the two lines. As shown in Figure D.1, the position and value of
the matching capacitor can be adjusted to achieve the desired input match. This
technique greatly simplies the task of input matching. The capacitor can be held
with a pair of tweezers and placed at various points along the line while S11 measurements are performed. Thus, renement of the match proceeds easily. Once the
optimum value and position are determined, the capacitor is soldered in place. It is
found experimentally that matching with this technique can be done in 10 minutes,
typically, compared to an hour or more for matching with a lumped component
L-match.
The output of the LNA drives another Murata balun, though a connector to the
HP8970B noise gure meter. For LNAs with open-drain output drivers, a simple
bias tee can be implemented on the board with a pull-up inductor or resistor and
a 1nF coupling capacitor. With this setup, measurement accuracy on the order of
0.2dB can be easily obtained. To achieve this accuracy, it is important that the
output of the LNA be impedance-matched to the input of the noise gure meter.
This requirement is due to the fact that the meter assumes that the insertion gain
of the LNA is identical to its available gain, and this is only true when the output
of the LNA is matched. The insertion gain measurement is used by the meter to
correct for its own contribution to the measured noise gure. Thus, any dierence
between the insertion gain and the available gain leads to an error.
210
Appendix D: Measurement Techniques
HP 346B
Noise Source
HP8593E
Spectrum
Analyzer
HP 8970B
Noise Figure Meter
Murata
LDB20C101A1600
100
1k
120p
1n
1n
DUT
2.2p
3.3p
1812WBT-2
1k
AD9630
25
25
120p
1812WBT-4
HP8664A
Frequency
Synthesizer
143MHz
0dBm
1n
1n
1k
1k
PLL
Ref.
25
25
Figure D.2: Experimental setup for receiver noise gure measurements.
D.2 Pre-Limiter Receiver Measurements
To verify the receiver signal path, several measurements are taken at a test point just
preceding the limiting amplier chain. These measurements include a noise gure
measurement, an IP3 measurement and a signal path frequency response measurement.
Figure D.2 shows the experimental setup for the system noise gure measurement. The primary complication with noise gure measurements of the entire signal
path is that the signal path bandwidth is only 3.5MHz, whereas the input bandwidth of the noise gure meter is 10MHz. In addition, the IF frequency is below
the minimum measurement frequency of the HP8970B meter. So, the measurement
must be performed with a spectrum analyzer instead of the noise gure meter.
The LNA input matching circuitry is identical to that presented in Figure D.1.
An o-chip frequency reference is supplied with the HP8664A frequency synthesizer.
D.2: Pre-Limiter Receiver Measurements
211
This reference is used by the on-chip PLL for synthesis of the 1.573GHz local oscillator. Note that the reference is brought on-chip as a low-swing dierential clock to
reduce coupling to the substrate.
The test point output is an open drain amplier that is very similar to the
intermediate frequency amplier. The output signal is ac coupled to two AD9630
high-speed low-distortion buers that provide sucient transducer power gain into
50
to make a meaningful noise measurement. The noise of the buers contributes
negligibly to the total noise gure. The buered dierential signal is transformed
into a single-ended signal for driving the spectrum analyzer.
The measurement principle is as follows. The noise source toggles between a hot
and cold state. In the cold state, it produces a noise power of kTB and in the hot
state, it produces a noise power of ENRkTB , where ENR is termed the excess noise
power ratio. At the system output, the noise gure can be determined by comparing
the output noise for the two source temperatures. The output noise power ratio is
related to the ENR by
a + (F , 1)kTBGa
= ENR +F(F , 1) :
OPR = ENRkTBGFkTBG
a
(D.1)
Solving for F yields
ENR , 1 :
F = OPR
,1
(D.2)
The OPR can easily be measured using the spectrum analyzer.
In addition to noise gure measurements, an IP3 measurement can be performed
with a very similar setup, shown in Figure D.3. In this case, the receiver input is
driven by two signal sources at slightly dierent frequencies. The frequencies are
selected so that the two input tones and their IM3 products fall within the receiver
passband. A simple power splitter combines the two signals and 10dB attenuators
are used to prevent direct cross-modulation of the output stages of the frequency
synthesizers. Thus, each signal source sees a 26dB attenuation from the output of
the other signal source. The third order intermodulation products produced by the
212
Appendix D: Measurement Techniques
1.57592GHz
PSPL 5330A
Power Splitter
16.7
10dB
HP8780A
Frequency
Synthesizer
HP8593E
Spectrum
Analyzer
16.7
16.7
10dB
HP8648C
Frequency
Synthesizer
1.57542GHz
Murata
LDB20C101A1600
100
1k
120p
1n
1n
DUT
2.2p
3.3p
1812WBT-2
1k
AD9630
25
25
120p
1812WBT-4
HP8664A
Frequency
Synthesizer
143MHz
0dBm
1n
1n
1k
1k
PLL
Ref.
25
25
Figure D.3: Experimental setup for receiver IP3 measurements.
receiver can be observed directly with the spectrum analyzer. It is important to note
that the specied linearity of the AD9630 buers is such that they do not contribute
signicantly to the observed distortion.
Finally, the same board setup can be used for measurement of the receiver frequency response using the arrangement depicted in Figure D.4. In this test, the
tracking generator of the HP8590B spectrum analyzer stimulates the receiver input. Because the DUT has frequency conversion built into it, the tracking generator
output must rst be upconverted to the desired input frequency band, centered at
1.57542GHz. This is accomplished using a frequency synthesizer and a Minicircuits
ZFM-2 diode ring modulator. A variable attenuator allows for rapid adjustment
of the receiver input power without having to re-align the tracking generator. The
attenuator also attenuates any spurious outputs of the ZFM-2 mixer.
Once the tracking generator is properly aligned to the spectrum analyzer sweep
oscillator, the frequency response of the DUT will be swept out and displayed on the
screen. The dynamic range of frequency response measurements using this technique
is limited to about 80dB by the spectrum analyzer.
D.3: Whole Receiver Verication
213
HP8648C
Frequency
Synthesizer
1.57342GHz
7dBm
L
I
R
Atten.
0dB-70dB
ZFM-2
HP8590B
Spectrum
Analyzer
Tracking
Generator
-11dBm
Murata
LDB20C101A1600
100
1k
120p
1n
1n
DUT
2.2p
3.3p
1812WBT-2
1k
AD9630
25
25
120p
1812WBT-4
HP8664A
Frequency
Synthesizer
143MHz
0dBm
1n
1n
1k
1k
PLL
Ref.
25
25
Figure D.4: Experimental setup for receiver frequency response measurements.
D.3 Whole Receiver Verication
Finally, the entire receiver can be tested by applying a pseudo-noise modulated RF
carrier to the input and acquiring the digital output bit streams from the I and Q
channels. These bit streams can then be correlated by a computer to determine the
SNR of the whole receiver. An experimental setup for doing such a measurement is
shown in Figure D.5.
In this setup, the I and Q output channels are brought o-chip as low-swing
dierential signals to reduce coupling to the substrate. The signals are sensed with
an AD9698 dual comparator and then latched into two J-K ip-ops. The comparators and ip-ops are clocked with the HP8648C frequency synthesizer, which also
supplies the sampling clock to the DUT. This sampling clock is also a low-swing
dierential signal. An AD790 comparator amplies this signal up to a full-swing
logic level for operation of the comparators and ip-ops. The same clock signal
also drives the logic analyzer, thereby ensuring that all parts of the system are on
the same timebase. Note that all of the frequency synthesizers are slaved to the
214
Appendix D: Measurement Techniques
HP8780A
Frequency
Synthesizer
BPSK
Mod.
HP16500B
Logic Analyzer
1.57542GHz
-130dBm
Murata
LDB20C101A1600
390
1k
AD9698
74HC73D
120p
2.2p
J
DUT
J
120p
1n
AD790
157.3374MHz
0dBm
CLK
PLL
Ref.
Q
K Q
1812WBT-4
HP8664A
Frequency
Synthesizer
Q
K Q
1812WBT-2
HP8648C
Frequency
Synthesizer
16.368MHz
0dBm
25
Figure D.5: Experimental setup for complete receiver measurements.
D.3: Whole Receiver Verication
215
10MHz crystal reference of the HP8664A so that they also share the same timebase.
This connection is omitted from the gure for clarity.
To operate this experiment, a pseudo-noise sequence is loaded into the pattern
generator of the HP16500B logic analyzer. The pseudo-noise pattern modulates a
1.57542GHz carrier produced by the HP8780A frequency synthesizer. This modulated carrier stimulates the receiver input, and the resulting output data streams
are acquired by the logic analyzer. The pseudo-noise code is also acquired by the
analyzer to provide a convenient phase-reference for subsequent code correlations
performed by computer.
The PLL reference frequency and the sampling CLK frequency are chosen to
provide a sampling rate that is exactly sixteen times the pseudo-noise code rate
of 1.023MHz and eight times the intermediate frequency of 2.046MHz. Note that a
PLL reference frequency of 157.3374MHz produces an LO frequency of 1.573374GHz
so that the IF frequency is 2.046MHz. This frequency plan causes pseudo-noise
chips to occur at regular sample intervals, thereby simplifying the computational
complexity in correlating the received IF signal with a reference pseudo-noise code.
Even with such simplications, the computation takes about 1 hour on a Sun Ultra 1
workstation.
216
Appendix D: Measurement Techniques
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