UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
Last modified on November 17, 2005 by Lynn Wang (ting0918@eecs.berkeley.edu)
Dejan Markovic
Homework 9
EECS 141
th
Due Tuesday, Nov 29 , 5pm
8
Problem 1 –Pulse-triggered latch
Vdd
X
Q
Q
D
Clk
Clkb
Figure above shows a practical implementation of a pulse- triggered latch. The Clock is ideal
with 50% duty cycle.
Data : tp,inv = 200ps, Cclkb = 10fF, Cx = 10fF, CQ = CQ = 20fF
a)
b)
c)
Draw the waveforms at nodes Clk, Clkb, X and Q for two clock cycles, with D equals
0 in one cycle and 1 in the other.
What is the approximate value of setup and hold times for this circuit?
If the probability that D will change its logic value in one clock cycle is α = 0.3, with
equal probability of being 0 or 1, what is the power consumption of this circuit?
(Count only the power consumption in the given capacitors) Assume fclk = 100 MHz.
Problem 2 – Timing and Clock Skew
Consider the pipelined logic structure below, where signals advance from one latch to the next in
each clock cycle. Assume latches L1 – L3 are all on the same clock and are positive transparent.
The latches have a propagation delay given by tlatch = 0.3 ns when the clock is high.
Combinational logic blocks A and B are static, and have logic delays that depend on their inputs.
Minimum and maximum delays for each logic block are listed below.
Block A: tpmin = 1.7 ns; tpmax = 2.1 ns
Block B: tpmin = 1.2 ns; tpmax = 1.6 ns
Block C: tpmin = 1.0 ns; tpmax = 1.2 ns (this is for all inputs)
L1
A
L2
B
C
L3
a) Determine ton,max, the maximum time that the clock pulse can be high (i.e. longest time the
latches can be open for). Assume there is NO clock skew.
b) Determine the minimum clock period tmin and the worst case latency tpipeline from the input of
L1 to the output of C. Assume NO clock skew.
c) Now assume that the clock is routed from latch 1 (L1) to latch 3 (L3) in ascending order.
Assume that the clock skew between subsequent latches is the same (i.e. the skew from L1 to L2
is the same as the skew from L2 to L3). Find the MINIMUM clock skew needed to safely run
the clock with a 2.5 ns period.
d) What is the minimum clock period tmin and worst case latency tpipeline from the input of L1 to
the output of C if an additional latch is added between logic blocks B and C?
Problem 3 –Schmitt Trigger
Consider the circuit below. The transistors have VT =0.7V, kn =20 µA/V2 and kp =8 µA/V2 .
Ignore all other parasitic effects in the transistors (including velocity saturation and body
effect).
M1
M5
M2
IN
OUT
M3
M6
M4
The input, shown in the next figure, has a 1ns rise time, ringing between 1V and 4V before
settling to the final value within 30ns. The input acts accordingly when going from high to
low, i.e. the fall time is 1ns with ringing between 1.5 V and –1.5V before settling to 0V within
30ns.
4.0V
Vdd= 2.5V
1.25V
1.0V
a.
b.
c.
d.
Briefly explain the operation of this circuit as a Schmitt trigger.
Find Vm+ and Vm- such that the output transitions only once for this input going
low to high, and transitions only once for the input going high to low.
Size the trans istors, M1 through M6 to implement this VM+ and VM-. (You can start
from the assumption WM3 = WM4 = 1um. Also WP = 2.5WN in a standard inverter.)
Simulate your circuit using spice. For the input, use a step input with rise and fall
times of 20ns. Compare the simulated VM+ and VM- versus those found in parts
(a) and (b). Explain any discrepancies. Use the following Level 1 spice model for
the transistors:
.model pmos pmos LEVEL=1 TOX=25 VTO=-0.7 KP=8e-6 LAMBDA=0.19
PHI=0.6
.model nmos nmos LEVEL=1 TOX=25 VTO=0.7 KP=20e-6 LAMBDA=0.06
PHI=0.6