Simulating with extracted parasitic
Let’s assume I designed the cell inv1, for which I created the views schematic, symbol and
layout.
Creating the inv1 cell WITHOUT power pins
First, create the inverter with the vdd! and
gnd! as global nets using symbols from
analogLib, see screenshot on left.
Then Create Cellview from Cellview, to
create a symbol without power pins. Given
that the power and ground nets are global,
connectivity will be created by name.
You can see the symbol below. Actually a
green rectangle is the default shape, it is the
user responsibility to draw a “nice” symbol,
like the inverter symbol below.
On the VLSI_lab site there is a pointer to a
Berkeley tutorial on schematic and symbol
creation.
Creating the inv1 cell WITH power pins
The first steps show how to create the inv1 cell so that it can be used in higher hierarchy:
Create the inverter schematic view. The
vdd and gnd pins are created as global
nets with “Net Expression” toggled on.
For pin vdd set the “Net Expression”
property name vdd and default net vdd!
For pin gnd set the “Net Expression”
property name gnd and default net gnd!
On both pins set Power Sensitivity to
“None”
The form for the vdd pin is brought below,
the form for gnd is similar.
Then Create symbol view from schematic view using CreateCell viewfrom Cellview. In
the symbol view don’t include the vdd and gnd pins ARE INCUDED.
The user may decide on which side of the symbol to place the pins.
Actually this symbol was created by copying the INV2X symbolPT view from library
gsclib090. It is common practice to copy quality symbols from vendor library and modify
them, abd then save with same name as your cell.
Create layout from schematic, you can again follow one of Berkeley tutorials pointed to by
the VLSI_lab site, however they are on older version of Cadence. In this example inv1 is
actually one of the inverters in the standard cell library. Examples were also provided in the
introductory Cadence slides in class.
You may see the gnd! and vdd! pins on layout. In both cases for schematics WITH or
WITHOUT power pins, you must have the power pins defined in layout and have exactly
same names as in schematic. Here you can see the gnd! and vdd! pins. Names are “case
sensitive”, e.g. vdd, VDD and Vdd are 3 different names.
The next section describes the DRC, LVS and QRC runs on inv1.
Layout verification and RC extraction
1. Verify the layout vs. schematic using Assura LVS, this will open a Run, for which you give
a name, e.g. inv1_ver
2. Run Assura DRC in same Run
3. Perform QRC extraction in same run to “extracted view”, a new view av_extracted is
added for cell inv1. Next you see the Setup form and part of Extraction form
You must have gnd! (your ground node as reference)
Creating the inv1_sim schematic and simulating it
In order to simulate extracted inv1, you need an hierarchy above in which inv1 is used. In this
example I created a cell inv1_sim, which uses inv1.
In this schematic it is worth noting several details:
1. The sources (DC supply and pulse input) as well as load are connected to global ground,
designated so by attaching the gnd cell (from analogLib) to it.
2. The other pin of the DC supply is connected to a net called vdd.
3. Because inv1 symbol has no ground and power pins (to have a simpler symbol), its
power and ground are connected by name, using the netSet properties on the inv1
instance.
4. The next drawing shows the case where inverter pins property VDD is assigned value
vdd and the property VSS is assigned value gnd!. This connects nets vdd and gnd of the
inv1_sim to instance I0 of inv1. THIS IS NOT NEEDED if you used global nets vdd! and
gnd! within the inverter AND in top schematic !! It may be needed when using gsclib090
standard cells without power pins, as the power pin names there are VDD and VSS.
To simulate with RC extracted view
1. First simulate the usual way in ADE GXL
2. Then open the Test EditorSetupEnvironment form and add av_extracted at
beginning of first line, this will enable using the inv1 view av_extracted for cell inv1 in
the simulation.
Using the inverter WITH POWER PINS in simulation
The procedure is same as above, but you must use the symbol with power pins. This may be
useful if you are requested to plot the current of a specific cell or calculate its energy per single
operation.
It is worth noting several details in this schematic:
1. There are explicit vdd and gnd symbols, in previous schematic we had only gnd, but vdd
was only a net. It is GOOD PRACTICE to have explicit vdd and gnd symbols in the top
simulation schematic
2. The power pins of the inverter symbol are connected to respective power nets.
3. Although not requested in this exercise, there is an RCWIRE symbol on output before
the capacitive load, it is used when needed to represent long wires in schematic,
possibly using several RCWIRE sections connected one after the other.