2.4 Modeling and Analysis of Three Phase Four Leg Inverter
The main feature of a three phase inverter, with an additional neutral leg, is its ability
to deal with load unbalance in a standalone power supply system [7],[12]. The goal of the
three phase four leg inverter is to maintain the desired sinusoidal output voltage waveform
over all loading conditions and transients. It is ideal for applications like data communication,
industrial automation, military equipment, which require high performance uninterruptible
power supply. As shown in Figure 1.2, the three phase four leg inverter is used in the
shipboard DC DPS to provide secondary AC power distribution. It can be utilized to supply
utility power for combat equipment, radar and other critical electronic load.
In this section, the modeling and control of a PEBB based three phase four leg
inverter is described. Modeling of the four leg inverter has been discussed in the literature [7].
But, effect of power stage coupling and sampling delay on control design has not been
addressed. This section investigates two control strategies and their limitations.
2.4.1 Principle of Operation
Figure 2.17 shows the three phase four leg inverter composed of PEBBs. Four PEBB
cells with integrated gate drives are configured to form the Four Leg Inverter power stage.
The additional PEBB leg is connected to the neutral of the load. A DSP based local controller
Chapter 2
36
VDC
F
I
L
T
E
R
F
I
L
T
E
R
Driver
Driver
Driver
3φ
3 Phase
4 Wire
Sensor
Board
Driver
Vac
DSP Interface Board
VDC
DSP (I,V Loop, PWM Generation)
Hierarchical Control (Host Computer)
Figure 2.17 : PEBB based Three Phase Four Leg Inverter : Four PEBB cells with
integrated gate drives are configured to form the Inverter. The additional
PEBB cell is connected to the neutral of the load.
Chapter 2
37
supplies gate drive commands through a DSP interface board. The feedback control loop is
implemented digitally using the DSP. The PEBB system includes a sensor board which senses
the DC link voltage and output capacitor voltage and provides feedback to the local
controller. The structure of the PEBB based system inverter (Figure 2.17) is similar to that of
boost rectifier (Figure 2.3). Both of them have the same general purpose controller
configuration. The difference lies in the control algorithm implemented in the local controller.
Figure 2.18 shows the discrete switching model of three phase four leg inverter
simulated using SABER. The PEBB cells are modeled as ideal switches with anti-parallel
diodes. The power stage comprises of four leg inverter with an output LC filter to attenuate
the switching ripple in the output voltage. The additional PEBB leg is connected to the load
neutral. As compared to the conventional inverter, the Four Leg Inverter has the additional
freedom of controlling the load neutral potential. This allows it to maintain balanced output
voltage in presence of unbalanced and non-linear load [7].
The output filter capacitor voltages are sensed and fed back to the local controller
(DSP). The voltages are converted from stationary co-ordinates to rotating co-ordinates to
generate Vd,Vq,V0 . These are compared to the reference voltages and the error voltages are
passed through a compensator. The controller is implemented in rotating co-ordinates. The
output of the compensator, i.e. dd , dq , d0 are inverse transformed to stationary coordinates
to yield d α , d β , d γ . Finally, a complex 3 dimensional space vector modulation scheme
yields the duty cycles for the 16 power switches [7].
Chapter 2
38
Nonlinear
Unbalanced Load
Output Filter
PEBB1
Vφ
L
Vdc
F
I
L
T
E
R
a
a
a
a
C
LN
Driver Driver Driver Driver
V cap
3D SVM
abc/dq0
Rotating
Transformation
dαβγ
Inverse Rotating
Transformation
Vdq0
-
ddq0
Sampling
Delay
Voltage
Compensator
Voltage
Reference
+
Digital Processor Controller
Figure 2.18 : Discrete Switching Model of the Four Leg Inverter : It provides time
domain information. The output filter capacitor voltages are sensed and fed
to the compensator. The controller is shown in the dotted box.
Chapter 2
39
2.4.2 Power Stage Modeling
Figure 2.20(a) shows the power stage model of the three phase four leg inverter with a
second order load filter. The average model in stationary co-ordinates is shown in Figure
2.20(b). The power stage parameters are given in Appendix A. The output voltage and input
current in the inverter can be represented as :
V
 an
Vb n

Vc n

0
0
0
0
0
0


=



dan 
d V
 bn  g

dcn 

,
I p = [d an dbn
I a 

d cn ]
I
b
 

I c 

where, Vin (i=a0,b0,c0) are the inverter output voltages (line-neutral), Ii (i=a,b,c) are line
currents. And, din (i=a,b,c) are the line-to-neutral duty cycles
The duty cycles din (i=a,b,c) are controlled in a way so as to produce sinusoidal
voltages at output of the filter irrespective of the load i.e. the load could be light, heavy,
unbalanced or non-linear. The system requirement can be represented as :
cos(ωt )

Van 

 
0 
Vbn  = Vm cos(ωt − 120 )


Vcn 

cos(ωt + 120 ) 

0
Chapter 2
40
POWER STAGE
nonlinear and/or
unbalanced load
OUTPUT FILTER
Vdc
F
I
L
T
E
R
L
Ln
Va
Vb
Vφ
Vc
Vn
C
neutral
(a) Discrete Switching Model
POWER STAGE
dan*Vg
F
I
L
T
E
R
Vdc
ao
L
a
L
dbn*Vg
bo
dcn*Vg
co
Ip
nonlinear and/or
unbalanced load
OUTPUT FILTER
b
L
Z
c
Co
no
Ln
n
(b) Average Large Signal Model
Figure 2.19 : Power Stage Modeling in Stationary Co-ordinates: The process of
averaging replaces the switches with controlled voltage and current
sources.
Chapter 2
41
where, Vin (i=a,b,c) is the output load voltage
and, Vm = rated output voltage
To produce the desired sinusoidal output voltages, the steady state duty cycles are
time-varying and sinusoidal. But, to apply classical control techniques we need a DC
operating point.
Thus, we apply the transformation T, given in Appendix C, to get the power stage
model in rotating co-ordinates. Figure 2.20 gives the power stage model in rotating coordinates and it is redrawn as a signal flow graph in Figure 2.21. The d and q sub-circuits have
coupled voltage and current sources, shown as the shaded region.
The steady state output load voltages and the duty cycles are DC quantities and are
given as :
Vd  Vm 
   
Vq  = 0 

0 

Vo 
 
,
where, Vm = rated output voltage
And, the duty cycles are given by :
V 

(1 − ω 2 LC ) m 

Vg
D 


 d 

D  =  ωLI d

 q 
Vg

D  

0
 o








Chapter 2
42
ω LIq
Id
dd*Vg
Ip
dq*Vg
L
ω CVq
ω LId
L
Iq
Vq
ω CVd
L+3Ln
d0*Vg
Vd
V0
Figure 2.20 Power Stage Average Model in Rotating Coordinates : The d and q subcircuits have coupled voltage and current sources, shown as the shaded
blocks.
Chapter 2
43
1
dd
dq
Vg
Vg
-
1
sL
+
iLd
- icd
+
ωL
ωC
ωL
ωC
-
1
sL
iLq
icq
-
R
1
sC
Vd
1
sC
Vq
1
1
d0
Vg
+
-
1
s( L + 3Ln)
- ic0
iL0
+
R
R
1
sC
V0
Figure 2.21 : Average Model represented as a Signal Flow Graph : The coupling in d
and q sub- circuits is shown as the shaded blocks. The load is represented as
a resistive load (R).
Chapter 2
44
The load of the system is represented as a disturbance and is assumed resistive. The
Output power varies from 100% to 1% rated power. The system is designed for 150 kW rated
output. Thus, the load varies from 1.53 ohm to 153 ohm. The Average Large Signal model,
shown in Figure 2.20 is simulated using SABER and it is perturbed and linearized at an
operating point to get Small Signal model. The small signal model is utilized for control
design.
The open loop control to output transfer function is shown in Figure 2.22 and 2.23.
Neglecting the coupling in the power stage, the open loop transfer function is approximated
as:
Vd
≈
dd
Vg
Vg
=
L
s
s2
1 + s + s 2 LC 1 +
+
R
ω oQ ω o 2
Where, the resonant frequency is given by ωo =
1
LC
and is ~ 872 Hz. The Q of
the circuit depends on R, thus we have large Q when R is large (Light Load).
As shown in Figure 2.22, the control to output transfer function exhibits peaking for
light load situation. The phase plot shows a steep drop by 1800 near the resonant frequency. In
case of heavy load situation, the control-to-output transfer function is well damped and it
shows a phase drop of 900 at the resonant frequency. The controller is designed to satisfy the
system performance for both heavy and light load situation.
Chapter 2
45
Gain (dB)
Phase (degrees)
Frequency (Hz)
Frequency (Hz)
Figure 2.22 : Control-to-Output Transfer Function for Light Load : The Vd/dd transfer
function for light load situation shows peaking around 872 Hz (Resonant
Frequency). It has a steep phase drop of 1800 at resonance.
Chapter 2
46
Gain (dB)
Phase (degrees)
Frequency (Hz)
Frequency (Hz)
Figure 2.23 : Control-to-Output Transfer Function for Heavy Load : The Vd/dd transfer
function for heavy load situation is well damped and does not exhibit peaking
at resonance.. It has a phase drop of 900 at resonance.
Chapter 2
47
Digital implementation of the current controller introduces a sampling delay, as
discussed in [5]. The delay yields 1800 phase lag at half the switching frequency and must be
taken into account. It is given by:
e − sT
1 2 2
s T − 0.5sT + 1
12
=
1 2 2
s T + 0.5sT + 1
12
, where T = Sampling Time
The switching frequency of 20 kHz introduces 1800 phase delay at half the switching
frequency and around 150 phase lag at the resonant frequency .
The power stage is a highly coupled multi-variable multi-loop system. The coupling
between the d and q channels of the power stage is represented as the shaded blocks, as
shown in Figure 2.21. It has coupled voltage sources given by ω L and current sources given
by ω C . In order to independently control the d-q-o channels of the power stage, the power
stage must be de-coupled. The voltage source ω L, is canceled by adding a factor ( ω L/Vg)
in the d and q channel duty cycles, as shown in the Figure 2.24.
The power stage cannot be fully de-coupled due to the presence of the delay term at
the output of the modulator as seen in Figure 2.24. As a result, the power stage with non-ideal
de-coupling is given by Figure 2.25. Decoupling the power stage reduces the peaking in the
control-to-output transfer function and improves the phase drop near resonant frequency.
Chapter 2
48
Decoupling
Circuit
1
ddc
-
e-sT
ωL
ωL
dqc
+
Vg
Vg
Vg
e-sT
-
1
sL
+
ωL
iLd
+
- icd
R
1
sC
Vd
1
sC
Vq
ωC
ωL
Vg
-
1
sL
iLq
ωC
icq
-
-
1
1
d0
e-sT
Vg
+
-
1
s( L + 3Ln )
- ic0
iL0
+
R
R
1
sC
V0
Figure 2.25 : Power Stage Decoupling : The voltage source ω L which couples d and q
sub-circuits is canceled by introducing a term ( ω L/Vg) in the controller. It
is not possible to cancel the current sources ω C by this strategy.
Chapter 2
49
1
ddc
e-sT
dqc
e-sT
Vg
1
sL
+
(ω L)
(ω L)
-
+
Vg
iLd
- icd
+
sT
1− ( 05
. ) sT +
R
1
sC
Vd
1
sC
Vq
ωC
1
( sT) 2
12
sT
. ) sT +
1− ( 05
ωC
icq
-
1
( sT) 2
12
+
-
1
sL
iLq
-
1
1
d0
e-sT
Vg
+
-
1
s( L + 3Ln )
- ic0
iL0
+
R
R
1
sC
V0
Figure 2.26 : Partially Decoupled Power Stage : The voltage source ω L which couples d
and q sub-circuits cannot be totally eliminated due to the presence of delay
term e-sT . It has been reduced by a factor (1-e-sT).
Chapter 2
50
2.4.3 Control Loop Design
The Average Large Signal model with partially decoupled power stage, shown in
Figure 2.25 is used to generate the small signal characteristics for the inverter. Figure 2.26
shows the control structure for capacitor voltage loop control. The output filter capacitor
voltages are sensed and transformed from stationary to rotating co-ordinates. These are fed as
feedback signals to d-q-0 channel voltage compensators.
The voltage loop gain TV is given by:
TV =
Vd
HV
dd
The control to output transfer function Vd/dd is given in Figure 2.22 and Figure 2.23.
As discussed in the previous section, the effect of delay and light load places a severe
constraint in the control loop design.
Three phase four leg inverter is a multi-loop and highly coupled multi-variable system.
As the first step, the d-q-o channel compensators are designed independently i.e with other 2
channels assumed open. After the compensators have been designed for all three channels, the
loop gain in a channel is measured again with other 2 loops closed as shown in Figure 2.28.
This is to verify the stability of the system.
Two control design strategies are presented in this section. The dynamic performance
of the inverter with the two control strategies is presented in the next section.
Chapter 2
51
1
dd
e-sT
Vg
dq
e-sT
Vg
1
sL
+
( ω L)
(ω L)
-
+
iLd
- icd
+
sT
. ) sT +
1− (05
R
Vd
1
sC
ωC
1
( sT) 2
12
sT
1− ( 05
. ) sT +
ωC
icq
-
1
( sT) 2
12
+
-
1
sL
iLq
-
Vq
1
sC
1
1
d0
e-sT
Vg
+
-
1
s( L + 3Ln)
- ic0
iL0
+
R
R
V0
1
sC
TV
dd
-
HV
+
Vdref
Voltage Compensator (d-channel)
dq
Vq
Voltage Compensator (q-channel)
d0
Voltage Compensator (0-channel)
Vqref
V0
V0ref
Figure 2.26 : Capacitor Voltage Loop Control (d-channel): The power stage is shown
inside the dotted box. While designing d loop, other two channels i.e. q and
0 channels are left open.
Chapter 2
52
1
dd
e-sT
Vg
dq
e-sT
Vg
1
sL
+
(ω L)
(ω L)
-
+
iLd
+
- icd
sT
. ) sT +
1− (05
R
ωC
1
( sT) 2
12
sT
. ) sT +
1 −( 05
ωC
icq
-
1
( sT) 2
12
+
-
1
sL
iLq
-
1
e-sT
Vg
+
-
1
s( L + 3 Ln )
- ic0
iL0
+
Vq
1
sC
1
d0
Vd
1
sC
R
R
V0
1
sC
TV
dd
H
-
V
+
Vdref
Voltage Compensator (d-channel)
Vq
dq
Voltage Compensator (q-channel)
d0
Vqref
V0
Voltage Compensator (0-channel)
V0ref
Figure 2.27 : Actual Loop Gain (d-channel) : After designing d-q-0 channel compensators,
the actual d channel loop gain is measured by keeping q and 0 channels closed.
Chapter 2
53
2.4.3 (a) Design Strategy - I (PI Compensator)
As shown in Figure 2.22, the control-to-output transfer function Vd/dd has a large
peaking at the resonant frequency of 872 Hz under light load situation. It has a phase drop of
nearly 1800 at resonance. One possibility is to use a PI compensator and close the voltage
loop much below resonance so that the phase drop and peaking effect at resonance do not
affect system stability. The compensator can be implemented as a PI. This is given by :
HV = K p +
Ki Ki 
s 
=
1
+


s
s 
 Ki K p 

Figure 2.28 shows the asymptotic plot of the loop gain. The control-to-output transfer
function has a complex pole at 872 Hz, shown as the dotted curve. A pole is placed at the
origin to give zero steady state error. The zero given by Ki/Kp is placed beyond the loop gain
crossover. The crossover frequency is chosen low so that there is sufficient gain margin.
Figure 2.29 shows the loop gain TV for the light load situation. It has a small
bandwidth of the order of 10 Hz and has a gain margin of around 15 dB. Figure 2.30 shows
the loop gain for the heavy load situation. It is well damped and has 35 dB gain margin and
has a phase margin of around 900. It shows that the design is not optimized for the heavy load
situation. And, designing the same compensator for 1% - 100% load yields a poor design if
conventional PI compensator strategy is employed.
Chapter 2
54
Gain (dB)
Vd/dd Transfer Function
-1
ωz
fBW
ω0
-2
Gain Margin
-1
ω0 = 872 Hz
add integrator and zero
Ki
HV = K p +
s
f BW = 10 Hz
kp = 1.2e-5, k i = 0.07
φm = 900
Figure 2.28 : Asymptotic plot of Loop Gain (Design I) : An integrator is added to ensure
zero steady state error. The cross over frequency is less than the resonant
frequency.
Chapter 2
55
Gain (dB)
Phase (degrees)
Frequency (Hz)
Frequency (Hz)
Figure 2.30 : Loop Gain under Light Load (Design I) : The loop gain cross over
frequency is 10 Hz and it has 15 dB gain margin. The peaking under light
load situation restricts the cross over frequency.
Chapter 2
56
Gain (dB)
Phase (degrees)
Frequency (Hz)
Frequency (Hz)
Figure 2.31 : Loop Gain under Heavy Load (Design I) : The loop gain cross over
frequency is 10 Hz and it has 35 dB gain margin. It has a phase margin
of around 900.
Chapter 2
57
2.4.3 (b) Design Strategy - II ( 4 zero/5 pole compensator)
As discussed in the previous section, closing the loop gain below the resonance yields
low system bandwidth and this results in a poor transient response. Another possibility is to
close the system loop after resonance. It is investigated in this section.
Figure 2.28 shows the asymptotic plot of the control-to-output transfer function which
has a double pole at resonant frequency of 872 Hz. The effect of 1800 phase lag at resonance
and presence of delay at higher frequencies must be taken into account. A pole is placed at the
origin to give zero steady state error. This yields 900 phase lag and thus we have around 2700
phase at resonance. This phase lag must be compensated by zero’s in the compensator.
If we choose to use a 2 zero/3pole compensator, then the two zeros must be placed
one decade below resonance so that they yield 1800 at resonance. As a result of peaking at
light load, the loop gain around 120 Hz would be very small.
The compensator finally chosen is 4 zero/5 pole given as :
s
s
s
s
)(1 + )(1 + )(1 + )
z1
z2
z3
z4
HV = K
s
s
s
s
s(1 + )(1 +
)(1 + )(1 +
)
p1
p2
p3
p4
(1 +
Where, z1 = 780 Hz , z2 = 800 Hz , z3 = 820 Hz , z4 = 840 Hz
and, K = 3.5 , p1 = 1 kHz , p2 = 2.5 kHz , p3 = 10 kHz , p4 = 10 Hz
Chapter 2
58
Placing four zeros near resonance yields 450 from each zero and thus a total of 1800.
Thus, we can compensate the phase lag due to the double resonant pole of the power stage.
As seen in Figure 2.22, the Q of the power stage shows a peaking between 600 Hz to 1500
Hz. Thus, the four zeros are placed in this region so as not to increase the peaking effect.
Final placement of the zeros is chosen according to the tradeoff between cross over frequency
and phase margin. In order to attenuate switching frequency ripple, 2 poles are placed at half
the switching frequency. The other 2 poles are placed before the cross over frequency such
that the loop gain crosses over with -20 dB/decade slope.
Figure 2.31 shows the asymptotic plot of the system loop gain with 4 zero/5 pole
compensator. The four zeros are represented as z1-4 and two poles are shown as p1,2 . The
loop gain has a pole at origin and two poles at half the switching frequency. Figure 2.32
shows the loop gain for light load situation. The loop gain has a cross over frequency of 2
kHz and phase margin of 300. The phase of the system drops sharply after 2.5 kHz due to the
effect of the digital delay. Hence, as a precautionary measure taking into account parameter
variability the bandwidth is chosen around 2 kHz. It has around 12 dB gain at 120 Hz. The
significance of this will be seen in the later 2.4.5.
Figure 2.33 shows the loop gain for heavy load situation. The loop gain has same
cross over frequency of
2 kHz and phase margin of 550. It has higher phase margin as the
phase lag at resonance is not as steep as in light load situation. The phase of the system drops
sharply after 2.5 kHz due to the effect of the digital delay. It also has around 12 dB gain at
120Hz.
Chapter 2
59
Loop Gain
Gain (dB)
-1
-1
fBW
z1,2,3,4
p1,2
Frequency (Hz)
ω0 = 872 Hz
s
s
s
s
)(1 + )(1 + )(1 + )
z1
z2
z3
z4
HV = K
s
s
s
s
s(1 + )(1 + )(1 + )(1 + )
p1
p2
p3
p4
f BW = 2 kHz
(1 +
φm = 30 0
Figure 2.31 : Asymptotic plot of Loop Gain (Design II) : An integrator is added to ensure
zero steady state error. The cross over frequency is more than the resonant
frequency.
Chapter 2
60
Gain (dB)
Phase (degrees)
Frequency (Hz)
Frequency (Hz)
Figure 2.32 : Loop Gain under Light Load (Design II) : The loop gain cross over
frequency is 2 kHz and it has a phase margin of 300. The phase drops
sharply after cross over due to the effect of digital delay.
Chapter 2
61
Gain (dB)
Phase (degrees)
Frequency (Hz)
Frequency (Hz)
Figure 2.33 : Loop Gain under Heavy Load (Design II) : The loop gain cross over
frequency is 2 kHz and it has 12 dB gain at 120 Hz. It has a phase margin
of around 550.
Chapter 2
62
2.4.4 Simulation Results
The three phase four leg inverter, shown in Figure 2.18 is designed to supply 150 kW
output power. The power stage parameters are given in Appendix A. The control design
strategy II is chosen as the optimum strategy. The system operation is verified for load
variation from 1% to 100% rated load. The switching frequency employed is 20 kHz.
Figure 2.34 shows the simulation results for light load situation. The system has a
settling time of around 3 ms. The output load voltages are balanced sinusoids. Figure 2.35
shows the simulation results for heavy load situation. Again, the system has a settling time of
around 3 ms. This is due to the fact that the loop gain are designed such that the cross over
frequency is the same for both light and heavy load situation. The output load voltages are
sinusoidal and the system has a good transient response for balanced load situation
irrespective of the load value.
Control design II is superior to design I as the cross over frequency in case II is much
higher than case I. Dynamic simulations of inverter employing strategy I show that the settling
time for output load voltages is of the order of 100ms. Figure 2.34 and 2.35 also show the
plot of Vd and Vq. The compensator is designed in rotating co-ordinates and hence it controls
Vd and Vq . The final output voltages is derived from them after applying the transformation T.
The V0 turns out to be 0 in these simulations as the load is taken as the balanced load.
Chapter 2
63
Time (s)
(a) Vd , Vq plot
Time (s)
(b) Output Voltages Va , Vb , Vc
Figure 2.34 : Dynamic Performance under Light Load (Design II) : The transient settles
response settles in around 3ms. The output voltages are balanced sinusoids.
Chapter 2
64
Time (s)
(a) Vd , Vq plot
Time (s)
(b) Output Voltages Va , Vb , Vc
Figure 2.35 : Dynamic Performance under Heavy Load (Design II) : The transient settles
response settles in around 3ms. The output voltages are balanced sinusoids.
Chapter 2
65
2.4.5 Effect of Unbalanced and Non-Linear Load
The three phase four leg inverter is supposed to provide rated load voltage in presence
of unbalanced and non-linear load. Fig. 2.36 (a) shows the system with one phase loading.
The average model in stationary co-ordinates is transformed to rotating co-ordinates using the
transformation T, discussed in Appendix C. The unbalanced load represented by a resistor R
results in a line current given by :
Ia 
Ib  =
 

Ic 

(
)
 Vm cosω t
R




0


0




The line currents can be transformed to positive, negative and zero sequence currents,
explained in Appendix D [18]. These currents can then be transformed from stationary to
rotating co-ordinates as given by :
Id 
1 + cos 2ω t
Iq  = Vm  - sin2ω t 

  

 3R 



I
0
cos
ω
t
 


Figure 2.37 (b) gives the power stage model in rotating co-ordinates with load
represented as current sources.
Chapter 2
66
POWER STAGE
dan*Vg
LOAD
L
ao
ia
a
L
dbn*Vg
Ip
OUTPUT FILTER
b
bo
L
dcn*Vg
co
R
c
Co
Ln
no
ω LIq
Id
L
ω LId
L
Iq
d0*Vg
ILd
Vq
ILq
ω CVd
L+3Ln
n
Vd
ω CVq
dd*Vg
dq*Vg
in
V0
IL0
Figure 2.36 a-b : Unbalanced Load situation in Stationary & Rotating Coordinates
Chapter 2
67
The steady state duty cycles required by the inverter are calculated as ;
Dd 
Dq  =
 

D 0 

(
)
(
)
Vm 1 − ω 2 LC − ωL Vm
sin 2ω t
3R


1
 

1 − cos 2ω t)
ωL Vm
(
 

3
R
Vg 


− ωL Vm
sin ω t


3R


(
(
)
)
The steady state duty cycles required by the system are DC quantities and a sinusoidal
component at twice the output frequency i.e 120 Hz and the 0 channel has a sine term of 60
Hz. The unbalanced load presents a 2nd order harmonic in d and q channels which must be
attenuated by the loop gain at that frequencies. The system requires sufficient bandwidth to
take care of unbalanced loads.
The system performance with the two control strategies is investigated in this section.
Figure 2.37 shows the dynamic performance with control design I. The system is loaded one
phase with the rated load. It is seen that the output voltages are not balanced and have a low
frequency oscillation. This is due to the presence of 120 Hz ripple in Vd and Vq and a 60 Hz
ripple in V0. These have not been attenuated due to insufficient loop gain at these frequencies.
Figure 2.38 shows the dynamic performance with control design II. It can be seen that
output voltages are sinusoidal and the control design meets the system specifications. The 120
Hz ripple in Vd and Vq and the 60 Hz ripple in V0 have been attenuated due to
Chapter 2
68
Time (s)
(a) Vd , Vq ,V0 plot
Time (s)
(b) Output Voltages Va , Vb , Vc
Figure 2.37 : Dynamic Performance under Unbalanced Load (Design I) : The output
voltages are not perfectly sinusoidal. Vd and Vq have large 120 Hz ripple.
Chapter 2
69
Time (s)
(a) Vd , Vq ,V0 plot
Time (s)
(b) Output Voltages Va , Vb , Vc
Figure 2.38 : Dynamic performance under Unbalanced Load (Design II) : The output
voltages are balanced sinusoids. Vd and Vq have small 120 Hz ripple.
Chapter 2
70
sufficient loop gain at these frequencies. The system performance is superior than previous
case. It is the most suitable control design approach.
The three phase four leg inverter is supposed to provide rated load voltage in presence
of non-linear load. Fig. 2.39 (a) shows the system feeding a typical non-linear load, diode
rectifier. Diode rectifier is a very popular topology used as a front-end in many electronic
loads.
Figure 2.39 (b) shows the current drawn by the rectifier when fed by an ideal
sinusoidal voltage supply. It draws a current rich in harmonics. Figure 2.39 (c) shows the
input current spectrum. The current has components at 5 ω ,7 ω , 11 ω and 13 ω . Where,
ω is the fundamental output frequency i.e. 60 Hz.
The system performance with the two control strategies is investigated in this section.
Figure 2.40 shows the dynamic performance with control design I. It is seen that the output
voltages are distorted and have a voltage peak of 450 V. Thus the output voltages are around
15% over voltage and they do not meet the specifications. The Vd and Vq have large ripple.
These have not been attenuated due to insufficient loop gain at these frequencies.
Figure 2.41 shows the dynamic performance with control design II. It can be seen that
output voltages are less distorted and do not have any significant over voltage. The system
performance is not as good as in unbalanced case as the loop gain does not have sufficient
bandwidth at high frequencies to reduce their effect on the outer load voltage. The system
performance is superior than Design I. It is a better control design approach
Chapter 2
71
Power Stage
Output Filter
Nonlinear Load
Vdc
F
I
L
T
E
R
L
Vn
Ln
Va
Vb
Vφ
Vc
C
Controller
(a) Inverter feeding Diode Rectifier (Non-Linear Load)
(b) Input Current Drawn By the Rectifier
(c) Input Current Harmonic Spectrum
Figure 2.39 : Four Leg Inverter Feeding Non-Linear Load : The diode rectifier is taken
as the non-linear load. The input current drawn by the rectifier has frequency
components at 5,7,11 and 13 times fundamental frequency (60 Hz).
Chapter 2
72
Time (s)
(a) Vd , Vq ,V0 plot
Time (s)
(b) Output Voltages Va , Vb , Vc
Figure 2.40 : Dynamic Performance under Non-Linear Load (Design I) : The output
voltages are distorted and have harmonics. It has around 15% over voltage.
Chapter 2
73
Time (s)
(a) Vd , Vq ,V0 plot
Time (s)
(b) Output Voltages Va , Vb , Vc
Figure 2.41 : Dynamic performance under Non-Linear Load (Design II) : The output
voltage distortion is reduced and it does not have any significant over voltage.
Chapter 2
74
2.5 Summary
This chapter presented the modeling and control of a PEBB based Boost Rectifier and
Four Leg Inverter. The main feature of a PEBB based system is standardization and ease of
design. It was shown that a common standardized controller can be used for both applications.
This results in lower procurement cost and reduced spare parts inventory for typical medium
power Navy applications and it justifies the additional material cost of the general purpose
PEBB converter as compared to custom-designed converters.
A three level modeling approach was adopted. Based on the small signal analysis,
closed loop design guidelines for the Boost Rectifier are proposed. A DSP based discrete
switching model of the Boost Rectifier was developed. The closed loop simulation of Boost
Rectifier verified the controller design. Fault tolerance concept was demonstrated by ensuring
stable system operation of the rectifier with one leg of the rectifier failed open-circuited.
A PEBB based system has the ability to reconfigure in case of a fault condition.
Whereas, the conventional system suffers from the drawback that if one of the legs of the
rectifier switches fails then the system has to be shut down. Thus we need to have redundancy
in the system and this increases the cost of the system. A PEBB based converter can assure
reliable delivery of electric power to the loads, high system efficiency and flexibility in system
operation. The local controller has communication ports to receive information regarding the
system state and fault situation from the system controller and it can reconfigure the system in
case one of the PEBB cell fails open-circuited.
Chapter 2
75
Also, the issues in the modeling and control of four leg inverter were investigated in
this chapter. The effect of power stage coupling and sampling delay on the control design has
been studied. It was found that digital implementation of the controller introduces a sampling
delay in the system and this places a severe constraint in control design. It was found that
loading on the inverter changes the control-to-output transfer function and must be taken into
account while designing the loop gain. Two control loop designs were presented. The
performance of the inverter with the two designs was presented.
The ability of a four leg inverter in dealing with unbalanced and non-linear loads was
presented. It was established that in order to deal with unbalanced load, the loop gain must
have sufficient gain at 2 ω where ω is the fundamental output frequency (i.e. 60 Hz). A
diode rectifier was used as an example of a typical non-linear load. The input current drawn by
the rectifier has significant frequency components at ω , 5 ω , 7 ω , 11 ω . It was shown that
insufficient loop gain at these frequencies result in distorted output voltages. And, these
voltage distortions can be reduced by designing a complex 4 zero 5 pole voltage loop
compensator.
Chapter 2
76