Gate Oxide Degradation
R. Jacob Baker and Bill Knowlton
‰
Microwave test structures
◙
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‰
The weakest link (gate oxide stress)
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Motivation
Why oxide is the weakest link
Experimental results
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What’s been done
What we’re doing
Device stress
Circuit stress
Summary and publications
1
What has been done
Design of Schottky diodes, first-chip
‰ Re-design due to spacing problems
‰ Characterized Schottky detector circuit below
‰
2
Circuit Characteristics
Schottky Detector Circuit
.control
destroy all
run
plot vin
plot vout
.endc
D1 VD 0 dmod 30
C1 Vin VD .5p
R1 VD Vout 1k
C2 Vout 0 10p IC=0
Vin Vin 0 sin 0 500m 1G
.TRAN .1n 30u
.MODEL dmod D vj=0.3 cjo=0 tt=0
rs=10
.end
3
Measured Results
Several different types of test structures
‰ Measured the DC voltage out as a function of
microwave power applied to the test structure.
‰
60
55
50
45
40
35
30
25
20
15
10
5
0
Diode 50int
Diode 40int
1
0.
3
0.
39
81
0.
63
1
Diode 30int
0.
1
0.
15
85
0.
01
0.
01
58
0.
02
51
0.
03
98
0.
06
31
DCout (mV)
Diodes
Pin (W)
4
We also looked at the frequency behavior of the
circuit.
Dcout vs Input Frequency
Power=-10dbM
10
9
8
7
6
Diode=900um^2
5
Diode=1600um^2
4
3
Diode=2500um^2
2
1
19
00
17
00
15
00
13
00
11
00
90
0
70
0
50
0
30
0
0
10
0
DCout (mV)
‰
Freqency (MHz)
5
Current Activities
‰
We are now integrating the Schottky detector with
various circuits to characterize change with DC bias
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‰
Pass Gate
Transmission Gate
Inverter
Self-Biasing Differential Amplifier
Waiting for fabrication through MOSIS
6
‰
Layout Schematics
Pass Gate
Schematic
Transmission
Gate Schematic
7
‰
Layout views
Pass Gate Layout
Pass Gate inset
8
‰
Layout views cont.
Transmission Gate Layout
TG inset
9
‰
Layout Schematics cont.
Inverter Schematic
Self-bias diff-amp
Schematic
10
‰
Layout views cont.
Inverter Layout
Inverter inset
11
‰
Layout views cont.
Layout self-bias diff-amp
Inset diff-amp
12
Motivation
Drain
+V
Gate
+V
Source
VDD
tox
Gate
-V
Drain
+V
Oxide
p+
Oxide
p+
p+
+
+
+
+ +++++
+ ++
+
n-type
Bulk
VDD
Source
VDD
p+
n-type
Bulk
VDD
13
Motivation
‰
Doubling of transistors every couple of years
Gordon Moore. http://www.intel.com/research/silicon/mooreslaw.htm
14
Motivation
MV
1V
E=
= 1 .4
7 nm
cm
V
E=
tox
E
1V
MV
E=
=5
2.0nm
cm
MV
4V
E=
= 20
2.0nm
cm
4V
MV
E=
= 5 .7
7 nm
cm
-V
E
-V
tox
Oxide
Source
Drain
Source
Drain
tox decreases
New Reliability Issues
1R.
J. Baker, H. W. Li, and D. E. Boyce, "CMOS: Circuit design, layout, and simulation," IEEE Press, pp. 201-228, 1998.
15
Statement of Work
Investigate simple integrated circuit
response to low-level leakage current
degradation in 2.0 nm gate oxides
How defects accumulated over time in
gate oxides affect circuits
16
Measured Results
Observed effects in 3.2 nm gate oxides:
What happens to 2.0 nm gate oxide circuits?
‰
Will comparable gate oxide degradation produce comparable
circuit response?
‰
Will thinner oxide circuits prove more susceptible to oxide
degradation?
17
Measured Results
3.2 nm Oxide Degradation
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Observed degradation
and breakdown
mechanisms:
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WP/LP = 25 µm/ 25 µm
AOX = 6.25 x 10-6 cm2
Stressed induced
leakage current (SILC)1,2
Soft breakdown (SBD)3,4
Limited hard breakdown
(LHBD)5
Hard breakdown (HBD)
1
D. J. DiMaria, JAP, vol. 86, pp. 2100-2109, 1999
B. Ricco, et al., IEEE TED, vol. 45, pp. 1154-1555, 1998.
3 S. Lombardo, F. Crupi, and J. H. Stathis, IEEE IRPS, pp 163-167, 2001.
4 B. P. Linder, et al., IEEE EDL, vol. 23, pp. 661-663, 2002.
5 W. B. Knowlton, et al., IEEE International IRW, pp. 87-88, 2001.
2
18
Comparison of Oxide Degradation
3.2 nm pMOSFET
‰
‰
WP/LP = 25 µm/ 25 µm
AOX = 6.25 x 10-6 cm2
2.0 nm pMOSFET
‰
‰
WP/LP = 10 µm/ 1 µm
AOX = 1 x 10-7 cm2
BD Mechanisms less clear for 2.0 nm Æ focus on low leakage regime
19
CVS Technique
‰
Focus on low leakage regime
1S.
Lombardo, J. H. Stathis, and B. P. Linder, PRL, vol. 90, 2003. 2S. Lombardo, et al., "Breakdown transients in ultra-thin gate oxynitrides," presented at
IEEE ICICDT, 2004. 3D. J. DiMaria, JAP, vol. 86, pp. 2100-2109, 1999. 4B. Ricco, et al., IEEE TED, vol. 45, pp. 1154-1555, 1998.
20
Experimental
Wafer-level stress and characterization
Inverter
nMOSFET
Switch
Matrix
D
G
Sp ,Bp
Gp
Gn
B
S
Dp
Dn
pMOSFET
S
G
Sn, Bn
B
D
◙
◙
tOX = 2.0 nm
WP, N/LP, N = 10 µm/1 µm
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0.1 µm CMOS process
Nominal operating voltage: 1 V
21
Experimental Procedure
Fresh Inverter Characterization
VTC and VT
Fresh MOSFET Characterization
IG-VG, ID-VD, ID-VG
Source
Gate
CVS pMOSFET
X amount of time
+
Post Inverter and
MOSFET
Characterization
N
Z Cycles
Completed
?
Well
Drain
Stress configuration
1
End
Y
1F.
Crupi, et al., IEEE TED, vol. 48, pp. 1109-1113, 2001
22
Experimental Procedure
Inverter parameters
defined
‰
Sample voltage transfer
characteristics (VTC)
pMOS on
1.8
Voltage Output
High (VOH)
1.5
increased
pMOSFET Vth,P
0.9
Voltage Switching
Point ( VSP )
increased
nMOSFET Vth,N
0.6
0.3
0
0
0.3
0.6
0.9
1.2
VIN (V)
Sample voltage-time
(V-t) domain
1.5
nMOS on
Output Voltage (VOUT)
1.5
VOUT
Max
Voltage Output Low
( VOL )
Fresh
Input Voltage (VIN)
1.8
1.8
Voltage (V)
VOUT (V)
1.2
1.2
II
0.9
I
Falling
signal
0.6
Rising
signal
VOUT
0.3
tf
Min
tr
0
0
200
400
Time (µs)
600
800
23
PMOSFET CVS and IG-VG
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Observed gate leakage current increase (2.0 nm)
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Accumulation mode ~ 2 to 3 orders of magnitude
Inversion mode < 1 order of magnitude
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Inverter Voltage Transfer Characteristics
Fresh Æ E level degradation:
1
◙ ∆ VSP ~8% shift left
◙
1R.
Output behavior transitions from 1 to 0
J. Baker, H. W. Li, and D. E. Boyce, "CMOS: Circuit design, layout, and simulation," IEEE Press, pp. 201-228, 1998.
25
Inverter Time Domain
3.2 nm pMOSFET
Fresh Æ LHBD
∆ rise time1 ~32%
1R.
2.0 nm pMOSFET
Fresh Æ E level degradation
∆ rise time1 ~36% to 62%
J. Baker, H. W. Li, and D. E. Boyce, "CMOS: Circuit design, layout, and simulation," IEEE Press, pp. 201-228, 1998.
26
Degraded Inverter Characteristics –
Why?
What aspect of device characteristics may
be causing the inverter to respond to the
degradation in this manner?
27
PMOS ID-VD (Drive Current)
Fresh Æ E level degradation:
◙ ∆ IDrive ~40% decrease
◙ ∆ VTH,P ~17% to 20% shift
◙ ∆ GM, MAX ~16% to 19% decrease
2.0 nm pMOSFET
28
Relation to Logic Technology
FPSN
FPFN
“Corner Parameters”1
TPTN
SPSN
Fresh Æ E level degradation:
◙ ∆ IDrive ~40% decrease
◙ ∆ VTH,P ~17% to 20% shift
◙ ∆ GM, MAX ~16% to 19% decrease
1MOSIS,
SPFN
Typical logic process:
◙ ∆ IDrive ~6% decrease
◙ ∆ VTH,P ~10% shift
◙ ∆ GM, MAX ~7% decrease
“AMIS C5N/C5F Family Process: SPICE corner models, “4676 Admirality Way, Marina del Ray, California 90292-6695 USA, 2004.
29
Conclusions
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Dramatic decrease in inverter performance
directly related to:
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◙
‰
∆ IDrive (decrease)
∆ VTH,P (increase) and ∆ GM (decrease)
For thinner oxides:
◙
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Inverter circuits more sensitive to degradation
Circuit failure may result before a definite BD event
30
Future Work
‰
NMOS degradation
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Circuit level inverter stress
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Circuit operation effects
Devices effects
Circuit operation effects
Device effects
Modeling inverter performance
31
2004 Publication Summary
Cheek, Betsy J., Stutzke, Nate, Santosh Kumar, R. Jacob Baker, Amy J. Moll and William
B. Knowlton, Investigation of Circuit-Level Oxide Degradation and its Effect on CMOS
Inverter Operation Performance and MOSFET Characteristics, in proceedings of the 2004
IEEE International Reliability Physics Symposium (April, 25-29, 2004) pp. 110-116.
M. L. Ogas, R. G. Southwick III, B. J. Cheek, C. E. Lawrence, S. Kumar, A. Haggag, R. J.
Baker, W. B. Knowlton, Multiple Waveform Pulse Voltage Stress (MWPVS) Technique for
Modeling Noise in Ultra Thin Oxides, poster presentation at 2004 IEEE Workshop on
Microelectronics and Electron Devices (April 16, 2004).
Dorian Kiri, Michael L. Ogas, Ouahid Salhi, Richard G. Southwick III, Gennadi Bersuker,
Betsy J. Cheek, William B. Knowlton, Investigation of Ultra Thin Gate OxideReliability in
MOS Devices and Simple ICs, poster presentation at 2004 IEEE Workshop on
Microelectronics and Electron Devices (April 16, 2004).
M. L. Ogas, R. G. Southwick III, B. J. Cheek, R. J. Baker, G. Bersuker, W. B. Knowlton,
Survey of Soft Breakdown (SBD) in 2.0 nm Gate Oxides in MOS Devices and Inverter
Circuits, accepted for oral presentation at 2004 IEEE International Integrated Reliability
Workshop (Oct, 20-23, 2004).
Betsy J. Cheek, Santosh Kumar, R. Jacob Baker, Amy J. Moll and William B. Knowlton,
Examination of Transistor-Level Current Limited Hard Breakdown (LHBD) and Its Effect
on CMOS Inverter Circuit Operation, submitted for publication to IEEE Transactions on
Electron Devices.
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