Technological Studies
Applied Electronics
(Advanced Higher)
7857
September 2000
HIGHER STILL
Technological
Studies
Applied Electronics
Advanced Higher
Support Materials
*+,-./
This publication may be reproduced in whole or in part for educational purposes provided that no profit
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First published 2000
Higher Still Development Unit
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CONTENTS
APPLIED ELECTRONICS
Outcome 1 – Sequential Logic Devices
When you have completed this unit, you should be able to:
• describe correctly the operation of common sequential logic devices;
• describe how D-type and J-K bistables are used to construct sequential logic
systems;
• interpret the operation of a sequential logic system;
• construct sequential logic systems;
• use appropriate test equipment to verify the operation of a sequential logic system.
Before you start this unit you should have an understanding of:
• the operation of combinational logic systems;
• truth tables;
• use of circuit test equipment;
• use of prototype boards (breadboards);
• use of a circuit simulation program (e.g. Crocodile Clips).
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Introduction
Logic circuits have digital inputs and outputs (0’s and 1’s)
The 0’s and 1’s are used to produce binary numbers.
A single 0 or 1 is known as a Binary digiT (or BIT for short).
Eight BITs make up a byte.
A computers memory may be measured in kilobytes, Megabytes, Gigabytes etc.
Two types of logic circuits exist:Combinational Logic Circuits
Here, the output of the circuit is completely determined by the state of the inputs, as
soon as the inputs change, the effect on the output can be immediately seen.
Sequential Logic Circuits
Here the output not only depends on the state of the inputs but the order (or sequence)
in which the inputs change. A sequential logic circuit has therefore to “remember”
the previous inputs in order to check the sequence. These “memory” circuits are
called bistables (or flip flops, or latches).
A bistables circuit has two (hence “bi”) stable outputs (0 or 1).
A monostable has only one stable output (if forced into the “wrong” state in will
revert back to its stable state).
An astable has no stable output state and will continually change between one state
and the other.
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The S-R bistable
Consider the circuit shown in figure 1.
A
O UTP U T Q
B
AE.AH.LO1 fig 1
Assume the output of inverter A is 0. Since this is fed into inverter B, its output (and
hence output Q) will be 1. This 1 is fed back to inverter A and hence its output will
be 0 – this circuit is in a stable state with output Q = 1.
Conversely, assume the output of inverter A is 1, the output of B (and hence output Q)
is 0. This is fed back to A and hence its output will be 1 – the circuit is still in a stable
state but this time output Q = 0.
This circuit is a bistable since it has two stable states.
Both states are equally stable and equally valid. When the circuit is first switched on,
we have no way of knowing if Q will =1 or if Q will = 0.
Now consider adding two switches as in figure 2.
+
+
S
R
A
B
O UTP U T Q
AE.AH.LO1 fig 2
Pressing S momentarily will cause the input to A to become 1, its output will become
0, this is fed into inverter B hence output Q = 1. Q will remain at 1 even when S is
switched off since the circuit is in a stable state.
Pressing R momentarily will cause the input of B to become 1, hence output Q = 0.
Again the circuit is in a stable state and Q will remain at 0.
Pressing S causes Q = 1, the circuit is said to be Set.
Pressing R causes Q = 0, the circuit is said to be Reset.
It should be noted that since B is an inverter, the input to B will always be the
opposite of Q i.e. NOT Q , normally written as Q (Q bar).
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A
B
Q
Q
AE.AH.LO1 fig 3
The accepted diagram for an SR (sometimes also called an RS) bistable is shown in
figure 4.
S
Q
R
Q
AE.AH.LO1 fig 4
Summary of the operation of the SR bistable
If S = 0 and R = 0, Q = whatever it was at before (0 or 1).
If S = 1 and R = 0, Q = 1, the bistable is Set.
If S = 0 and R = 1, Q = 0. The bistable is Reset.
If S = 1 and R = 1, a problem exists since both the inputs and the outputs of the
inverters are forced to be high. This situation is normally avoided in the circuit
design.
Activity 1.1
Construct the circuit shown below using the “Croc clips” simulator.
Test the bistable to ensure that the output Q can be Set or Reset.
This circuit could be used in an alarm. If the bistable is Set, the alarm will continue to
be activated until it is Reset.
Activity 1.2
Increase the number of switches and include a buzzer in the circuit shown above so
that the “alarm” will sound if any of the Set switches are pressed.
Technological Studies: Applied Electronics (AH)
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Activity 1.3
Construct the circuit shown below using the “Croc clips” simulator.
This type of circuit might be used in quiz shows. Test its operation and give a written
explanation of how it works.
Technological Studies: Applied Electronics (AH)
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It is normally very bad practice to connect the output of gates directly to the positive
power lines ( as with R and S in figure 2). Set – Reset bistables however can be
constructed using NOR gates as in figure 5 or NAND gates as in figure 6
S
Q
Q
R
AE.AH. LO1 fig 5
S
X
R
Y
Q
Q
AE.AH. LO1 fig 6
NAND gates X and Y act as inverters (required since the output of NANDS only go
high if one or other of the inputs is low).
Activity 1.4
Using “Croc clips” or a similar software package, construct the SR bistable shown in
figure 7
AE.AH.LO1 fig 7
Test the circuit and complete the truth table shown on worksheet 1.1
What can you say about the output Q when the two inputs (R and S) are 1 ?
Assignment 1.1
The diagrams in figure 8 show the traces of signals applied to the Set and Reset inputs
to an SR bistable
Technological Studies: Applied Electronics (AH)
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1
S
0
1
R
0
AE.AH.LO1 fig 8
On worksheet 1.2, complete the corresponding traces that would appear at outputs Q
and Q .
Assignment 1.2
Construct a truth table to show that the situation “Set = 1 and Reset = 1” is avoided
by using the circuit shown in figure 9.
S
SET
Q
R
RESET
Q
AE.AH.LO1 fig 9
Activity 1.5
Using “Croc clips” construct the circuit shown in figure 10.
S
Q
10K
R
Q
1K
100µ F
0V
AE.AH.LO1 fig 10
Press and release the switch.
Describe what happens and explain the operation of this circuit.
The circuit shown in figure 10 can be used to lengthen the duration of a pulse e.g. in
an electronic keyboard, the note continues to sound even after the key is released.
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Astable multivibrators (or clocks)
You should have discovered that the circuit shown in figure 10 acted as a monostable
circuit, i.e. it had only one stable output (Q = 0). If the output is forced to be 1 (when
the circuit is set) it will revert back to its stable state (Q = 0).
With the addition of other components, an SR bistable can be made to operate as an
astable circuit, i.e. one where the output oscillates between 1 and 0.
Astable circuits are widely used to produce clock pulses. These pulses can be used to
control the rate at which steps in a sequence are processed.
The “555” integrated circuit has been specifically designed to be used as a monostable
or astable device. Its block diagram is shown in figure 11.
R
1/
3 Vcc
R
2/
3 Vcc
TRIG G ER
(PIN 2)
O UTPUT
(PIN 3)
R
+Vcc
(PIN 8)
0V
(PIN 1)
DISCH ARG E
(PIN 7)
CO M PARATO R
INVERTING
BUFFER
SR
BISTABLE
CO M PARATO R
THRESHO LD
(PIN 6)
F.M. INPUT
(PIN 5)
RESET
(PIN 4)
AE.AH.LO1 fig 11
The 3 resistors between pin 8 and pin 1 (inside the IC) set the voltages for the two
comparitor circuits to be +2/3 Vcc and + 1/3 Vcc as shown.
If Vthreshold > 2/3 Vcc, the SR switches on, the output goes low and the discharge
transistor conducts.
If Vtrigger < 1/3 Vcc, the SR switches off, the output goes high and the discharge
transistor switches off.
The pin out diagram for the 555 is shown in figure 12
Technological Studies: Applied Electronics (AH)
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1
2
3
4
0V
TR IG G E R
O UTP U T
R ES E T
8
7
6
5
+V cc
D IS C HA R G E
TH RE S HO LD
FM IN P UT
(O P TIO NA L)
AE.AH.LO1 fig 12
Consider the circuit shown in figure 13
+V cc
R1
S
1
2
3
4
8
7
6
5
R2
C
0V
AE.AH.LO1 fig 13
When S is pressed, the trigger voltage (pin 2) falls to 0V and the output (pin 3) goes
high. When S is released, the capacitor starts to charge up through resistors R1 and
R2. When the voltage at the threshold (pin 6) reaches 2/3 Vcc the output goes low, the
discharge transistor conducts and the capacitor is discharged.
N.B. The capacitor charges through R1 + R2 but discharges through R2 only. The
time taken to charge is therefore greater than the time taken to discharge.
The temptation of making R1 = 0 (thus making the charge and discharge time the
same should be avoided since this would mean the discharge transistor being directly
connected to +Vcc with no load resistor – resulting in a very hot 555! R1 should have
a minimum value of 1k.
Now consider the circuit shown in figure 14 (power connections for pins 8, 1 and 4
have been omitted for clarity)
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R1
1
2
3
4
8
7
6
5
R2
C
0V
AE.AH.LO1 fig 14
In figure 14, the trigger is also connected to the capacitor.
Initially the capacitor is discharged (at 0V) hence Vtrigger = 0, the output (pin 3) is at 1
and the capacitor starts to charge through R1 and R2.
When Vthreshold > 2/3 Vcc, the output goes to 0 and the capacitor discharges through
R2. This time, when the trigger voltage (the voltage over the capacitor) gets to less
than 1/3Vcc, the output changes to 1 and the capacitor starts to charge again. The
process continually repeats with the capacitor charging and discharging between
1/3Vcc and 2/3Vcc and the output continually changing between 1 and 0.
Typical voltage diagrams are shown in figure 15
Vcap
2/
3
1/
3
Vcc
Vcc
t
OUTPUT
1
0
t
AE.AH.LO1 fig 15
The 555 now acts as an astable multivibrator circuit producing pulses which may be
used as a clock.
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The initial pulse will be slightly longer than the others since the capacitor is charging
from 0V (thereafter the pulses will be equally spaced).
1 CYCLE
t 1 + t2
ON
O
F
F
t2
t1
ON
O
F
F
ON
AE.AH. LO1 fig 16
The time taken to charge or discharge a capacitor ca be calculated from V0 = Vc e –t/RC
Since the capacitor charges through R1 + R2 and discharges through R2 only, the on
and off times can be determined using the equations
On time t1 = 0.693 (R1 + R2) C
Off time t2 = 0.693 R2 C
The total time for one complete cycle (the period) is then given by
Period T = t1 + t2 = 0.693 (R1 + R2) C + 0.693 R2 C
Hence T = 0.693 (R1 + 2 R2) C
The frequency of the pulses can be calculated from f = 1/T = 1/(0.693 (R1 + 2 R2) C
Hence f = 1.44/( R1 + 2 R2)C
EXAMPLE
Calculate the ON and OFF time and the frequency of the pulses if R1 = 10k, R2 =
100k and C = 100 µF
ON time t1 = 0.693 (R1 + R2) C = 0.693 (110 x 103) 100 x 10 –6
Hence t1 = 7.632 s
OFF time t2 = 0.693 R2 C = 0.693 x 100 x 103 100 x 10 –6
Hence t2 = 6.96s
Frequency = 1.44/( R1 + 2 R2) C = 1.44/(210 x 103) 100 x 10 –6
Hence f =
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Assignment 1.3
a) Calculate the frequency that would be produced by a 555 astable circuit if R1 =
10k, R2 = 10k and C = 10 µF
b) What size of capacitor would be required in order to produce a frequency of 1 kHz
if R1 = 15k, and R2 = 20k
c) A 555 astable circuit is constructed with R1 = 10k, and C = 100 nF. An ntc
thermistor is used as R2 . If the frequency of the circuit is found to be 300 Hz,
calculate the resistance of the thermistor and comment on what will happen as the
temperature of the thermistor increases.
Since pins 4 and 8 are connected to +Vcc, pin 1 to 0V and pins 2 and 7 to the
capacitor, 555 circuit diagrams can become untidy. The circuit symbol for a 555
“clock” circuit is shown in figure 17.
Vcc
R1
4
7
R2
6
O U T PU T
3
2
C
8
5
1
0.1µ F (O P TIO N AL)
0V
AE.AH. LO1 fig 17
Pin 5 is the f.m. input. If it is left unconnected, stray pick up may cause the length of
the timing pulse to change. This can be avoided if pin 5 is connected to 0V through a
small capacitor – only required when timing is absolutely critical.
The 555 can be used as a source or as a sink. In figure 18 a, it acts as a source, when
the output goes high the led will light. In figure 18 b, it acts as a sink, when the
output goes low the led will light.
5V
5V
10K
4
7
330 R
10K
8
4
7
120 K
3
2
6
8
120 K
1
5
3
2
330 R
6
10µ F
1
5
10µ F
AE.AH. LO1 fig 18a & b
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Activity 1.6
Construct the circuits shown in figures 18 a and b onto prototype board and
compare their operation.
Activity 1.7
Construct the circuit shown below. Use a calibrated oscilloscope to measure the
period of the output and compare this with the theoretical value.
5V
5K
4
7
10K
3
2
6
8
1
5
0.1µ F
0V
AE.AH. LO1 fig 19
Activity 1.8
Design and build a 555 clock pulse generator which will produce pulses at a
frequency of 100 Hz.
Activity 1.9
Connect two 555 Ics as shown in figure 20
9V
10K
4
7
10K
8
4
7
220 K
2
1K
6
8
3
1
3
2
5
6
1µ F
0.1µ F
1
5
64 Ω
SPE AKER
0V
AE.AH. LO1 fig 20
Monitor the outputs of both 555s using a twin beam oscilloscope, draw the patterns
obtained and explain their production.
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Clocked Bistables
A clocked bistable is a logic circuit where the information at the inputs is only
transferred to the output when a clocked pulse arrives.
Clocked logic circuits are used in counters, shift registers, computers, microprocessors
etc.
The circuit shown in figure 21 shows how an SR bistable may be clocked.
SET
S
Q
R
Q
C LO C K
R ESET
AND G AT ES
AE.AH. LO1 fig 21
Here the bistable will only set when SET = 1 and the clock pulse = 1
The clock pulse triggers the bistable into accepting the input data.
As long as the clock pulse remains high, the data will be transferred from the inputs to
the output. This type of triggering is known as level triggering.
The symbol for a clocked SR bistable is shown in figure 22
S
Q
R
Q
CK
AE.AH. LO1 fig 22
Bistables can also be designed to operate off low clock pulses (by incorporating a
NOT gate). Its symbol is shown in figure 23.
S
Q
R
Q
CK
AE.AH. LO1 fig 23
Bistable can also be designed to be edge triggered.
Negative edge triggering – here the data will only be transferred from the input to the
output when the clock pulse falls from a high to a low.
Positive edge triggering - here the data will only be transferred from the input to the
output when the clock pulse rises from a low to a high.
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1
1
FALLING
RISING
0
0
NEGATIVE EDGE
TRIGGERING
POSITIVE EDGE
TRIGGERING
AE.AH. LO1 fig 24
Changes in the input data, after the edge, will have no effect on the output until the
next edge occurs.
The D-type bistable.
An SR bistable can have Q = 1 (Set) or Q = 0 (Reset), it is therefore possible to store a
single binary digit (BIT) on an SR bistable by using a NOT gate as shown in figure
25.
D ATA
S
Q
R
Q
CK
AE.AH. LO1 fig 25
If the data is “1”, the Set goes high and the output Q = 1
If the data is “0”, Set goes low (having, by itself, no effect) however, the signal is
inverted and the high signal passed to the Reset hence Q = 0.
This type of bistable is known as the D (for data) type bistable.
D
Q
CK
Q
AE.AH. LO1 fig 26
D-types are normally edge triggered.
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Activity 1.10
Construct the circuit shown below using “Croc clips”.
Data can be made High or Low by toggling the switch On or Off.
The clock signal can be Low, Rising (when just switched on), High (when the switch
is on) or Falling (when just switched off).
By experimenting with the circuit, determine the nature of the clock pulse required to
trigger the D-type bistable in the “Croc clips” package.
An example of a timing diagram for a positive edge triggered D-type is shown in
figure 27
CLO CK
1
0
DATA
Q
1
0
1
0
Q
1
0
AE.AH. LO1 fig 27
Assignment 1.4
The diagram below shows the timing pulses for the Clock and Data inputs.
CLOCK
1
0
DATA
1
0
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Copy these diagrams (twice) and draw the corresponding trace that would be obtained
at Q and Q bar if these pulses were fed into:
a) a positive edge triggered D-type bistable
b) a negative edge triggered d-type bistable.
D-type bistables can also be used to debounce mechanical switches. When a
mechanical switch is closed, the contacts may bounce a number of times before
completely coming together. This produces a train of pulses, not normally noticed in
an electrical system, but which would cause an electronic system to “think” that the
switch had been pressed on and off a number of times. This would provide difficulty
in counting.
Subsequent
bounces
First contact
In an electronic system, a D-type bistable is clocked such that the clocking time is
long enough to take care of any subsequent bounces.
Output
fro m Q
Clock
pulse
Some D-types also have the facility of being Set (Q = 1) or Cleared (Q = 0)
S
D
Q
CK
Q
AE.AH. LO1 fig 28
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Set and Clear functions normally operate off low signals.
When S = 0, Q = 1
When C = 0, Q = 0
When S and C are high, they have no effect on the operation of the bistable.
S and C are useful during counting when the counter can be cleared to zero or set to a
particular number.
When S and C are not required, they should be connected to 1 (if using TTL logic,
they will automatically float to 1 if left unconnected).
Inputs which have no effect on the output until the bistable is “clocked” are said to be
synchronised (to the clock), inputs (like S and C above) which are not dependent on
the clock signal are said to be asynchronous.
The D-type can be made to toggle (i.e. Q changes state on each successive clock
pulse) if Q bar is connected to the D input as shown.
D
Q
O U T PU T
Q
CK
AE.AH. LO1 fig 29
Initially,
On the first clock pulse,
On the second clock pulse
On the third clock pulse
Q = 0 therefore Q bar = 1, hence D =1
D is transferred to Q, Q = 1 therefore Q bar =0 and D = 0
D (now 0) is transferred to Q, Q = 0, Q bar = 1, D = 1
The cycle repeats as for the first clock pulse etc.
A “1” is produced at Q for every two “1”s of the clock pulse. This triggering action is
the basis of a divide by 2 counter – used in binary counting and frequency dividers.
This is sometimes known as a T (for toggle) bistable.
Activity 1.11
a) Construct the circuit shown below using “Croc clips”.
Display the two traces on separate graphs and determine how the period of the clock
pulses compares with the period of the clock pulses appearing at Q.
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b) Connect the Q output to the clock of another T-type bistable as shown.
By increasing the number of T-types in series determine the relationship between the
number of T-type bistables in series and the output frequency of the circuit.
Assignment 1.5
Two D-types are connected as shown below.
Initially outputs Qa and Qb are both zero.
a) Construct a timing diagram to show how the clock, Qa and Qb vary over the first
8 clock pulses.
b) How does the frequency of Qa compare with the frequency of Qb ?
c) Find out what happens to the frequency of the output as the number of D-types in
series increases (each time the last Qbar is fed back to the first D input).
The JK bistable
This is probably the most versatile bistable. It has two inputs (labelled J and K), a
clock input (CK) and, on some, the possibility of setting and clearing (sometimes
known as Preset and Preclear)
S
J
Q
K
Q
CK
AE.AH. LO1 fig 30
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Most JK bistables work off a falling edge clock pulse (as oppose to D-types, where
most operate off a rising edge pulse), great care must therefore be taken if attempting
to use both types in the one circuit.
As before, making S = 0 sets Q = 1, making C = 0 sets Q = 0
N.B. S = 0 and C = 0 should not be allowed at the same time. If S = 1 and C = 1, the
bistable operates under normal clocking conditions (normally left unconnected in TTL
logic). S and C are asynchronous.
Clocked operations are as follows:J = 0 and K = 0
Q stays the same on clocking
J = 1 and K = 0
Q = 1 (Set) on clocking
J = 0 and K = 1
Q = 0 (Reset) on clocking
J = 1 and K = 1
Q toggles to its opposite state on clocking
An example of a JK timing diagram is shown in figure 31.
CK
1
0
J
K
1
0
1
0
Q
1
0
AE.AH. LO1 fig 31
Assignment 1.6
Draw the timing diagrams to show the Q outputs that would occur for a negative edge
triggered JK bistable for the following input pulses.
a)
CLOCK
1
0
J
1
0
1
K
0
Technological Studies: Applied Electronics (AH)
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b)
CLOCK
1
0
J
1
0
1
K
0
The JK can be connected to perform as the other bistables as shown below.
N.B. This JK connected as a D-type will act on a falling edge pulse. This avoids
complications of mixing JKs triggering off falling edges and “true” Ds triggering off
rising edge pulses.
Frequency Dividers
Frequency dividers are required in, for example, digital watches where the 32768 Hz
frequency of a quartz crystal is divided 15 times to provide a 1 Hz signal for the
stepper motor used for the second hand sweep.
We have seen that successive T-type bistable connected together as shown below
progressively divides the clock signal by a factor of two, as such the circuit can be
thought of as a frequency divider since each stage halves the frequency.
Since each subsequent bistable receives its clock pulse from the previous output, the
effects of the changing signal at the input clock therefore takes time to propagate
along the line to the final bistable. This delay is known as the propagation delay
This type of divider is asynchronous.
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We have seen that connecting D-types as shown below can provide division by
2;4;6;8;10 etc depending on the number of bistables used.
These bistables are said synchronous since they all operate off the same clock pulse
This type of divider is much faster however, in order to produce division by a large
number, you require a large number of bistables e.g to divide by 64 you would need
32 bistables as oppose to 6.
Although division by two is important in binary applications, it may also be necessary
to divide by other numbers e.g. in a digital watch, the seconds have to divided by 10
(to give the “tens of seconds”), then divided by 6 (to give the “minutes”) etc.
Division by odd numbers can be achieved by using JK bistables as shown below.
Assignment 1.7
For the circuit shown above, initially outputs Qa and Qb are both zero.
Construct a timing diagram to show how the clock, Qa and Qb vary over the first 8
clock pulses
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Activity 1.12
Construct the circuit shown below using “Croc clips”
a) By analysing the traces at the input and output, determine the frequency division
taking place in this circuit.
b) Add a JK connected as a T-type bistable to this circuit in order to achieve division
of the input frequency by 10.
Counters
Successively dividing by two forms the basis of a binary counter.
It is possible to create binary counters from both D-type and JK-type bistables by
constructing T-type bistables as shown in figure 32.
AE.AH. LO1 fig 32
By using the Q bar output as a clock for the next bistable, a series of one BIT counters
can be made to count any number of pulses in binary.
AE.AH. LO1 fig 33
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These are Binary counters. Qa will represent the least significant BIT
Each bistable will correspond to one BIT, in order to count higher than 1111, more
bistables are added in series.
This type of counter is called a ripple counter since the bistables are asynchronous.
Care must be taken when using ripple counters since there is a propagation delay
between a signal appearing at the input and it finally working its way through the
system to the last bistable. If the counter is read before the signal has worked its way
through the system then an incorrect reading will be obtained.
Activity 1.13
Construct the 4-BIT counter as shown below.
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Press the Reset button in order to set the counter to 0000.
Copy and complete the following table.
Number of clock pulses
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Qd
0
Qc
0
Qb
0
Qa
0
Assignment 1.8
a) Design a counter circuit that will count up to six (Binary 0110) then reset to 0000.
b) Design a counter circuit that will stop when the count reaches ten (Binary 1010).
Activity 1.14
Construct a counter as shown in activity 1.13 but instead of connected the Q outputs
to the next clock, connect the Q bars to the next clock.
Construct a table as for activity 1.13 and state how these two circuits compare in their
operation.
Counters constructed form JK bistables have the advantage that individual bistables
can be preSet or preCleared to a give any particular starting number on the counter.
Activity 1.15
Design a count down timer that will count down from 10 (Binary 1010) to zero,
switch on a red warning LED when the count gets below 5 and sets off a buzzer when
zero is reached.
Activity 1.16
Although computer simulations allow us to design and tests circuits safely and
quickly, their operation is limited by the computer programmers and the speed at
which the computer program runs. Real ICs can operate at very high frequencies
(25MHz).
Construct an astable pulse generator using a 555 with R1 = 10k, R2 = 1M variable and
C = 1µF
Construct a 2-BIT counter using the two D-type bistables on a 7474 TTL IC.
Display the 2 BITs using LEDs with appropriate protection resistors.
Technological Studies: Applied Electronics (AH)
25
Connect the output from the 555 to the counter. If operating correctly, the LEDs
should light in the correct sequence.
Now increase the pulse rate by decreasing the variable resistor. The LEDs should
now appear to be on all the time.
Connect the binary outputs to a twin beam oscilloscope to display the patterns.
Shift registers
A register is a number of memory elements (BITs), each capable of storing a “0” or
“1”. All J-K and D type bistables can be used to make up single bit registers. In
computers, all data and information is passed via binary states. This information has
to be stored, and this is done in registers.
A number containing eight BITs is referred to a BYTE of memory. If we wanted to
transfer a BYTE from one location to another, we would need 8 wires (one for each
BIT). Shifting one complete byte at a time is known as parallel transfer.
AE.AH. LO1 fig 36
This is easy inside a computer since internal communication is along the 8 wires
making up the DATA BUS.
If we want to transfer information from one machine to another, it would be much
more convenient to use a single line rather than 8.
Shifting one bit at a time along a connection is known as serial transfer.
AE.AH. LO1 fig 37
In order to transfer an eight BIT word by serial transfer, 8 clock pulses would be
required (as oppose to parallel transfer where only one is required).
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Since communication into a system may be in serial format there is also the need to be
able to convert the information from serial to parallel.
Shift registers allow us to transfer information from one location to another.
Four types of registers exist:SISO – serial in serial out
PIPO – parallel in parallel out
SIPO – serial in parallel out
PISO – parallel in serial out
Figures 38 and 39 show how serial and parallel transfer can be performed using Dtype bistables.
AE.AH. LO1 fig 38
Serial transfer – data (0 or 1) appears at the data switch, the first clock pulse sends this
to the first bistable, new data appears, the next clock pulse sends this data to the first
bistable, the data that was on this is then transferred to the next bistable etc until the 4BIT word that was in serial appears on the 4 output parallel lines (SIPO).
AE.AH. LO1 fig 39
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A 4-BIT number appears at the input switches. When one clock pulse appears, this
data is transferred immediately to the output (PIPO).
Assignment 19
Draw the symbol for a D-type bistable, then draw the circuit for cross-coupled NAND
gates that would perform the same function.
Assignment 1.10
Draw an arrangement of D-type bistables connected together to form a 4-BIT counter
Assignment 1.11
A D-type bistable has its Q bar output connected to its D input. A square wave is fed
into its C input. Assuming the output Q is initially at 0, draw the input waveform and
the corresponding output waveform that would appear at Q.
Assignment 1.12
The circuit shown in figure 40 shows three D-type bistables joined together. Each one
has a LED connected between the Q output and the 0V line. The input C is connected
to a pulse generator which produces one square pulse each time the switch is pressed.
AE.AH.LO1. fig 40
To begin with, all the LEDs are off, then the switch is pressed 8 times.
a) Describe the state of the LEDs after the 8 presses of the switch.
b) Which LEDs would be on after 5 presses of the switch ?
c) Explain how the system can be used to count the number of people entering a shop
through a door
d) What disadvantages and limitations does this system have in operation ?
Technological Studies: Applied Electronics (AH)
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Assignment 1.13
The circuit below shows three bistables connected to an astable which produces
square waves at a frequency of 8 Hz.
AE.AH.LO1 fig 41
a) What will the frequency of the output be at Q3 ?
b) On worksheet 1.3, draw the graphs to show how the logic levels at Q1, Q2 and Q3
vary over the same time.
Assignment 1.14 (Past Higher 1997 Paper 1 question 8)
Figure Q8 shows a digital system which is used in a disco to illuminate 6V decorative
lamps in a set sequence.
SU B-SY ST EM
D
X
Q
A
CK
Q
B
C
AE.AH.LO1 fig Q8
(a) Name sub-system X.
(b) Worksheet 1.4 shows the timing diagram for the input pulse fed into CK and the
incomplete timing diagrams for the lamps A, B and C. On worksheet 1.4,
complete the timing diagrams for the lamps A, B and C.
(c) It is found that the output current from the logic ICs is not sufficient to operate the
lamps. Explain, with the aid of a circuit diagram, how you could increase the
output current of the logic ICs to operate the lamps.
(d) It is decided that the system is to be altered so that the three lamps light in
sequence, (A then B then C), one at a time, repeating continuously.
A sequential logic control system is to be used to operate the new timing
sequence.
Draw a block diagram of the sequential logic control system, showing all the
individual sub-systems. You should start with the sub-system which generates the
input pulses and finishes with the lamps.
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Assignment 1.15 (Past Higher 1993 Paper 1 question 3)
(a) Name the device represented by the symbol shown in figure Q3(a)
D
Q
C
Q
AE.AH. LO1 fig Q3(a)
(b) redraw the symbol for the device and show the external components required to
produce the output trace Q from the input trace C. See figure Q3(b)
C
1
0
Q
1
0
AE.AH. LO1 fig Q3(b)
(c) State whether the device is positive or negative edge triggered. Justify your
answer.
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APPLIED ELECTRONICS
UNIT 1 WORKSHEETS
Worksheet 1.1
R
S
0
0
1
1
1
0
1
1
0
1
Q
Q
Worksheet 1.2
1
S
0
1
R
0
1
0
Q
1
Q
0
Worksheet 1.3
c lo c k
1
0
1
Q1
0
Q2
1
0
Q3
1
0
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Worksheet 1.4
CK
1
0
1
A
0
B
1
0
C
1
0
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APPLIED ELECTRONICS (AH)
SOLUTIONS
OUTCOME 1
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Technological Studies: Applied Electronics (AH)
34
Activity 1.2
Activity 1.3
When all the bistables are RESET, all the output Q (to the NAND gate) are High.
The output of the NAND is therefore low. This is inverted by the NOT gate to give a
High signal to each of the SET switches. As soon as any Set switch is pressed, that Q
goes high (and the indicator lights), that Q goes low, the output of the NAND goes
high, this is then inverted by the NOT gate and therefore the input to each of the Set
switches goes low. This means that pressing any other Set switch will have no effect
on the circuit. This circuit will therefore indicate which team or person has pressed
their switch first. The circuit can be reset (for the next question).
Activity 1.4
The output Q could be either 1 or 0 dependent on the previous input states (hence
sequential logic)
Assignment 1.1
S
R
Q
Q
Assignment 1.2
S
0
0
1
1
R
0
1
0
1
Set
0
0
1
1
Reset
0
1
0
0
Q
0
0
1
1
Q
1
1
0
0
When S = 1 and R = 1 the gate network ensures that Set =1 and Reset =0
Technological Studies: Applied Electronics (AH)
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Activity 1.5
When the switch is pressed, the bistable is Set, Q = 1 and the indicator comes on.
This high signal is used to charge the capacitor through the resistor, eventually the
voltage over the capacitor becomes high enough to Reset the bistable, Q = 0, the
indicator goes off and Q =1. This high signal switches the transistor on which causes
the capacitor to discharge (ready for the next switch pulse). The effect is to
cause the indicator to stay on for a length of time (determined by the size of R and C)
Assignment 1.3
a) f = 4.8 Hz
b) C = 26 nF
c) R2 = 19 k As the temperature rises, the size of R2 decreases causing the
frequency to increase.
Activity 1.6
Both leds flash on and off at the same frequency. Circuit A lights the led when the
output of the 555 is high, circuit B when the output is low however since R1 is << R2,
the On and Off times are almost equal and therefore there should be no appreciable
difference in the two operations.
Activity 1.7
theoretical frequency = 576Hz
(Precision of the oscilloscope will limit the actual measurement obtainable)
Activity 1.8
Any suitable combination of R1, R2 and C giving freq = 100 Hz
e.g. R1 = 10 k, C = 0.1µF, R2 = 67k
Activity 1.9
The first 555 acts as a free running astable of frequency 3.2 Hz.
When the output of this 555 goes high, it triggers the second 555 to produce pulses at
a frequency of 1200Hz
Activity 1.10
This D type bistable switches on a rising pulse.
Technological Studies: Applied Electronics (AH)
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Assignment 1.4
positive edge triggered
negative edge triggered
clock
data
Q
Qbar
Q
Activity 1.11
a) Clock pulses are produced at twice the frequency as those at the Q output
b) Each bistable successively divides the previous freqency by 2.
n
Hence for an input frequeny of F, for n bistables, the output frequency will be F/2
Assignment 1.5
clock
Qa
Qb
b) The frequency of Qa = Qb
c) For an input frequeny of F, for n bistables, the output frequency will be F/2n
Assignment 1.6
a)
clock
J
K
Q
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b)
clock
J
K
Q
Assignment 1.7
clock
Qa
Qb
Activity 1.12
a) divide by 5
b)
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Activity 1.13
N
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Qd
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Qc
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
Qb
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Qa
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Assignment 1.8
a)
b)
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Activity 1.14
N
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Qd
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
Qc
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
Qb
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
0
1
Qa
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
The circuit in Activity 1.13 performs a count-up function, the circuit in Activity 1.14
performs a count-down function.
Activity 1.15
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Assignment 1.9
Assignment 1.10
Assignment 1.11
clock
Q
Assignment 1.12
a)
b)
c)
d)
all leds would be off
on, off, on
any suitable switch e.g. breaking the light beam to a photo diode
can only count up to 7
Technological Studies: Applied Electronics (AH)
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Assignment 1.13
a) 1 Hz
b)
clock
Q1
Q2
Q3
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APPLIED ELECTRONICS
Outcome 2 – Sequential Control
When you have completed this unit, you should be able to:
• State and explain the function of the main elements of a sequential logic system
• Analyse a logic array
• Use a computer simulator to evaluate a sequential control system
• Construct a sequential control system to meet a given specification.
Before you start this unit you should have an understanding of:
• S-R, J-K and D type bistables
• Counter and divider circuits
• Combinational logic arrays
• Boolean expressions.
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Introduction
Digital methods of measurement can be made more accurate (by adding another digit
to the display) than their analogue equivalent, they are less likely to be misread and
often need fewer adjustments to their calibration once set.
Clocks, bistables, dividers, counters, registers and logic arrays form the basic building
blocks of all digital electronic systems.
Since these blocks are used extensively, dedicated ICs have been manufactured to
carry out these particular functions e.g. the TTL IC 7493 is a 16 BIT ripple counter
Activity 2.1
Use the “Croc clips” simulation to construct the 4-BIT counter shown below.
Use an AND gate to get the counter to Reset on 6 (0110 in binary).
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Decoders
Digital circuits count using base 2 and will produce a Binary number (e.g. 100110).
Humans count in base 10 and produce a decimal number (e.g. 5698).
There is therefore a need to convert the binary number into its decimal equivalent.
This is known as decoding.
Consider decoding a 2-BIT number into its decimal equivalent.
The table below shows the binary number and its decimal equivalent.
Binary number
0 0
0 1
1 0
1 1
Decimal
0
1
2
3
Now consider each BIT to be a separate logic input and determine the Boolean
expression required to give a high output for each combination.
B
0
0
1
1
A
0
1
0
1
A• B
A• B
A• B
A• B
These expressions can now be used to build a logic array of gates in order to decode
the binary number to its decimal equivalent.
(The logic array could be simplified or reduced to its NAND equivalents)
Assignment 2.1
a) Copy and complete the above decoder circuit to show how the remaining numbers
could be decoded.
b) Derive the Boolean expression and draw the logic array that would decode the
binary number 1011 to give a High output.
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BCD numbers
A 4-BIT counter will count from 0000 (decimal zero) to 1111 (decimal fifteen),
humans count from 0 to 9 (then carry a “1” onto the next significant digit i.e. 10, ten!).
If the counter is designed only to count from zero to nine only, then the number it
produces is called a Binary Coded Decimal number (BCD).
e.g. a Binary number of 10010111 would convert to 1+2+4+0+16+0+0+128 = 151
a BCD number of 10010111 is split into two 4-BIT word lengths 1011 and 0111,each
individual word is then converted to its decimal equivalent 1001 = 9, 0111 = 5, hence
95, ninety five!
BCD numbers are easier and quicker to decode back to a decimal number however
they require more storage memory than using “pure” binary numbers.
Activity 2.2
a) Use an AND gate to reset the 4-BIT counter to zero when the count reaches ten.
b) Use the output of the AND gate as the clock pulse for another 4-BIT counter.
(The first circuit will count the “Units”, the second “Tens”, next “Hundreds” etc.)
BCD decoder
The BCD number can be decoded so that each individual input number is converter to
a single individual high output (as above) or it can be decoded in such a way as to
drive an output display which will produce a recognisable decimal character.
The “Croc clips” simulator provides a 4 to 10 line decoder that produces an individual
High output for each BCD input (shown below)
These outputs can be used to drive other devices e.g. LEDs
Activity 2.3
Using the “Croc clips” simulator, design and build a ten second timer circuit with the
following specification:• the count should be displayed by ten LEDs arranged in a circular pattern;
• the colour of the LEDs should indicate the count;
• the count down should start when enabled and stop when the count reaches zero;
• an alarm (which can be switched off by an override switch) should sound at zero.
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46
The “Croc clips” simulator also contains a BCD to 7-segment decoder driver. Each
output is connected to a separate segment on the display. The circuit is shown below.
The decoder driver also has three “enabling” inputs, LT (Lamp Test), BI (Blanking
Input) and EL (Enable Lamps). Each of these inputs could be either High or Low.
(The bar indicates that these functions operate of Low signals). The operation of
these inputs are hierarchical and can be summarised as:If LT = 0 all the outputs go high, all 7 segments will be lit (hence Lamp Test)
If BI = 0 all the outputs go low, all segments will be off (hence Blanking Input)
If EL = 0 all outputs change according to the input BCD (hence Enable Lamps)
Activity 2.4
a) Using the “Croc clips” simulator, construct a circuit with a pulse generator,
counter and BCD to 7-segment decoder driver circuit with the correct enabling
inputs to allow counting to take place.
b) Add a second similar circuit where the clock pulse comes from the first circuit
when its count changes back to 0. (A logic gate is not required since the circuit
works of a falling pulse!)
c) Add a logic array that will Blank the leading zero on the display when the decimal
number is less than 10 i.e. the number eight is displayed as 8 as oppose to 08
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Assignment 2.2
Describe the operation of the circuit shown below making reference to the functions
of the switches and suggest a suitable application for this circuit.
Assignment 2.3
The circuit shown below only contains one decimal but it could easily be expanded.
Write a report on the operation of this circuit indicating: • how the count is produced;
• the function of the bistable;
• a possible use for this type of circuit and;
• one improvement that could be made (giving a circuit diagram if appropriate).
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Assignment 2.4
In the circuit shown below, the four output BITs of the counter are initially all zero.
a) Draw a table to indicate the state of each of the outputs and the logic levels at
positions W and X for the first 8 input pulses.
b) Draw a timing diagram to show the first 8 clock pulses and the outputs at W and
X.
Assignment 2.5
The circuit below shows part of a digital watch.
a) If clock pulses, produced every second, were fed into the initial counter, how long
would it take before the final counter registers 0110?
b) Show how the circuit could be expanded to count up to 12 hours.
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Assignment 2.6
The circuit below is constructed using red, yellow and green LEDs.
Initially, output A is High and the yellow LED is on.
a) Construct a table to show the condition of the outputs A and B and the state of the
three LEDs for the first 8 input pulses.
b) Suggest a possible use for this type of circuit.
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50
c) Redraw the circuit diagram, including extra components and a push switch such
that the sequence will stop when the green LED is on and will only restart when
the switch is pressed.
Assignment 2.7
One of the safety devices in aeroplanes includes lights on the floor, which indicate the
direction in which passengers should go in order to find the nearest exit.
Part of the circuit is shown below.
When enabled, the LEDs light up in sequence indicating an arrow shape.
Show how the circuit could be expanded to include a second arrow such that the
second sequence carries on from the first before recycling back to illuminate the first
arrow again.
Assignment 2.8
The 7493 is an example of a 4-BIT counter constructed from bistables, the initial
bistable is separated from the other three (these three being linked internally).
The pin out diagram for the 7493 is shown below.
(Since unconnected inputs in TTL logic float High, pins 2 and 3 must be grounded if
not in use.)
0V
14
nc
A
D
B
C
reset
nc
nc
nc
1
+5V
7493
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Construct tables showing the outputs and pulse input and hence determine the
operation carried out by the 7493 when it is connected as shown in the following
circuits.
(Supply connections have been omitted for clarity.)
a)
Clock pulses in
7493
b)
7493
Clock pulses in
Activity 2.5
The block diagram below shows a circuit that will count up to ten.
Astable
Clock
Pulse
generator
Binary
counter
BCD to 7
segment
Decoder
driver
Resistor
array
7 segment
display
On prototype board, construct and test the operation of each the following subsystems before linking them together:a) an astable pulse generator using a 555 with R1 = 22k, R2 = 39k and C = 10µF.
b) a binary counter using a 7493 connected to reset on ten
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c) a 7447 BCD to seven segment display decoder/driver. ( The 7447 decodes a BCD
number to provide a grounded output on a particular segment to be lit.)
d) a 330 Ω resistor array connected to a 7-segment (common anode) display.
Extension exercise
Replace the 7447 and 7-segment display with a 7442 (BCD to 10 line decoder) and a
10 bar DIL LED array.
Assignment 2.9 (Past Higher Paper 1998 Paper 1 question 9 b)
The exercise bicycle in the health club has a reed switch fitted to the wheel arch and a
magnet fitted to the wheel rim to allow the number of revolutions made by the wheel
to be counted.
REED SW ITCH
M AGNET
AE.AH. LO2 fig Q9B(1)
A diagram of the electronic system used to process this information is shown in figure
Q9B(2). Sub-system X is included to remove the “switch bounce” from the system.
+5V
S U B-S Y ST E M
X
4-BIT BIN A RY
C O U N T ER
B C D -D
D E C O D ER
LO G IC
A R R AY
LE D
O U T PU T S
0V
AE.AH. LO2 fig Q9B(2)
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(i)
(ii)
(iii)
(iv)
(v)
State why switch bounce must be removed from the system.
Name sub-system X
Give a brief description of how the complete system operates, making
reference to each sub-system in the block diagram.
Show how D-type bistables could be connected together to form the 4-BIT
binary counter.
Rather than use a reed switch, show with the aid of sketches an alternative
electronic method of detecting the number of revolutions made by the bicycle
wheel.
Assignment 2.10 (Past Higher Paper 1998 Paper 2 question 3, part a only)
The truth table shown in figure Q3 shows the sequence used to control the drying
cycle of a tumble drier.
Output
decimal
signal
0
1
2
3
4
5
6
7
8
9
Heater level
High Med Low
(H) (M) (L)
0 0 0
1 1 1
1 1 1
1 1 1
0 1 1
0 1 1
0 1 1
0 0 1
0 0 1
0 0 1
Drum motor
Fwd Rev
(F) (R)
0
0
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
Indicator
Light
ON
0
1
1
1
1
1
1
1
1
1
AE.AH.LO2 fig Q3
(i)
(ii)
(iii)
(iv)
Draw a block diagram showing the main subsystems used in
constructing a hard-wired sequential control system which could be used
to operate the tumble drier.
With reference to the table, describe the operation of the drying cycle.
For each heater level H, M, and L, write Boolean expressions which
describe the control of the heater.
Making use of 2-input NAND gates only, draw a logic diagram which
shows the circuit used to control the heat levels H, M and L.
Assignment 2.11 (Past Higher Paper 1996 Paper 2 question 3)
The bottling plant in a lemonade factory is operated by a sequential control system. A
schematic diagram of the bottling plant is shown in figure Q3A.
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RO LLERS
SLIDING
CARRIAGE
SU PPORT BEAM
CAP
PO SITIO NING
CYLINDER
BO TTLE
FILLING VALVE
CARRIAGE PO SITIO NING
CYLINDER
BO TTLECAP
SH UTE
CO NVEYO R BELT
CO NVEYO R BELT
AH.AE.LO2 fig Q3A
(a) The control sequence is produced by a clock, 3-bit counter and logic array.
(i)
(ii)
Draw a 3-bit counter constructed from negative edge triggered D-type
bistables.
Construct a timing diagram for the 3-bit counter showing the clock pulses
and the 3 outputs (A, B and C).
(b) The control sequence for the bottling process is shown in the truth table Figure
Q3B. A logic “1” signal switches on the conveyor belt, the filling valve and the
turntable motor, and outstrokes the cap positioning and carriage positioning
cylinders. The turntable screws each bottle onto its cap.
(i)
(ii)
Write a Boolean expression for the conveyor belt, filling valve, turntable
motor, cap positioning cylinder and carriage positioning cylinder.
Design a logic array using NAND gates, which will process the signals
from the 3-bit counter to produce the required sequence for the turntable
only.
Signal from
3-bit
counter
C B A
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Conveyor
Belt
Filling
Valve
Turntable
Cap
Positioning
cylinder
Carriage
Positioning
cylinder
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
0
0
1
1
1
0
0
0
0
0
AE.AH. LO2 Figure Q3B
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Assignment 2.12 (Past Higher Paper 1993 Paper 2 question 4)
On a large construction project, batches of concrete are mixed using an automated
process. In the table below the output sequence which is followed by the process is
shown. At various stages of the process, a signal releases measured amounts of sand,
cement, aggregate and water from hoppers into a mixing drum. The drum is rotated
by an electric motor. Concrete is removed from the mixer by means of an auger
driven chute.
Clock
Pulse
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
Sand
Cement
Aggregate
Water
Motor
Auger
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
The following block diagram is an outline plan for an electronic system to control the
process.
CLOCK
BINARY
COUNTER
DECODER
LOGIC
ARRAY
DRIVER
OUTPUTS
(a) Explain the function of each part of the system.
(b) The pin-outs for the binary counter and the decoder chips are shown on
Worksheet Q4. Show on Worksheet Q4 how these devices would be connected
in the system.
(c) The system should be able to set manually to start the process and reset
automatically when the process is completed. With reference to the binary
counter and decoder chips, and using the worksheet, show how this could be
achieved.
(d) With reference to the table, state which clock pulse signal each of the following
outputs:
Sand; cement; aggregate; water and auger feed.
Then develop a logic statement (Boolean) for each output.
(e) Draw a logic system using NAND gates, to process the signals from the decoder
to the outputs.
(f) The signals from the logic array are processed to operate relays controlling
transducers for the output devices. Draw a driver circuit which could be used to
control one of these relays.
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APPLIED ELECTRONICS UNIT 2 WORKSHEETS
Worksheet Q4
Vcc
Vcc
1
1
4
2
2
3
15
3
0
1
14
4
7
B
13
5
9
C
12
6
5
D
11
7
6
A
10
8
0V
8
9
Vcc 16
14
CLOCK
2
13
A
3
12
4
11
CLOCK
D
+Vcc 5
10 0V
B
6
9
R ESE T
C
7
8
BINA RY C O UN TER
D EC OD ER
0V
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0V
57
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APPLIED ELECTRONICS (AH)
SOLUTIONS
OUTCOME 2
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ACTIVITY 2.1
Assignment 2.1
a)
b)
D C B A
1 0 1 1
D C B A
D C B
A
Activity 2.2
a)
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b)
Activity 2.3
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Activity 2.4
b)
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c)
Assignment 2.2
When switch 2 is pressed, the counter and display resets to zero. When switch 1 is
pressed, the bistable toggles, Q =1, the counter is enabled and counting begins.
When switch 1 is pressed again, the bistable toggles again, Q = 0 and the count
stops. This is the operating principal of a digital stopwatch.
Assignment 2.3
Assume that Q = 1 initially. The count is RESET to zero. At the first HIGH enable
pulse, the bistable toggles, Q = 0 and the counter counts the number of pulses coming
from the unknown clock. When the enable pulse goes low, the count stops. At the
next HIGH enable pulse, the bistable toggles and the process is repeated.
Since the enable pulse is high for 1 second, the counter will display the number of
"unknown" pulses received in one second. This circuit is the principle of a frequency
counter.
Possible improvements might include increasing the number of digits, blanking the
zero, blanking the display until the count has finished etc.
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Assignment 2.4
pulse
1
2
3
4
5
6
7
8
D
C
B
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0 RESETS
1 the count
1
this
0
0
0
0
0
0
A
0
1
0
1
0
1
0
0
1
W
0
0
0
0
0
0
1
0
0
X
0
1
1
1
0
1
1
0
1
clock
W
X
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Assignment 2.5
a) 60 minutes
b)
Assignment 2.6
a)
B
A
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
red
0
1
1
0
0
1
1
0
yellow
1
0
1
0
1
0
1
0
green
0
0
0
1
0
0
0
1
b)
This is the same sequence as that used in traffic lights.
c)
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Assignment 2.7
Assignment 2.8
a) divide by 10
b) divide by 5
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APPLIED ELECTRONICS
Outcome 3 – Operational Amplifiers
When you have completed this unit, you should be able to:
• Describe the operation of, and construct, a basic op-amp integrator
• Describe the operation of, and construct, an op-amp Schmitt trigger
• Describe the operation of a simple oscillator circuit
• Evaluate the operation of analogue systems.
Before you start this unit you should have an understanding of:
• The basic op-amp configurations i.e. inverting mode, non-inverting mode, summer,
difference amplifier, comparitor;
• The mathematical operation of integration.
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Introduction
The operational amplifier (op. amp) is a highly adaptable device. By employing
suitable external components, we can construct a.c. and d.c. amplifiers, sinusoidal and
waveform generators, integrators, differentiators and a vast number of other circuits
for various applications.
The op. amp. amplifies the difference between the two input signals (V+ - V-) by the
open loop gain (Ao) of the amplifier.
INV ERT IN G INP UT
+V cc
N O N -INVE RT IN G INP UT
-V cc
AE.AH.LO3. fig 1
The output voltage (Vo) is therefore given by
Vo = Ao (V+ - V-)
An ideal op. amp. will have the following characteristics:An infinite input resistance – this means that the IC will draw zero current through it;
Zero output resistance – this means that its output voltage will not depend on the load
applied to it;
Zero output voltage when both input signals are equal (in practice this is difficult to
achieve so manufacturers have built in an “offset-null” to achieve this);
A very high inherent open loop gain (typically 106 or more).
Since the open loop gain of the amplifier is so large, the difference between the two
inputs must be very small otherwise saturation will occur and the output will swing to
either +VCC or – VCC
e.g. VCC = 10V, Ao = 1 x 106
(V+ - V-) = 10/(1 x 106) = 10µV
this difference is so small that, to all intents and purposes, V+ = V-
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Inverting mode
Since the open loop gain of the op. amp. is very high, using negative feed back as
shown in figure 2 can reduce the gain of a circuit.
Rf
R1
Vin
Vo
0V
AE.AH.LO3 fig 2
Here the non-inverting input is connected to 0V, hence V+ = 0
If saturation does not occur then V- = V+ hence V- = 0V
This means that all of the input voltage (V1) is dropped over R1
The current through R1 can be calculated from Ohm’s law
I1 = V1 / R1
Since the IC is designed to take very little current, all of I1 must flow through Rf
The voltage dropped over Rf is therefore given by Vf = I1 Rf
Since the voltage at the inverting input is zero, the output voltage must be zero minus
the voltage dropped over Rf i.e. Vo = 0 - I1 Rf = - I1 Rf
I1
Rf
I1
R1
0V
V1
Vo
0V
AE.AH.LO3 fig 3
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The voltage gain of any circuit can be calculated from
Av = Vout / Vin
Hence for the inverting circuit,
Av = Vout / Vin = (- I1 Rf ) / (I1 R1)
Av = - Rf / R1
The output voltage is therefore no longer dependent on the open loop gain of the
amplifier, it merely depends on the input voltage and the resistors in the circuit.
Integrator circuit
An op. amp. can be made to perform the mathematical function of integration if the
feedback resistor is replaced by a capacitor.
C
R1
V1
Vo
AE.AH.LO3 fig 4
Since the non-inverting input is still connected to zero volts, if saturation does not
occur, V- = 0V, hence the current through R1 is the same as before,
I1 = V1 / R1
The current this time is used to charge up the capacitor.
Current is defined as the rate of charge flow. If the current is changing (as in charging
up a capacitor), the current at any instant in time is obtained by differentiating charge
(q) with respect to time (t) i.e. I = dq/dt
For a capacitor, q = CV
Substituting, we get I = d(CV)/dt
Since C is a constant for a given circuit,
Rearranging we get:
Technological Studies: Applied Electronics (AH)
I = C (dV/dt)
dV = (I dt)/C
72
The voltage over the capacitor can be obtained by integrating (1/C (I dt))
As before, the output voltage will be zero minus the voltage over the capacitor hence
1
Vo = − ∫ I 1 dt
C
Since I1 = V1 / R1
Vo = − ∫
V1
R1
1
C
dt
Since C and R1 are constants, Vo = −
1
R1
C
∫V
1
dt
Assignment 3.1
The following graphs and equations describe the input voltage applied to an
integrator. Write down the equation and sketch the graph of the output voltage.
a)
R = 10k, C = 1µF,
V1 = 10 Volts
V1
b)
R = 5k, C = 100µF
V1 = 2t Volts
V1
c) R = 1k, C = 10µF
V1 = 3 sin (10t)
V1
t
t
t
AE.AH.LO3 fig 5
If the input voltage to an integrator is fixed then the output voltage will be directly
V t
proportional to time since ∫ V1 dt = V1t hence Vo = − 1
R1 C
Since V1, R1 and C are constants, Vo = - kt where k is a constant. This means that a
graph of V:t should give a straight line of gradient –k (feeding this through an inverter
would produce a gradient of +k).
Vo
Straight line of grad ient k
t
Any circuit which produces an ever increasing (or decreasing voltage is known as a
ramp generator. The voltage at any moment α time.
(The maximum possible output of this circuit would be limited due to the supply
voltage to the op amp.)
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Activity 3.1
a) Construct the integrator circuit shown below.
Since the input voltage to the integrator is a constant (+5V or –5V), the output is
Vt
given by Vo = −
R1 C
Investigate this circuit and write a report indicating the three ways that the slope of the
output voltage curve can be altered.
b) Integrators can be used to change square wave input signals to saw tooth signals.
Replace the switch and 5V supply in the above circuit with a square wave input of
frequency 1 Hz and 0ffset –2.5 V from the signal generator. Investigate, and write
a report on what affect changing the offset, frequency, R and C has on the output
signal.
Assignment 3.2
Two integrators are connected as shown.
a) Determine the equation for the output voltage V3 in terms of V1
b) Determine the equation for the input voltage V1 in terms of V3.
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Assignment 3.3
Three integrators are connected as shown.
The input for op amp 1 is derived from the output of op amp 3. Assuming this is
initially saturated at +9V (say), sketch graphs of the output voltages that would be
obtained at each of the three op amps and explain how each is produced.
The Schmitt trigger
The circuit in figure 6 shows an op. amp. in the comparitor mode. The power to the
IC is restricted to +Vcc and 0V. This means that the output can go positive but cannot
go negative
+V cc = 12V
10K
R1
Vo
R2
10K
0V
AE.AH.LO3 fig 6
Resistors R1 and R2 set the non-inverting input voltage (V+ ) to ½ the supply voltage
(in this example, 6 Volts). If this is greater than the voltage at the inverting input (V), the output will saturate positively and Vo = + Vcc (12V approximately).
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If the light intensity on the LDR is reduced, the voltage at the inverting input will rise,
eventually becoming greater than V+ and the output will saturate negatively (however
since this power supply is restricted, the output will go as low as possible i.e. to 0
Volts) Vo = 0 V.
In practice, because the open loop gain of the op. amp. is so high, the comparitor
circuit is so sensitive that minor changes in either input voltages either side of the
switching point might cause the output voltage to switch high and low repeatedly until
eventually settling down.
This “hunting” effect is reduced by using positive feedback (R3) as shown in figure 7.
+V cc = 12V
R1
10K
10K
R3
R2
Vo
10K
0V
AE. AH. LO3 fig 7
In this circuit, R1 is connected to + Vcc if the output of the op. amp. is also + Vcc
then R3 is also connected to + Vcc this has the effect of making R1 in parallel with R3
hence the voltage at the non-inverting input is set to 8 Volts (10k/15k x 12V).
Now if the light intensity on the LDR changes such that the voltage at the inverting
input becomes greater than 8 V, the output will saturate negative and V0 = 0 Volts.
Since R2 is already connected to 0V, this has the effect of making R3 now in parallel
with R2 , the voltage at the non-inverting input now drops to 4 Volts (5k/10k x 12V).
This means that any minor changes in either voltages will not have any effect on the
output voltage since once the op. amp. has triggered, the voltage at the inverting input
would have to reduce to below 4V before it has any effect.
This type of circuit is known as a Schmitt trigger, it is used to produce immediate
switching without any “hunting” effects, its main purpose is to convert a slow moving
input voltage into a rapid-action transition.
The voltage difference between the “switch on” and “switch off” (in this example, 8-4
= 4Volts) is known as hysteresis.
A typical Schmitt trigger hysteresis curve is shown in figure 8. This shows how the
output voltage would vary as the voltage at the inverting input is varied between 0V to
12 V and back again.
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Vo
V cc
V (-)
0
4
8
12
AE.AH.LO3. fig 8
For reliable operation of logic gates and counters, very fast rise and fall times are
required this is obtained by using logic gates that are Schmitt triggered.
To indicate that a gate is Schmitt triggered, the “hysteresis” sign is included on the
symbol.
AE.AH.LO3. fig 9
Assignment 3.2
a) For the circuit shown in figure 9b, calculate the approximate switch ON and
switch OFF voltages and sketch the hysteresis curve that would be obtained.
15V
8K
8K
24K
AE.AH.LO3. fig 9b
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b) Calculate the switch On and switch Off voltages if the two 8k resistors shown
above were replaced by two 24k resistors.
c) Draw a circuit diagram for any Schmitt trigger, calculate the On and Off voltages
for your design and compare this with the On and Off voltage that would be
required if the positive feedback resistor is removed.
Activity 3.2
Compare the switching action of a “normal” inverter and a Schmitt triggered inverter
by constructing the circuit shown below.
Write a report showing and explaining the difference in the two waveforms.
Oscillator circuits
Consider the Schmitt trigger circuit as shown in figure 10.
12V
R1
10K
10K
R4
10K
C
R3
R2
Vo
10K
0V
AE.AH.LO3. fig 10
Initially, at switch on, the capacitor is discharged therefore the voltage at the inverting
input is zero. Since the voltage at the non-inverting input is not zero, the output will
saturate positively. This has the effect of connecting R3 in parallel with R1 (as before)
and setting V+ to 8 Volts.
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Since the output is at a high voltage, current will start to flow through R4 and the
capacitor will start to charge. As C charges up, eventually V- >V+, the output will
saturate negatively (in this circuit to zero volts) and R3 will now effectively be in
parallel with R2 setting V+ to 4 Volts.
Since the output is now set to 0V, the capacitor will start to discharge through R4, the
voltage over the capacitor will fall until V- < 4 Volts. The output will again go high
and the process will be repeated.
This type of circuit is known as a relaxation oscillator. Since the circuit uses a
Schmitt trigger it produces a good quality square wave output.
The frequency of the output signal depends on C and R4.
The output waveform of this type of oscillator may not be symmetrical.
The mark to space ratio of a square wave pulse generator is defined as the ratio of the
ON time to the OFF time.
on
off
mark
space
For example, if the ON time is 2 seconds and the OFF time is 3 seconds, the mark to
space ratio is 2:3 (or 1:1.5)
Assignment 3.3
A CRO timebase is set to 5ms/div. The diagram below shows the output trace from a
square wave generator.
Calculate the mark:space ratio and the frequency of the pulses.
Assignment 3.4
Square waves are produced at a frequency of 1kHz. If the ON time of a pulse is 0.2
ms, calculate:a) the time taken to produce one complete pulse;
b) the OFF time of the pulse
c) the mark:space ratio of the pulse.
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Activity 3.3
Construct the circuit shown onto prototype board.
Use a CRO to measure the following:
a) the time that the pulse is High;
b) the time that the pulse is Low;
c) the mark to space ratio;
d) the frequency at which the pulses are produced.
Saw tooth (triangular) wave generators.
Integrators can be used to produce “ramp” output voltages if the input voltage is
constant.
If the input voltage to an integrator changes from being a constant positive voltage to
being a constant negative voltage, the integrated output should give a corresponding
negative ramp voltage followed by a positive ramp voltage.
Square wave input
Triangular wave
output
Activity 3.4
Add an integrator to the pulse generator from activity 3.3 in order to produce a
triangular waveform.
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Determine the effect of changing each of the capacitors in this circuit.
Sine wave generators
The circuit below shows a Wien Bridge oscillator.
The circuit is constructed so that C1 = C2 and R1 = R2. The value of these components
determines the frequency of the waves produced. R1 and C1 apply positive feedback
to R2 and C2
The resonant frequency of the circuit if given by
1
f =
2πRC
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Activity 3.5
Construct the Wien Bridge oscillator circuit shown below
Measure the frequency of this circuit and state how it compares with the theoretical
value.
Assignment 3.5
Calculate the resonant frequency that would obtain using a Wien bridge circuit with
the following values of resistor and capacitor:a) R = 1k, C = 2.2µF b) R = 4.7k, C = 10nF
c) R = 100 , C = 100 pF
Assignment 3.6
Calculate suitable values for R and C that would produce the following frequencies in
a Wien bridge circuit:a) 50 Hz
b) 1 kHz
c) 1 Hz
Assignment 3.7
Describe the operation of the circuit shown below making reference to the output
traces that would be obtained at the three points indicated.
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Assignment 3.8
The diagram below shows a Voltage Controlled Oscillator (VCO).
a) Describe the operation of the circuit and explain how the frequency of the output
pulses depends on the input voltage.
This design of VCO has two major drawbacks:1) the input voltage has to be above the voltage set at the inverting input; and
2) the frequency is restricted by the speed at which the mechanical contacts of
the relay can operate.
b) Explain how “drawback” 1 can be overcome by using the circuit below.
c) Draw a suitable circuit diagram that would allow the capacitor to be discharged
electronically i.e. without the need for the mechanical relay.
Assignment 3.9
Draw a block diagram to show and explain how a digital voltmeter might be
constructed by using a VCO and circuits from the previous unit.
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APPLIED ELECTRONICS (AH)
SOLUTIONS
OUTCOME 3
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Assignment 3.1
3
a) V = - 10 t
b) V = - 2 t
V
2
c) V = 30 cos(10t)
V
V
t
t
saturation
t
saturation
Activity 3.1
a) Increasing the input voltage increases the slope of the line. Increasing R or C
decreases the slope of the line.
b) Increasing R or C decreases the slope of the line which means that the amplitude
of the output waveform is reduced. Changing the offset moves the waveform away
from the central position and may result in saturation or clipping of the signal.
Assignment 3.2
(
)
a) V3 = 4 ∫ ∫ V1 dt dt
b) V1 = 0.25 d/dt ( dV3/dt)
Assignment 3.3
If V1 is saturated, V2 = -1/RC
If V1= 9V, V2 = -18t
∫
( V1 dt) Since V1 is constant, V2 = -2 V1t
V
t
saturation
V3 = -1/RC
V
∫
( V2 dt), V3 = -2
∫
(-18t dt) = 18 t
2
saturation
t
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V4 = -1/RC
∫
( V3 dt), V4 = -2
∫
2
(18 t dt) = -12 t
3
V
t
saturation
Assignment 3.2
a) 6.43 V and 12.86 V
b) Values depend on the individual circuit that has been designed.
Activity 3.2
The Schmitt inverter responds quicker and gives a faster fall and rise time producing a
"squarer" pulse.
Schmitt
Assignment 3.3
1.5:2.5 (or 3:5)
50 Hz
Assignment 3.4
a) 1 ms
b) 0.8 ms
c) 1:4
Activity 3.4
Increasing the 100 µF decreases the frequency of the square wave oscillations.
Increasing the 10 µF decreases the gradient and amplitude of the triangular waveform.
Activity 3.5
Theoretical frequency = 15.9 Hz
Assignment 3.5
a) 72.3 Hz
b) 3.39 kHz c) 15.9 MHz
Assignment 3.6
Any suitable combination of R and C such that R x C = 1/(2πf)
-3
-4
b) RC = 1.59 x 10
c) RC = 0.159
a) RC = 3.18 x 10
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Assignment 3.7
The first op. amp. is used in a Wein Bridge oscillator circuit which produces a sine
wave at a frequency of 15.9 Hz. (output 1).
The second op. amp. is used as a Schmitt trigger. This is used to change the sine
wave into a square wave (output 2).
The third op. amp. is used as an integrator. This changes the square wave into a
triangular waveform (output 3).
Output 1
Output 2
Output 3
Assignment 3.8
The op. amp. is used in the comparitor mode. The voltage at the inverting input is set
to 0.82V by the 10k and the 1k potential divider circuit. Initially the capacitor is
discharged. Since this is connected to the non-inverting input, the output of the op.
amp. is negative and the transistor is off. Current from the input voltage flows
through the 50k resistor and the capacitor starts to charge up. Eventually, the voltage
over the capacitor becomes greater than 0.82V and the output of the op. amp. switches
positively. This in turn switches the transistor on, actuating the relay, closing the
relay contacts which in turn short circuits the capacitor, discharging it back to zero
volts, The op. amp. output again becomes negative, the transistor switches off and the
process recycles.
The rate at which the capacitor charges will depend on the rate of current flow. This
in turn will depend on the size of resistor used (50k) and the charging voltage. As the
voltage increases, the capacitor will charge up more quickly. The time taken to repeat
the process will be reduced hence the frequency of the output will increase.
b) Op. amp. 2 is set up as an inverting amplifier of gain -1 (in order to produce a
positive output for the VCO). Op. amp. 1 is set up as a summing amplifier, the
output is the sum of the two input voltages. The 10k and 1k are used to set one of the
input voltages to 0.82V (the voltage set an the inverting input of the VCO). This
means that the voltage sent to the VCO will always be greater than 0.82V (assuming
the input voltage >0) and therefore the capacitor will always charge up causing the
circuit to oscillate.
c) A MOSFET could be used in place of the bipolar transistor
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APPLIED ELECTRONICS
Outcome 4: D-A and A-D converters
When you have completed this unit, you should be able to:
• Understand the need for A-D and D-A conversion
• Construct and describe the behaviour of D-A and A-D converters
Before you start this unit you should have an understanding of:
• Analogue and digital signals
• Operational amplifiers
• Binary counters
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Introduction
Electrical signals which can vary in amplitude between some preset low and some
preset high level are analogue. The signal information is carried by the amplitude of
the signal.
Electrical signals which are either high or low (1 or 0), are digital. The information is
carried either by the length of the pulse or by the sequence of a predetermined number
of pulses (as a Binary Coded Decimal number).
Analogue to Digital converters (A-D)
An A-D converter is a device which can generate a binary number which represents a
particular voltage (the higher the analogue voltage, the higher the binary number).
+V cc
D
C
A-D
CONVERTER
AN ALO G U E
VO LTA G E
IN
B
A
BIN ARY
N UM BE R
OUT
OV
AE.AH. LO4 fig 1
Digital to Analogue converters (D-A)
A D-A converter is a device which produces a voltage which corresponds to a
particular binary number (the greater the binary number, the higher the voltage).
BINARY
NUMBER
IN
D
C
B
A
D-A
CONVERTER
ANALOGUE
VOLTAGE
OUT
AE.AH. LO4 fig 2
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Construction of a D-A converter
A binary number will consist of a series of BITs, each of which may be at a high
voltage (normally +5V) or a low voltage (normally 0V). The D-A converter has to be
capable of combining these to produce an analogue voltage.
The digital signals are combined by using an op amp summing amplifier.
f
RB
VB
RA
VA
Vout
AE.AH. LO4 fig 3
In the summing amplifier shown in figure 3, the output voltage can be calculated from
Vout = -(VARf/RA + VBRf/RB)
(Here VA and VB will be either 5V or 0V depending on the BCD number being
converted)
Successful conversion of the binary number into its analogue equivalent depends on
correctly selecting values for RA and RB. The least significant BIT should have the
least weighting and therefore its voltage should be multiplied by the smallest number
(i.e. bigger input resistor) the next least significant BIT should have twice the
weighting of the previous BIT hence twice amplification (hence half the previous
input resistance).
A 4-BIT D-A converter is shown in figure 4.
SUM M ING
IN VER TING
100K
D
16K
1K
200K
C
400K
1K
B
800K
A
Vsum
Vout
AE.AH. LO4 fig 4
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In the circuit, the digital signals which are fed into A, B, C, and D are high or low (1
or 0) which will correspond to either +5 or 0V. The input voltage of any particular
BIT is therefore 5 x (the logic level). The output from the summing amplifier is
therefore
Vsum = - (5xDx16/100 + 5xCx16/200 + 5xBx16/400 + 5xAx16/800)
Where D, C, B and A are either 1 or 0
The formula can be simplified to
Vsum = -0.1 (8D + 4C + 2B + 1A)
The inverting amplifier (of gain –1) is included to produce a positive output
Vout = 0.1 (8D + 4C + 2B + 1A)
For example, the BCD number 1010 would produce an output voltage of
0.1(8x1 + 4x0 + 2x1 + 1x0) = 0.1(8 + 2) = 1 Volt
Assignment 4.1
For the circuit shown in figure 4, calculate the output voltage that would appear for
the following BCD inputs
a) 0010
b) 1111
c) 1001
d) 0101
Activity 4.1
Construct the circuit shown below (note the changes to the power supply for the op
amps).
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a) For each of the possible combinations of switch inputs, determine the output
voltage.
b) Include another switch in the circuit to represent another BIT. By experimenting
with this circuit, determine its limitations and state how this could be overcome.
Activity 4.2
Construct the circuit shown below.
Sketch the trace that appears at the output of this digital to analogue converter.
Assignment 4.2
A 2-BIT DAC is to be constructed as shown below.
A
B
Vout
The binary inputs (A and B) can be either high at 12V or low at 0V.
Calculate the size of resistors required so that the analogue output voltage is directly
equal to the decimal equivalent of the binary input voltage (e.g. binary 11 gives an
analogue output voltage of 3V)
Assignment 4.3
a) For the circuit shown below, calculate the analogue output that would appear if a
High (1) signal at the input represents 5 Volts.
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1k
1
1k
2k
0
4k
1
8k
1
16k
Vout
0
32k
1
0V
b) Design a 3- BIT ADC using a 5k feedback resistor, where an input High BIT is 3
Volts and the maximum output voltage is not to exceed 10 Volts.
Assignment 4.4
Describe the operation of the circuit shown below and sketch the output trace you
would expect to obtain.
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Construction of an A-D converter
A-D converters rely on comparing the input signal voltage with the (ever increasing)
output voltage of a D-A converter.
BINARY DIGITAL OUTPUT
D C B A
CLOCK
D-A
CONVERTER
BINARY
COUNTER
COMPARITOR
VDAC
Vsig
ANALOGUE
INPUT
SIGNAL
OV
AE.AH. LO4 fig 5
Initially the counter is set to 0 (0000 in binary), the D-A converter changes this to an
analogue output voltage, VDAC (at this time, 0V). VDAC and the analogue input
signal voltage, Vsig are fed into the comparitor circuit. If Vsig > VDAC, the
comparitor output goes high. This means that the high clock pulses will be fed to the
binary counter through the AND gate and the counter will increment (to 0001). The
count will continue to increment until VDAC > Vsig, at this time, the output from the
comparitor will go low and hence the AND gate will be disabled. The count will
cease. The binary digital output at this time will then correspond to the analogue
input signal voltage.
Although the output of a D-A can vary in size, it is limited to varying by steps, this
limits the resolution of the D-A and hence A-D converter. Increasing the number of
BITs into the D-A allows us to reduce the size of each individual step and hence
increase the resolution.
Assignment 4.5
In this particular circuit, you would see the digits counting up before giving the final
reading, show how a PIPO shift register could be used to overcome this.
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Activity 4.3
Construct the circuit shown below.
This circuit has a number of drawbacks. By experimenting with the circuit, determine
three possible drawbacks and suggest how these might be overcome.
Reference voltage of an A-D converter
A-D converters are designed to process analogue signals which have been conditioned
within a set range.
A common range for an 8-BIT A-D is 0-2.55V i.e. a reference input voltage of 2.55V
will give a digital output of 11111111 (255 in decimal).
If the input voltage is not 2.55V, the circuit will generate an 8-BIT word (somewhere
between 00000000 and 1111111) equivalent to the voltage signal applied at the input.
The binary word is found by assigning decimal weightings to each BIT on the digital
output from the device.
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MSB
7
6
5
4
3
2
1
0
A-D
CONVERTER
Vsig
DECIMAL
WEIGHTING
128
64
32
16
8
4
2
1
LSB
0V
AE.AH. LO4 fig 6
.
If an input reference voltage of 2.55V gives 255 BITs then a single BIT corresponds
to a voltage of 2.55/255 i.e. 0.01V. The MSB would therefore correspond to an input
voltage of 128 x 0.01 = 1.28V
MSB
1
0
0
0
A-D
0
0
0
0
CONVERTER
1.28V
B IN A RY
WORD
LS B
0V
AE.AH. LO4 fig 7
The decimal weightings can be converted to voltages in the correct range and then
subtracted from the input signal to produce the equivalent binary word.
MSB
1.28V
0.64V
0.32V
0.16V
0.08V
0.04V
0.02V
0.01V
A-D
CONVERTER
LSB
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For example, an A-D with a reference voltage of 2.55V processes an input signal of
2.05V, calculate the binary word generated.
Vsig = 2.05V
Leaving 0.77
Leaving 0.13
Leaving 0.05
Leaving 0.01
Subtract 1.28
subtract 0.64
can’t subtract 0.32
can’t subtract 0.16
subtract 0.08
subtract 0.04
can’t subtract 0.02
subtract 0.01
(line 7)
(line 6)
(line 5)
(line 4)
(line 3)
(line 2)
(line 1)
(line 0)
1
1
0
0
1
1
0
1
Leaving 0
Hence the binary word produced by 2.05V is 11001101
Assignment 4.6
For an A-D with a reference voltage of 2.55V, calculate the binary word produced by
the following voltages:
a) 1.50V
b) 0.90V
c) 0.50V
d) 2.45V
Assignment 4.7
For an A-D with a reference voltage of 2.55V, calculate input voltages that would
produce the following binary outputs:a) 10010111
b) 10110111
c) 01010011
d) 00111001
Assignment 4.8
For an A-D with a reference voltage of 12V, calculate the binary outputs that would
be produced by the following input voltages:
a) 3.0V
b) 6.0V
c) 9.0V
Assignment 4.9
An A-D converter produces a 12 BIT word. If a reference voltage of 5Volts produces
an output of 111111111111, calculate the input voltages that would produce the
following binary outputs:
a) 000000000001
b) 100111001011
c) 110011011001
Assignment 4.10
An ntc thermistor is to be used as part of a digital thermometer by connecting it to an
8-BIT ADC as shown below.
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+5V
A-D
CONVERTER
At 100oC, the thermistor has a resistance of 4kΩ. At 0oC, the thermistor has a
resistance of 10kΩ. A reference voltage of 2.55V to the ADC produces an output
binary number of 11111111.
The thermistor is placed in boiling water and the variable resistor is adjusted until a
binary output of the ADC is 01100100.
a) Calculate the decimal equivalent of this output voltage.
b) Calculate the input voltage to the ADC.
c) Calculate the size of the variable resistor.
d) Calculate the binary output that would appear if the thermistor were now placed in
freezing water at 0oC.
e) Suggest one problem in using this as a basis for a digital thermometer.
Assignment 4.11
Part of the circuit for an alternative design of ADC is shown below.
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Describe the operation of this circuit making reference to:
• Tr 1 and Tr 2;
• the configuration of op. amp 1 and op. amp 2; and
• the bistable.
Assignment 4.12 (Past Higher 1997 Paper 2 question 2 part b only)
Figure Q2A shows the layout of a plastic extrusion machine. The machine is
pneumatically operated and the process is computer controlled.
At the start of the process, the solenoid-operated release gate opens to allow plastic
powder into the extrusion chamber. After 30 seconds, the release gate closes. The
heating coil surrounding the chamber is then switched on to raise the temperature of
the plastic powder to 200 oC. When this temperature has been reached, the heating
coil is switched off and the pneumatic cylinder ram moves forward slowly.
The ram forces the molten plastic through the die nozzle to produce the extrusion. A
reed switch senses when the piston is fully outstroked and after a delay of 15 seconds
the piston instrokes quickly. One second later the system resets.
PLASTIC
POW D ER
SOLENOID OPER ATED
RELEASE GATE
EXTRUSION
CHAMBER
DIE NOZZLE
TEM PERATUR E
SENSOR
HEATING COIL
RAM
REED SW ITCH
M AGNETIC
PISTON
AE.AH. LO4 fig Q2A
The signal from the temperature sensing sub-system is processed by an A-D converter
at the analogue port of the computer before being read by the microprocessor. The AD has a reference voltage of 1.8 volts which produces a binary word of 11111111.
(i)
(ii)
What is an A-D converter and why is it required an the analogue port of a
computer ?
Calculate the binary word produced by the A-D converter at 200 oC, if the
voltage signal from the temperature sensing sub-system at this temperature
is 1.2V. Clearly identify the least significant bit (LSB).
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Assignment 4.13 (Past Higher 1994 Paper 1 question 8 part e only)
A microprocessor-based monitoring system is used to data log sound signals over a
period of time. It is found that the maximum voltage generated by the sound signals
is 6 V. However, the maximum voltage which may be fed into the microprocessor is
1.8 V.
(i)
Draw a circuit diagram of a suitable signal conditioning system, based on
operational amplifiers, which will allow the signals to be monitored without
damaging the microprocessor. Indicate values of any components used in
your circuit.
(ii)
If the sound signal is fed into the microprocessor through and A-D converter
which has a reference voltage of 1.8 V, write down the 8-bit binary pattern
you would expect from the A-D converter when the sound signal generates a
voltage of 4.8 V. Clearly identify the least significant bit (LSB).
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APPLIED ELECTRONICS
SOLUTIONS
OUTCOME 4
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Assignment 4.1
a) 0.2 V
b) 1.5 V
Activity 4.1
a)
C
B
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Vout
0
1
2
3
4
5
6
7
A
0
1
0
1
0
1
0
1
c) 0.9 V
d) 0.5 V
b) The op. amps. reach saturation. This could be overcome by either reducing the
size of the feeback resistor in the first circuit or by reducing the input voltage to the
switches.
Activity 4.2
Assignment 4.2
RA = 120 k
RB = 60 k
Rf = 10 k
(or any other suitable combination such that RA = 2 x RB and Rf/RΑ x 12 = 1)
two resistors in inverter circuit should be the same size e.g. 10 k
Assignment 4.3
a) 7.03 Volts
b)
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Assignment 4.4
The JK- bistables are connected as a 4-BIT binary counter.
When each Q output goes high, 5 Volts appears at its output. The output resistor and
the 10k act as a voltage divider circuit. The output voltage can be calculated for each
combination of pulses. If two (or more) ouputs are high then the resistors act as
though they are in parallel (before they are then in series with the 10k).
Assignment 4.5
Activity 4.3
i) decimals can be "seen" counting - overcome by using a shift register
ii) "Count" has to be reset manually - could be done electronically
iii) Poor resolution (only one decimal place) - overcome by using more counters
(hence BITS)
Assignment 4.6
a) 10010110 b) 01011010 c) 00110010 d) 11110101
Assignment 4.7
a) 1.52V
b) 1.83V
c) 0.83V
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108
Assignment 4.8
a) 01000000 b) 10000000 c) 11000000
Assignment 4.9
a) 0.00122V b) 3.06V
c) 4.01V
Assignment 4.10
a) 100
b) 1.0V
c) 16k
d) 11000000 (1.92V)
e) Reading increses as temperature decreases (overcome by using a ptc thermistor)
Assignment 4.11
Op amp 1 is configured as an integrator circuit, op amp 2 is in a comparitor circuit.
When Q = 1, the transistor across the capacitor conducts and the capacitor is
discharged. The output of op amp 1 at this point is zero volts. Since the analogue
input voltage at this time is >0 the output of op amp 2 is high. This enables the
counter. At the next input pulse to the bistable, Q = 0 (the transistor, Tr2 switches
off) and Q =1. Transistor Tr1 is now switched on and this provides a constant
voltage source for the integrator circuit. The output voltage of op amp 1 now steadily
rises, eventually, this voltage will become greater than the input analogue voltage, the
output of op amp 2 will go negative and the count will stop.
At the next input pulse to the bistable, Q = 1, the capacitor discharges and the cycle is
repeated.
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