ECE 5745 Complex Digital ASIC Design
Topic 3: CMOS Circuits
Christopher Batten
School of Electrical and Computer Engineering
Cornell University
http://www.csl.cornell.edu/courses/ece5950
Combinational Logic
Sequential State
Part 1: ASIC Design Overview
P P
M M
Topic 4
Full-Custom
Design
Methodology
Topic 6
Closing
the
Gap
Topic 1
Hardware
Description
Languages
Topic 5
Automated
Design
Methodologies
Topic 8
Testing and Verification
Topic 3
CMOS Circuits
Topic 2
CMOS Devices
ECE 5745
T03: CMOS Circuits
Topic 7
Clocking, Power Distribution,
Packaging, and I/O
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Combinational Logic
Sequential State
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CMOS Logic, State, Interconnect
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• Combinational Logic •
Sequential State
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CMOS Logic, State, Interconnect
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• Combinational Logic •
Sequential State
CMOS Inverter Simple RC Model
Close switch when Vin = 0
Vout
Vin
Vdd
Close switch when Vin = Vdd
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A simple RC model for the
inverter can
provide
significant
insight
CMOS
Inverter Simple
RC Model
• Combinational Logic •
Sequential State
Reff
Vin
Vout
Vin
Vout
Cg
Reff
Cd
Reff = Reff,N = Reff,P
Cg = Cg,N + Cg,P
Cd = Cd,N + Cd,P
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The most basic CMOS gate
CMOS Inverter Layout
is an inverter
• Combinational Logic •
Sequential State
VDD
PMOS
WP/LP
Vin
Vout
WN/LN
A
Y
NMOS
GND
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The most basic CMOS gate
is an inverter CMOS Inverter
• Combinational Logic •
Sequential State
Let’s make the following assumptions
WP/LP
Vin
2
Vout
WN/LN
1
1. All transistors are minimum length
2. All gates should have equal rise/fall
times. Since PMOS are twice as slow
as NMOS they must be twice as wide
to have the same effective resistance
3. Normalize all transistor widths to
minimum width NMOS
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• Combinational Logic •
Sequential State
Series Transistors
Adapted from [Weste’11]
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• Combinational Logic •
Sequential State
Parallel Transistors
Adapted from [Weste’11]
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Series and parallel MOSFET networks
Series/Parallel
Transistor
Networks
areother
Natural Duals
provide natural
duals
of each
• Combinational Logic •
Sequential State
A
A
A
B
B
Conducts if A=0
A
Conducts if A=0 OR B=0
A
Conducts if A=0 AND B=0
A
B
B
Conducts if A=1
Conducts if A=1 AND B=1
Conducts if A=1 OR B=1
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More complicated gates use more
Static Logic Style networks
transistorsCMOS
in pullup/pulldown
• Combinational Logic •
Sequential State
VDD
Pullup network, connects output
to VDD, contains only PMOS
Input 0
Input 1
Input N
VOUT
Pulldown network, connects output
to GND, contains only NMOS
For every set of input logic values, either pullup or pulldown
network makes connection to VDD or GND
– If both connected, power rails would be shorted together
– If neither connected, output would float (tristate logic)
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NAND and NOR gates illustrate the dual
natureNAND/NOR
of the pullup/pulldown
Static CMOS Logic networks
Gates
• Combinational Logic •
Sequential State
NAND Gate
A
B
NOR Gate
A
B
(A.B)
(A+B)
A
(A.B)
B
B
(A+B)
A
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• Combinational Logic •
Sequential State
Approach for Designing More Complex Gates
I Goal is to create a logic function f (x1 , x2 , ...)
. We can only implement inverting logic with one CMOS stage
I Implement pulldown network
. Write PD = f (x1 , x2 , ...)
. Use parallel NMOS for OR of inputs
. Use series NMOS for AND of inputs
I Implement pullup network
. Write PU = f (x1 , x2 , ...) = g (x1 , x2 , ...)
. Use parallel PMOS for OR of inverted inputs
. Use series PMOS for AND of inverted inputs
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Designers can use a methodical
approach to
build
more
complex
gates
Complex Logic Gate Example
• Combinational Logic •
Sequential State
A
B
(A+B).C
C
f
(A
B) C
PD
(A
B) C
PU
(A
B) C
(A
B)
( A B)
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C
C
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• Combinational Logic •
Sequential State
Single- vs. Multi-Stage Static CMOS Logic
Adapted from [Weste’11]
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• Combinational Logic •
Sequential State
Multiple Stages of Static CMOS Logic
Each design has different delay,
area, and energy trade-offs
Adapted from [Weste’11]
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• Combinational Logic •
Sequential State
CMOS Pass-Transistor Logic Style
Adapted from [Weste’11]
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• Combinational Logic •
Sequential State
CMOS Transmission Gate Multiplexer
Adapted from [Weste’11]
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• Combinational Logic •
Sequential State
CMOS Tri-State Buffers
Vdd
En
Y
A
En
Gnd
Adapted from [Weste’11]
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• Combinational Logic •
Sequential State
Various Multiplexer Implementations
Each design has different delay,
area, and energy trade-offs
Simple first-order analysis can help
suggest some of these trade-offs
Adapted from [Weste’11]
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• Combinational Logic •
Sequential State
Larger Tri-State Multiplexers
Adapted from [Weste’11]
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• Sequential State •
Combinational Logic
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• Sequential State •
Combinational Logic
Level-High Latch
Adapted from [Weste’11]
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• Sequential State •
Combinational Logic
Positive-Edge Triggered Flip-Flop
Adapted from [Weste’11]
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• Sequential State •
Combinational Logic
Positive-Edge Triggered Flip-Flop
Adapted from [Weste’11]
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Combinational Logic
Sequential State
Take-Away Points
I We have reviewed basic CMOS circuit implementations
. Combinational Logic: static CMOS, pass-transistor, tri-state buffers
. Sequential State: latches, flip-flops
I In the next two sections, we will explore various methodologies which
enable mapping designs written in a hardware-description language
down into these circuits
I In the next part of the course, we will explore the details of how to
quantitatively evaluate the cycle time, area, and energy of these
circuits
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Combinational Logic
Sequential State
Acknowledgments
I [Weste’11] N. Weste and D. Harris, “CMOS VLSI Design: A Circuits
and Systems Perspective,” 4th ed, Addison Wesley, 2011.
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