Aalborg University
Institute of Energy Technology
Power Electronics and Drives
Active Neutral Point Clamped Converter
PED9 – 1019b
ANPC 2008
Active Neutral Point Clamped Converter
Project period: 1st March – 11th June
Project group: PED9 – 1019b
Author: Ionut Trintis
Supervisors: Remus Teodorescu
Stig Munk-Nielsen
Number of copies: 4
Number of pages: 72
Abstract
The aim of the project is to design, build and test the Active Neutral Point Converter with
different control strategies. The introductory part of the project describe the basically
principle of three level converters and the known three-level topologies are presented. Further,
four Sinusoidal Pulse Width Modulation strategies are presented and their switching states are
analyzed. For proving the operation of these strategies, the models in Power Simulation
software are shown with results. The hardware implementation with all the components is
showed and software implementation using a Digital Signal Processor is described; three
control strategies were successfully implemented. In the last part the laboratory setup is
described and the experimental results are presented and discussed.
Preface
This report is a documentation of the project “Active Neutral Point Converter”.
This report was prepared by the group PED9-1019b at Aalborg University, Institute of Energy
Technology in Power Electronics and Drives field.
The report consists in seven chapters and three appendixes. The aim of the project was to
build and test the converter with different control strategies. The control was implemented
using Texas Instruments TMS320F28335 DSP platform.
The references of the literature are shown in brackets e.g. [1]. The reference list is presented at
the end of the chapters. Figures are numbered starting with chapter number like this:
Chapter.Subchapter.Number.; and the tables Chapter.Number.
The last appendix shows the contents of the attached CD.
Aalborg 11th June
Acknowledgments
Firstly I would like to thanks to Professor Dan Floricau, my supervisor from Romania, for
given me the opportunity to study in Aalborg University with such an interesting project
theme. Special thanks go to Professor Stig Munk-Nielsen for patience in supervising and for
his very useful advices, to Professor Remus Teodorescu for his help before and during the
project and for his short answers directly to the object. Thanks Robert Weissbach for your
very useful DSP laboratories, and for advices. Thanks Uffe Jakobsen for your very interesting
discussions. Thanks to all my colleagues from room 107/39: Mario Vetuschi, Veronica
Panaite, Andreea Zahiu and special thanks to Alin Raducu for his very useful administrative
advices. Last but not least thanks to Walter Neumayr for his help in laboratory.
Ionut Trintis
______________________
Abbreviations
3L – Three Level
PWM – Pulse Width Modulation
NPC – Neutral Point Clamped
ANPC – Active Neutral Point Clamped
VSC – Voltage Source Converter
FC – Flying Capacitor
SC – Stacked Cells
PSIM – Power Simulation Software
IGBT – Insulated Gate Bipolar Transistor
DC – Direct Current
PCB – Printed Circuit Board
LED – Light Emitting Diode
RMS – Root Mean Square
AVG – Average
DSP – Digital Signal Processor
CPU – Central Processing Unit
ePWM – Enhanced Pulse Width Modulation
HRPWM – High Resolution Pulse Width Modulation
I/O – Input/Output
GPIO – General Purpose Input/Output
FPGA – Field-Programmable Gate Array
CLK – Clock
TBPRD – Time Base Period Register
TBPHS – Time Base Phase Register
TBCTL – Time Base Control Register
Contents
Chapter 1. Introduction .......................................................................................................- 3 1.1. Background .................................................................................................................- 3 1.2. Three-level converters history.....................................................................................- 3 1.3. Three-level concept .....................................................................................................- 3 1.4. Aim of the project........................................................................................................- 5 1.5. Contents of report........................................................................................................- 5 1.6. Summary .....................................................................................................................- 6 Chapter 2. Comparison between known 3L converters ...................................................- 7 2.1. Three-level structures ..................................................................................................- 7 2.1.1. Stacked Cells........................................................................................................- 7 2.1.2. Neutral Point Clamped.........................................................................................- 9 2.1.3. Flying Capacitor.................................................................................................- 12 2.1.4. Active Neutral Point Clamped ...........................................................................- 13 2.2. Advantages and disadvantages of three-level inverters ..........................................- 16 2.3. Summary ...................................................................................................................- 17 Chapter 3. Control strategies ............................................................................................- 19 3.1. PWM 1 ......................................................................................................................- 19 3.2. PWM 2 ......................................................................................................................- 21 3.3. PWM 3 ......................................................................................................................- 22 3.4. PWM 4 ......................................................................................................................- 24 3.5. Summary ...................................................................................................................- 25 Chapter 4. Simulations.......................................................................................................- 27 4.1. Modeling PWM 1......................................................................................................- 27 4.2. Modeling PWM 2......................................................................................................- 30 4.2.1. Using two carriers ...............................................................................................- 30 4.2.2. Using one carrier.................................................................................................- 32 4.2.3. Simulation results................................................................................................- 33 4.3. Modeling PWM 3......................................................................................................- 34 4.4. PWM 4 ......................................................................................................................- 35 4.5. Summary ...................................................................................................................- 35 Chapter 5. Implementation ...............................................................................................- 37 -
ANPC 2008 5.1. Hardware implementation .........................................................................................- 37 5.1.1. Gate drive optocouplers .....................................................................................- 37 5.1.2. Dead time generator ...........................................................................................- 38 5.1.3. Heat sink ............................................................................................................- 40 5.1.4. Fiber optic bus....................................................................................................- 43 5.2. Software implementation ..........................................................................................- 44 5.2.1. General setups one DSP program ......................................................................- 44 5.2.2. Settings for PWM modules ................................................................................- 46 5.2.3. Sinusoidal PWM implementation ......................................................................- 47 5.2.4. Practical implementation of PWM.....................................................................- 49 5.3. Summary ...................................................................................................................- 50 Chapter 6. Laboratory .......................................................................................................- 51 6.1. Implementation for PWM 2 ......................................................................................- 51 6.1.1. DSP output signals .............................................................................................- 51 6.1.2. Test waveforms for PWM 2...............................................................................- 53 6.2. Implementation for PWM 3 ......................................................................................- 55 6.2.1. DSP output signals .............................................................................................- 55 6.2.2. Test waveforms for PWM 3...............................................................................- 56 6.3. Implementation for PWM 4 ......................................................................................- 58 6.3.1. DSP output signals .............................................................................................- 58 6.3.2. Test waveforms for PWM 4...............................................................................- 59 6.4. Summary ...................................................................................................................- 61 Chapter 7. Conclusion........................................................................................................- 63 7.1. Comparison between simulations and test results.....................................................- 63 7.1.1. PWM 2 ...............................................................................................................- 63 7.1.2. PWM 3 ...............................................................................................................- 64 7.1.3. PWM 4 ...............................................................................................................- 65 7.2. Summary ...................................................................................................................- 65 7.3. Future Work ..............................................................................................................- 66 References ...........................................................................................................................- 67 A. ANPC Design .................................................................................................................- 69 B. Fiber Optic interface Design.........................................................................................- 71 C. CD ...................................................................................................................................- 72 ‐ 2 ‐
ANPC 2008 Chapter 1. Introduction
In this chapter will be presented the basic principle of three-level commutation
1.1. Background
The classical two-level converter will be replaced with the three-level converter which is
better in high-power applications and it starts to be important in low-power applications too.
In applications with drives, the harmonics causes additional losses and pulsating torques in
motors. Using a three level converter for drive systems will provide a bigger efficiency
compared with a classical two level converter. The three-level Neutral Point Clamped Voltage
Source Converter (NPC VSC) it’s on the market used in applications like marine, traction,
mills, fans, pumps. For a better distribution of the power dissipated among the
semiconductors, and for a big output power the Active Neutral Point Clamped topology is
used.
1.2. Three-level converters history
The first topology developed in 1975, which is the start point in multilevel converter
topologies and it was the connection between single-phase inverters in order to generate more
steps in voltage [1]. After this concept, three-level Stacked Cells VSC was developed.
Experimental results have been shown very late, after 18 years [2].
Neutral Point Clamped VSC is the next topology developed. This converter is used in industry
in our days and is the most popular three-level converter. This topology is considerate to be
one particular implementation of Stacked Cells structure [2].
Flying Capacitor topology was the next developed structure. This structure is useful on higher
frequency because the size of his capacitors grows while the operating frequency is
diminuated. On lower frequency this converter is replaced with NPC topology.
Active Neutral Point Clamped VSC is one particular topology of NPC converter and it gives a
better distribution of power losses in the switches [3].
1.3. Three-level concept
The output terminal has three voltage levels. If the main direct voltage supply is VDC , the
output voltage levels are VDC/2, 0, -VDC/2, if the main tension is perfectly split by two ideal
‐ 3 ‐
ANPC 2008 capacitors in VDC/2. Generalized, if we have two voltage sources as shown in Fig. 1.1., the
output voltage levels will be V1, 0, V2.
Fig. 1.1. The principle of three-level commutation
In the multilevel power conversion theory is defined the value of the voltage sources V1 and
V2 that must be equal with [8]:
Vm =
VDC
,
m −1
m – number of inverter levels.
Also, an inverter with m levels needs (m-1) voltage sources or capacitors [8].
Output voltage and current is shown in Fig. 1.2. for an ideal sinusoidal current source as load.
With blue is wave for voltage and with red the load current. The commutation frequency is
fc=1000 Hz. Here we can see the order of voltage levels in one period of 20 ms equivalent of
50 Hz frequency, the voltage levels are 100V, 0V, -100V ; that order depends only of
command strategy adopted.
‐ 4 ‐
ANPC 2008 Fig. 1.2. Output voltage and current for three-level converter, fc=1 kHz
In comparison with two-level converters the voltage stress of semiconductors is lower. Every
switch must hold just half of total input voltage, the losses in commutation and conduction are
reduced, and the output power can be bigger and with lower output current ripples. Here we
have some good reasons to replace the old two-level converters with three-level converters.
The three-level conversion is not something new in power electronics, but until some couple
of years three-level converters haven’t been used. In the last period of time is an interest to
develop three-level converters with better performance in order to build a reliable converter
for high power applications. Now the researchers are trying to find the best solution for threelevel commutation, which has the bigger quality-price ratio. Active Neutral Point Clamped
VSC seems to be a good solution to three-level commutation and the interests for develop
new strategy commands which has more advantages are rising.
1.4. Aim of the project
Aim of the project is to design, build the Active Neutral Point Clamped Voltage Source
Converter (ANPC VSC) and test different command strategies on this topology.
1.5. Contents of report
Chapter 1 – Introduction – Contains the background of the project and the basic operating
principle of three-level converters.
‐ 5 ‐
ANPC 2008 Chapter 2 – Comparison between known 3L converters – The most known 3L topologies are
presented and described.
Chapter 3 – Control strategies – Four PWM strategies for ANPC will be presented.
Chapter 4 – Simulations – Simulations results of the PWM strategies implemented will be
presented.
Chapter 5 – Implementation – Hardware and software implementation of ANPC converter
will be explained
Chapter 6 – Laboratory – The laboratory setup and results will be shown.
Chapter 7 – Conclusion – Comparison between simulation and test results will be shown,
report summary and future work.
1.6. Summary
A background of the project was given. The basic principle of commutation in three-level
converters was described and aim of the project was defined. The aim of the project was
established and the contents of the report were mentioned.
‐ 6 ‐
ANPC 2008 Chapter 2. Comparison between known 3L
converters
In this chapter are presented the known three-level topologies. A comparison between them
will be made too.
2.1. Three-level structures
The number of levels of an inverter is the number of steps in the voltage of the output
terminals with respect to any arbitrary internal reference point [4].
Four most known topologies will be presented: Stacked Cells, Neutral Point Clamped, Flying
Capacitor and Active Neutral Point Clamped. A brief description of each topology is given
below.
2.1.1. Stacked Cells
The 3L-Stacked Cells (3L-SC) structure has three arms, every arm contains two serial
connected switches with inverse diodes in parallel. The upper and lower side of the converter
has two switches normally connected and the middle side has two switches in opposites
connected. Each switch must be designed to support a voltage equal with half of main supply
voltage (VDC/2). Those two voltage supplies, which can be two capacitors connected to one
main source or can be two different voltage supplies like in Fig. 2.1.1., are serial connected
and between them is defined the neutral point of the converter which is connected to the
ground.
‐ 7 ‐
ANPC 2008 Fig. 2.1.1. Stacked Cells topology
The switches can be partitioned virtual in three commutation cells: (S1-S1c), (S2-S2c) and (S3S3c). Switches S1, S1c, S3, and S3c works at high frequency while S2 and S2c at a lower
frequency [2].
(a)
(b)
‐ 8 ‐
ANPC 2008 (c)
Fig. 2.1.2. Stacked Cells conduction states: (a) positive load voltage; (b) zero load voltage;
(c) negative load voltage;
Advantage: the energy conversion is made at every moment on a single stage [2].
The biggest drawback of this topology consists in the modality of energy conversion which is
based on two partial uncoupled stages. The middle side is very stressed because it must
support the voltage on positive load and negative load too, and future more the bidirectional
path on zero load voltage. Thence, the losses in switches S1c and S3c are very significant and
this thing goes to degradation in time of those two switches. Future more, the operation at
“zero” speed is very bad [2].
2.1.2. Neutral Point Clamped
In this structure in comparison with Stacked Cells structure we have just two commutation
cells (S1-S1C) and (S2-S2C) and two clamped diodes Du and Dd (see Fig.2.1.3.). The clamping
point is between those two diodes, point which is connected to ground. The clamping diodes
equalize the voltage stress across transistors.
‐ 9 ‐
ANPC 2008 S1
V1
Du
S2
Iload
O
A
Dd
S2c
VDC
V2
S1c
Fig. 2.1.3. Neutral Point Clamped topology
(a)
(b)
‐ 10 ‐
ANPC 2008 (c)
Fig. 2.1.4. NPC conduction states: (a) positive load voltage; (b) zero load voltage; (c)
negative load voltage
On positive load voltage and positive current in conduction will be S1, S2 and if the current is
negative the anti-parallel diodes of S1 and S2 will be in conduction. On zero voltage and
positive current Du, S2 will drive the flow and if the current is negative Dd, S1C. On negative
voltage, for a positive current anti-parallel diodes of S2C and S1C will be in conduction,
respectively for a negative current S1C and S1C transistors will be on [10].
In comparison with Active NPC, topology described later, NPC topology has the constraint of
the clamped diodes on zero voltage state and both of the switches S2 and S1C must be on in
order to provide bidirectional current path. In ANPC by adding another two transistors, more
freedom in choosing the path for zero voltage state is provided and more switching states will
be available [6].
Like an advantage of this topology, the cost for implementing is cheaper in comparison with
other topologies because it consists of four transistors and six diodes, and the performances
are satisfactory. Because of this economical reason this topology is very used in high power
applications in industry
The drawback of this converter is the unequal loss distribution among the semiconductors.
‐ 11 ‐
ANPC 2008 2.1.3. Flying Capacitor
In schematic from below it can be sow Flying Capacitor (FC) topology that consists in four
switches (two commutation cells) and one capacitor (flying capacitor) between S1 and S1C.
This topology is also called the multicell converter, because it can be partitioned in two
commutation cells (S1-S1C) and (S2-S2C), every cell with one capacitor [4]. The main idea of
this topology is to use the flying capacitor which is charged with VDC/2 [7].
S1
V1
S2
Iload
O
A
S1c
VDC
V2
S2c
Fig. 2.1.5. Flying Capacitor topology
(a)
(b)
‐ 12 ‐
ANPC 2008 (c)
(d)
Fig. 2.1.6. FC conduction states: (a) positive load voltage; (b) zero down load voltage;
(c) zero up load voltage; (d) negative load voltage;
On positive and negative states everything is normal, like it can be seeing in Fig. 2.1.6. (a),
(d), a bidirectional current path is provided like the other converters from above. The
particular thing on this topology is the zero state; two different paths provide the zero
voltage to the output (Fig.2.1.6. (b); (c) ). On “zero down load voltage”, Fig. 2.1.6.(b), if
the current is positive the flying capacitor is charging and if the current is negative the
flying capacitor is discharging. On “zero up load voltage”, Fig. 2.1.6.(c), if the load current
is positive the flying capacitor is discharging and respectively if the current is negative this
capacitor is charging. Because of this phenomenon, “inverter output redundancy”, the
command strategy must take in account the voltage balancing in this flying capacitor. The
flying capacitor voltage must be maintained at VDC/2 [4].
Advantage: the active and reactive power flow can be controlled.
Disadvantage: the switching frequency must be very high and this leads to high switching
losses [8].
2.1.4. Active Neutral Point Clamped
In additionally, if the NPC schematic is observed, this topology has two more transistors then
NPC topology and in stead of two clamped diodes will be two transistors with anti-parallel
diodes, see Fig. 2.1.7. Those two transistors in plus can provide more freedom in command
‐ 13 ‐
ANPC 2008 and they can also take some losses from the regular transistors that where used to achieve the
desired conduction states. Now the topology can be splinted in three commutation cells in
different manner then in NPC topology, (S1-S1c), (S2-S2c) and (S3-S3c), in cells 1 and 3 the
switches must be always in complementary to avoid short circuit [11].
S1
V1 S1c
S2
Iload
O
S3
S3c
VDC
A
V2
S2c
Fig. 2.1.7. Active NPC topology
In Fig. 2.1.8. are presented the conduction states of ANPC converter. Like FC topology
ANPC has four conduction states: positive, zero up, zero down, negative.
ANPC can obtain the conduction states without any capacitor and this is a big advantage of
this converter in comparison with FC converter because when lower frequencies are used the
capacitor of FC topology must have big dimensions, and usually the capacitors in schematic
can be very expensive [2].
Starting from the conduction states of the ANPC topology, switching states can be defined. In
order to obtain more command strategies, more then basic switching states will be defined.
When positive conduction state is achieved by turning on S1 and S2, the switch S3 can be on or
off. In the same manner on negative state, S2C and S3C must be on, and S1C can be on or off.
‐ 14 ‐
ANPC 2008 For the zero load voltage from two conduction states on the same idea, four switching states
can be defined [6].
Table 2.1. shows the switching states for ANPC converter based on idea from above.
(a) (b) (c) (d) Fig. 2.1.8. ANPC conduction states: (a) positive load voltage; (b) zero load voltage – up;
(c) zero load voltage – down; (d) negative load voltage;
Having those two possibilities for zero load voltage the distribution of conduction losses can
be controlled by alternation between upper side and lower side. For the positive and negative
load voltages the losses cannot be distributed in other way [11].
‐ 15 ‐
ANPC 2008 Table 2.1. Switching states of 3L-ANPC
Switching
S1
S1c
S2
S2c
S3
S3c
Positive 1
1
0
1
0
0
0
Positive 2
1
0
1
0
1
0
Zero Up 1
0
1
1
0
0
0
Zero Up 2
0
1
1
0
0
1
Zero Down 1
0
0
0
1
1
0
Zero Down 2
1
0
0
1
1
0
Negative 1
0
0
0
1
0
1
Negative 2
0
1
0
1
0
1
state
Switch
The advantage of using Active NPC is that the zero state can be achieved basically in two
ways, while in NPC the zero state depends on the current direction because of the limitation
of the clamped diodes [6]. Usually at NPC converter the zero state is achieved by turning on
the switches S2 and S1c, see Fig. 2.4. (b), in order to have bidirectional current path. With
ANPC we can have two independent bidirectional paths for zero voltage and this particular
thing is a very big advantage.
In the table presented above more then basics switching states have been shown, these
derivate states are used to balance the losses among the semiconductors. The basic switching
states are: Positive 1, Zero Up 1, Zero Down 1, Negative 1. The states with “2” can be used in
order to create better strategies who don’t stress the switches and better performance for this
converter can be achieved.
2.2. Advantages and disadvantages of three-level inverters
The biggest advantage is that the domain of applied voltages to the inverters entrance can be
extended because the switches are not stressed in tension like on two-level inverters. The total
voltage that is applied at entrance is allocated to a bigger number of switches and in this way
‐ 16 ‐
ANPC 2008 it is possible to increase voltage, which is a necessity in our days when the consumption of
electrical energy it’s increased day by day.
The voltage distortion is lower because we have more sinusoidal waveforms [3].
The harmonics generated in grid are lower and the filtering will not be necessary [8].
The voltage variation is reduced ( dv/dt
) and therefore the voltage stress on the load is
smaller in comparison with two level inverters [7].
The disadvantage of the three level inverters is the increased number of the switches but
because the voltage on each switch must hold is smaller, the differences between prices of
transistors for a three level converter in comparison with a two level one is not so big [7].
Another drawback is the hardware schematic that is more complicated, more gate drivers are
required and the control is much more complicated. Also two DC buses are required in stead
of one but both of them with a half voltage.
Another problem of the three level converters can be the larger leakage inductance compared
with a two level inverter. In three level converters are serial connected switches and the
connection between every switch has a small leakage inductance, all the inductances summed
gives a value that can slow down the time for turning on and off the transistors which is an
disadvantage an on every topology this thing must be taken in account.
2.3. Summary
Stacked Cells, Neutral Point Clamped, Flying Capacitor and Active Neutral Point Clamped
topologies has been described. Conduction states, functionality, advantages, disadvantages
and comparison between those topologies was shown. Additionally, the advantages and
disadvantages of three level converters in general have been enumerated.
‐ 17 ‐
‐ 18 ‐
ANPC 2008 ANPC 2008 Chapter 3. Control strategies
In this chapter will be presented the Sinusoidal PWM control strategies which can be used for
ANPC converter [12]. Four strategies will be shown further.
3.1. PWM 1
This control strategy is used for Neutral Point Converter and can be used for ANPC too [12].
The equivalence between NPC and ANPC can be achieved.
S1
V1
Du
S2
Iload
O
A
Dd
S2c
VDC
S1c
V2
a)
b)
Fig. 3.1.1. a) NPC converter ; b) ANPC converter
With notation from Fig.3.1.1., equivalence between switches is achieved in Table 3.1. This is
necessary in order to distinguish the switches from ANPC that are present to NPC too, the
active switches will provide the clamping diodes if they will have no signal on the gate.
Table 3.1. ANPC to NPC switches equivalence
ANPC
NPC
S1
→
S1
S2
→
S2
S2C
→
S1C
S3C
→
S2C
‐ 19 ‐
ANPC 2008 In Fig. 3.1.2. is shown the waveforms like sinusoidal reference wave Sr, carrier waves C1, C2,
the switching states of the switches S1, S1C, S2, S2C of NPC converter and the waveform for
output voltage VAO. The carrier C2 is with offset and with 180 electrical degrees phase delay.
This is the basic principle of NPC converter conduction states which can be applied for ANPC
converter too.
Fig. 3.1.2. PWM 1 (NPC) strategy waveforms
Two carrier waves are used, one (C1) in order to obtain the switching between positive state
VDC/2 and zero state and the other one (C2) to obtain the switching between zero state and
negative state -VDC/2.
‐ 20 ‐
ANPC 2008 It can be observed in this diagram the main disadvantage of the NPC converter. The switches
S1C and S2 are more stressed in comparison with S1 and S2C [3]. For example S1C , when
reference wave is positive must switch at a higher frequency so in this time the switching
losses will be presented, and when the reference wave is negative in this switch will be
presented conduction losses and in comparison with S1 the losses are higher.
3.2. PWM 2
This PWM strategy is fixing the problem described before by using the switches that are in
plus from NPC and transform the converter in Active NPC [12].
The switches S1 and S1C , as it can be seen in Fig. 3.2.1., are switching a half of an entire cycle
in order to obtain positive VDC/2 voltage and zero voltage and the other half of the cycle them
will be turned off while there will be no more losses. In the same manner the switches S3 and
S3C will be off on the first half and on to the other half of cycle. The particular state will be to
switches S2 and S2C who will be on all the time on a half of an entire cycle and the other half
off, any time in opposite.
‐ 21 ‐
ANPC 2008 Fig. 3.2.1. PWM 2 (ANPC) strategy waveforms
3.3. PWM 3
On the same principle this command strategy has been developed in [12], with the same
carriers as it shown in Fig. 3.3.1. In this particular strategy the switches S1, S1C, S3, S3C, have
just a few switching losses because they are switching at a lower frequency and conduction
losses all the time, more exactly the switching frequency is equal with the reference wave
frequency because in one period they must switch one time on and one time off. S2 and S2C
‐ 22 ‐
ANPC 2008 define practically the output voltage states, the switching frequency is equal with carrier
frequency, and the switching losses are maxim in these switches.
Fig. 3.3.1. PWM 3 (ANPC) strategy waveforms
As it can be observed in PWM 1 and 2 strategies, in every moment two transistors are always
on, see Fig. 3.1.2 or Fig.3.2.1. Future more in this strategy in all the time three switches are
always on and this thing leads to a loss balancing in inverter. For example if S1 and S2 are on
in order to obtain the positive state, the switch to the zero state can be classical obtained by
turning S1 off and turning on S1C. If S3 is on, the zero state can be also obtained by turning off
‐ 23 ‐
ANPC 2008 S2 and turning on S2C. When S3 is on the disadvantage is that the switch S3C must hold a
VDC/2 voltage, in stead of VDC/4 because the voltage before were shared between this two
switches S3 and S3C , and it will be more stressed in voltage but the conduction losses are
taken by S3 and S2C for zero voltage state. So in this way the losses in conduction for zero
state when the reference is positive are moved in the switches from the zero down arm (S3C
and S2C) and respectively when the reference is negative the losses are in the upper arm (S1C
and S2). In this way the loss balancing in converter can be achieved.
3.4. PWM 4
Using command strategies presented above (PWM 1, 2, 3) the apparent output voltage
frequency will be equal with the highest commutation frequency of the transistors used in
ANPC topology.
One more strategy can be used for this converter. Using this strategy the apparent frequency
on the output will be double of the transistors switching frequency [12].
The table below shows the switching states and the output voltage.
Table 3.2. Commutation sequences for PWM4
Positive Reference
Negative Reference
S1
0
1
1
1
0
0
0
0
0
0
S1c
1
0
0
0
1
0
1
1
1
0
S2
1
1
0
1
1
0
0
1
0
0
S2c
0
0
1
0
0
1
1
0
1
1
S3
0
1
1
1
0
1
0
0
0
1
S3c
0
0
0
0
0
0
1
1
1
0
VAO
0
VDC/2
0
VDC/2
0
0
-VDC/2
0
-VDC/2
0
‐ 24 ‐
ANPC 2008 Achieving the output doubling frequency is based by using all the possibilities provided from
the freedom of this topology with Active switches.
When the reference is positive for achieving VDC/2 voltage “Positive 2” state was used (see
Table 2.1. from Chapter 2), but for achieving the zero state two switching states are used
alternative “Zero Up 1” and “Zero Down 2”. So, the alternant between VDC/2 and 0, will use
“Zero Up 1”, “Positive 2”, “Zero Down 2”, “Positive 2”, “Zero Up 1”…. etc.
When the reference is negative for achieving - VDC/2 voltage “Negative 2” state was used and
for zero state like before the alternate between “Zero Down 1” and “Zero Up 2”.
So, using this strategy it is possible to reduce the switching losses in one transistor at a half of
normal value that is achieved with the other command strategy. This particular thing makes
the converter ANPC very attractive for use even in low power applications and the harmonics
generated in grid will be lower because higher output frequencies can be achieved.
3.5. Summary
Four different PWM strategies used for ANPC converter were presented and explained. Wave
forms for a better understanding have been made. Advantages and disadvantages between
them have been discussed.
‐ 25 ‐
‐ 26 ‐
ANPC 2008 ANPC 2008 Chapter 4. Simulations
In this chapter the modeling in PSIM of ANPC converter will be presented with different
command strategies.
4.1. Modeling PWM 1
Using just four switches and two diodes the ANPC topology will be equivalent with NPC
topology (see subchapter 3.1.). In Fig. 4.1.1. is the model of the power schematic, made in
PSIM. T1, T1C, T2, T2C, T3, T3C are labels where the PWM pulses will be generated, module
IGBT switch for switches and a resistive-inductive load was used.
Fig. 4.1.1. Converter power schematic
In order to distinguish the positive and negative reference, for control, two signals will be
used “Inh” and “Inhn”, see Fig. 4.1.2.(a). Therefore, using a comparator, when reference wave
will be positive the signal Inh=1 and Inhn=0 and respectively for a negative reference Inh=0
and Inhn=1.
‐ 27 ‐
ANPC 2008 (a)
(c)
(b)
(d)
Fig. 4.1.2. (a) Inhibition signals; (b) Disable signals for T1C and T3 transistors;
(c) Comparison between reference wave and carrier C1; (d) Comparison between reference
wave and carrier C2.
In Fig. 4.1.2. (b) is the command for the active transistors who will not be used for this
strategy and the signal for them will be always 0. In order to have a simple and easy to debug
model, the comparison between reference wave and carriers, two more labels will be defined
(In Fig. 4.1.2. (c), (d) ).
As it can be observed in Fig. 3.1.2. (Chapter 3), the switch S1 will be in conduction only in the
firs half when the reference is positive, so using the comparison between first carrier and
reference wave (label uC1), and inhibition signal the PWM control is achieved for T1
(transistor from switch S1). In the same way but using the second carrier and the inhibition
signal for negative the PWM signal for T3C is generated. A 180 electrical degrees delay
between C1 and C2 is used in order to have a symmetrical output voltage.
The switches S2 and S2C have a different command, for example T2 must be always in
conduction when reference is positive and when reference is negative the comparison between
carrier C2 and reference wave will drive this transistor. In the same way but complementary
will be generated the signal for T2C .
‐ 28 ‐
ANPC 2008 Fig. 4.1.3. PWM control signals for T1, T2c, T2, T3c
For a load R=30Ω, L=170mH, DC link voltage VDC = 600V, switching frequency fC = 1 kHz,
modulation index M = 0.8, the simulated output voltage and current:
Fig. 4.1.4. Output voltage and current
‐ 29 ‐
ANPC 2008 In order to prove the comparison between control strategies, made in Chapter 3, and their
effect regarding the losses in switches, the simulation was used. Using this strategy on the
specified conditions the average values of the currents are:
I S1( AVG ) = 0.396 A
I S1C ( AVG ) = 0.7 A (the flow through the recovery diode)
I S 2 ( AVG ) = 1.1 A
I S2 C ( AVG ) = 1.07 A
I S3( AVG ) = 0.688 A (the flow through the recovery diode)
I S3C ( AVG ) = 0.38 A
The average switching frequency for all transistors using this strategy is f sw ,Sx ( AVG) =
f sw
.
2
It can be observed the unequal loss distribution; the most stressed switches are S2 and S2C ,
equivalent with S2, S1C from NPC (see Table 3.1., Chapter 3). In order to make the
comparison between PWM 1 and too, see the simulation results from PWM 2 in further
subchapter.
4.2. Modeling PWM 2
There are two possibilities to implement a PWM command strategies, with one carrier and
using one modified reference wave, or like in previous subchapter using two carriers and the
reference wave in natural way.
4.2.1. Using two carriers
In Fig. 4.2.1. are the signals for ANPC control with PWM 2 strategy. It can be observed the
operation of the transistors, T1 and T1C are on only when the reference is positive and them are
complementary (commutation cell 1), T3 and T3C in the same situation but only when the
reference is negative. The transistors T2 and T2C have a particular switching state; their
switching frequency is always equal with reference wave frequency.
‐ 30 ‐
ANPC 2008 Fig. 4.2.1. PWM 2 control signals using two carriers
The results are the same like before ( Fig.4.1.4 ). Further, a small comparison between two
implementation ways will be shown: one with phase delay between carriers and the other
without this phase delay.
(a)
‐ 31 ‐
ANPC 2008 (b)
Fig. 4.2.2. Output voltage waveforms; (a) With 180° delay; (b) Without delay
In figure above it can be observed the difference that can be made using the phase delay
between carriers.
4.2.2. Using one carrier
Implementation for this strategy can be made also using one carrier. The disadvantage of this
implementation is the same like described before, the output voltage will be unsymmetrical
and the result will be exactly like in Fig. 4.2.2. (b). Further will be shown the model.
‐ 32 ‐
ANPC 2008 Fig. 4.2.3. PWM 2 control signals using one carrier
This implementation is using a modified reference wave; the negative sine has a DC offset.
The logical operations are the same.
4.2.3. Simulation results
The average currents measured in simulation are:
I S1( AVG ) = 0.396 A
I S1C ( AVG ) = 0.235 A
I S 2 ( AVG ) = 0.63 A
I S 2 C ( AVG ) = 0.605 A
I S3( AVG ) = 0.22 A
I S3C ( AVG ) = 0.383 A
‐ 33 ‐
ANPC 2008 Now it can be observed the advantage using the ANPC for a better distribution of losses in
semiconductors. Using this strategy the average current in switches S2 and S2C is lower, from
1.1A and respectively 1.07A in PWM 1, now the values are 0.63A and 0.605A, therefore the
losses in this switches will be almost a half then before.
In this strategy the switches S1, S1C and S3, S3C works at the same frequency like the
transistors used in PWM 1 (fSW/2) but the switches S2 and S2C switch at the reference wave
frequency.
4.3. Modeling PWM 3
Implementation of PWM 3 is shown in Fig. 4.3.1. , the inhibition signals are the same like in
previous models (Fig. 4.1.2.(a) ). Transistors T1 and T1C (switching cell 1) have the same
command with T3 respectively T3C (switching cell 3), see Fig. 3.3.1. (subchapter 3.3.). The
switching states are achieved using PWM commands only for T2 and T2C. Comparison
between C1 and reference wave for positive voltage gives signals for T2 and complementary
for T2C and in the same manner when the reference is negative but using the second carrier.
The result is the same like in Fig. 4.1.4.
Fig. 4.3.1. PWM 3 control signals
‐ 34 ‐
ANPC 2008 4.4. PWM 4
Using switching states from Table 3.2. (see subchapter 3.4.), this new strategy that has been
developed in [12], for a switching frequencies to transistors of 500 Hz, the output parameters
are the same like using PWM 1, 2 or 3 for a switching frequencies equal with 1000 Hz, see
fig.4.4.1.
Fig. 4.4.1. Output voltage and current for PWM 4 strategy, fc=500Hz
It can be observed that the result is the same like in Fig. 4.1.4, presented before. These results
are achieved by using the both zero states provided by the active switches.
4.5. Summary
The simulation schematics were shown for implementing the PWM strategies, the
implementations and the results for every occurrence have been discussed. A small
comparison between them was done. In plus, the advantage of using the phase delay between
the carriers was shown.
‐ 35 ‐
‐ 36 ‐
ANPC 2008 ANPC 2008 Chapter 5. Implementation
In this chapter the hardware implementation of ANPC converter and software implementation
for control are presented
5.1. Hardware implementation
The hardware implementation of the ANPC converter is divided in two parts on the same
board. The firs part contains the power schematic of the converter with transistors, plugs for
DC link and plugs for output, and the second part contains digital integrates circuits belonging
to the control schematic. Those two parts are connected by DC/DC converters and gate drive
optocouplers, integrated circuits which achieve galvanic isolation.
Insulated Gate Bipolar Transistor (IGBT) with recovery diode in parallel from International
Rectifier was used.
Short circuit rates [16]: VCES = 1200V, VCE(on) = 3.17V, VGE = 15V, IC = 5A.
The inverter was designed with the following maximum ratings:
•
VDC = 600V
•
ILOAD(RMS) = 5A for fsw ≤ 4kHz / ILOAD(RMS) = 3.5A for fsw ∈ (4kHz ; 10kHz)
The design of this converter was made in Altium Designer 6 software, one PCB for each
phase leg, see Appendix A.
5.1.1. Gate drive optocouplers
A single channel gate drive optocoupler from Agilent Technologies was used. The gate drive
circuit has to the input between 2 and 3 pins one LED which is optically coupled to a
photodiode, see Fig. 5.1.1.
Depending of the logical state, the output voltage will be +15V for high input or -15V for a
low input. The voltage between 5 and 8 pins is provided by a DC/DC converter (XP IA0515S)
which has to the input 0V and 5V and provides to the output -15V, 0V, +15V [18]. Each gate
drive has own DC/DC converter.
‐ 37 ‐
ANPC 2008 a)
b)
Fig. 5.1.1. Gate drive optocoupler HCPL – 3150 [17]; a) Description of the integrate;
b) Description of the connection in schematic.
In order to minimize the IGBT switching losses, a resistor between the gate drive and
transistor gate must be dimensioned. The value of this resistor can be calculated as [17]:
Rg =
VCC − VEE − VOL 15 + 15 − 2
=
= 56Ω ,
I OLPEACK
0.5
VCC – positive supply voltage; VEE – negative supply voltage; VOL – low level output voltage;
IOLPEACK – low peak output current.
This gate drive that was used, can be used for IGBTs up to 1200V/50A [17].
5.1.2. Dead time generator
For generating the delay between turning off of one transistor and turn on the other transistor,
transistors that are serially connected and they make the connection between two voltage
different states, a hardware solution for the dead time was chosen.
The ANPC Converter that was designed, has six transistors with antiparallel diodes
(see Fig. 2.7.). Those transistors will be drived by three signals that will provide the
complementarily between every two transistors that must never be in conduction both of
them, for example switches S1, S1c and S3, S3c. The switches S2, S2c makes a exception of
this rule, so them can be in conduction in the same time, but for symmetry of the topology the
same logic rule was implemented. Therefore, this ANPC topology can’t be transformed in
NPC topology because there the equivalent switches that have S2, S2c notation in ANPC
topology (Fig. 2.7.) for zero voltage state in order to have bidirectional current direction the
switches S2 and S2c must be both of them turned on.
‐ 38 ‐
ANPC 2008 Fig. 5.1.2. Dead time generator IXDP631 [19]
It can be seen in Fig. 5.1.2., the input signals are R, S and T; the R signal was used to
command switches S1, S1c, the S signal for switches S2, S2c and respectively T signal for S3,
S3c. These two three signals will be spitted in six signals, as an example for a logical high
state (5V) on R pin the switch S1 will be turned on and for a low state (0V) S1c will be turned
on [19]. For those three input signals (R, S, T) are provided also the enable signals for each of
them and therefore those signals (ENAR, ENAS, ENAT) was used for turning off both of the
complementary switches in order to obtain more complicated and in the same time more
efficient command strategies.
One important input for this integrated circuit is the RESET signal. One logical schematic was
developed in order to reset the output signals (all outputs will be turned off) in some
conditions but seems that for implementation and development of different PWM strategies
this reset signal can’t be defined, therefore a button which can switch between low and high
logical state was implemented. The need of this reset button is in order to start from a good
defined point, all transistors are off.
The dead time is generated between the complementary output signals (RU, RL), and an
external crystal oscillator is required. The frequency of the crystal oscillator gives the length
of the dead time, therefore this frequency must be chosen. The dead time must be chosen
bigger the most big time that is required in order to switch on the transistor in safety
conditions, therefore the harder conditions for the transistor must be considered [8].
‐ 39 ‐
ANPC 2008 Typical times for IGBT transistor IRG4PH20KD at IC = 5A, VCC = 800V, TJ = 150 °C are:
td(off) = 110 ns (turn off delay time),
tf = 620 ns (fall time).
For safety, a dead time length must be chosen at least 1μs. Therefore the frequency of crystal
oscillator must be calculated. The dead time length in IXDP631 is 8 clock periods, then the
maximum clock frequency will be:
f CLK (max) =
8
8
=
= 8 ⋅ 10 6 Hz = 8 MHz
−6
deadtime(min) 1 ⋅ 10 s
For safety a 1.6μs was established on the board with one clock that oscillates at 5MHz. In
figure below is the real dead time generation for two complementary gate drive signals.
Fig. 5.1.2. Dead time generation
5.1.3. Heat sink
In order to choose the heat sink for this converter, power losses in semiconductors must be
calculated. Simulation of the operation is the base of the calculation. PWM 2 was used.
Operating conditions: VDC = 600V, M = 0.8, fC = 5 kHz; load: R = 30Ω; L= 170 mH
a) Conduction losses
Conduction losses in switches (transistors and diodes) can be calculated with the following
formula [15]:
‐ 40 ‐
ANPC 2008 PCON ( AV ) = U CE ( 0 ) ⋅ I C ( AVG ) + rf ⋅ I C ( RMS )
where: UCE(0) – forward collector to emitter voltage drop with zero current [V];
rf – forward resistance [Ω];
IC(AVG) – collector current, average value [A];
IC(RMS) – collector current, root means square value [A];
UCE(0) and rf values are from datasheet [16], UCE(0) is from IC = f(VCE) diagram and rf is the
inversion of the forward transconductance (gfe [S]):
U CE ( 0 ) ≈ 1.5 V
rf =
1
1
=
= 0.286 Ω
g fe 3.5
The AVG and RMS currents are from simulation.
From Fig. 3.3.1. it can be observed that the losses in S1=S3C, S1C=S3, S2=S2C.
PCON ( AV ),S1 / S3C = 1.5 ⋅ 0.39 + 0.286 ⋅ 1.277 = 1.051 W
PCON ( AV ),S1C / S3 = 1.5 ⋅ 0.232 + 0.286 ⋅ 1.494 = 0.986 W
PCON ( AV ),S 2 / S 2 C = 1.5 ⋅ 0.622 + 0.286 ⋅ 1.97 = 2.043 W
PCON ( AV ),TOTAL = 2 ⋅ ( PCON ( AV ),S1 / S3C + PCON ( AV ),S1C / S3 + PCON ( AV ),S 2 / S2 C ) = 8.16 W.
b) Switching losses
The switching losses can be calculated with [15]:
Psw
1
= ⋅ fC ⋅
T
TSW
∫ e ⋅ dt
0
where: T – period of the reference wave;
fc – switching frequency [Hz];
TSW – switching period;
e – total switching energy.
The total switching energy is chosen from Fig. 5.1.3. The conditions for this diagram are the
harder conditions that one transistor can support: TJ = 150°C, VDC = 800V, VGE = 15V,
RG=50Ω. The collector current is from simulation.
‐ 41 ‐
ANPC 2008 Fig. 5.1.3. Total switching losses depending of the collector current π
Psw ,S1 / S3C
1
=
⋅ 5 ⋅ 10 3 ⋅ ∫ 1.05 ⋅ 10 −3 ⋅ dt = 2.625 W
2π
0
π
Psw ,S1C / S3 =
1
⋅ 5 ⋅ 10 3 ⋅ ∫ 0.98 ⋅ 10 −3 ⋅ dt = 2.45 W
2π
0
π
Psw ,S2 / S2C
1
=
⋅ 50 ⋅ ∫ 1.2 ⋅ 10 −3 ⋅ dt = 0.3 W
2π
0
PSW ,TOTAL = 2 ⋅ ( Psw ,S1 / S3C + Psw ,S1C / S3 + Psw ,S 2 / S 2 C ) = 10.75 W
c) Total power losses
PTOTAL = PCON + PSW = 8.16 + 10.75 = 18.91 W
The maximum thermal resistance of heat sink must be:
R thsa ,max =
Tj − Ta
P
− (R thjc + R thcs )
where: Tj – maximum junction temperature;
Ta – ambient temperature;
Rthjc – junction to case thermal resistance;
Rthcs – case to sink thermal resistance;
P – total power losses.
R thsa ,max =
°C
125 − 50
− (2.1 + 0.24 ) = 1.607
19
W
‐ 42 ‐
For safety a heat sink with thermal resistance below 1
ANPC 2008 °C
was chosen. Also higher switching
W
frequencies can be tested with a bigger heat sink (10 kHz).
5.1.4. Fiber optic bus
Interconnections between DSP platform, that generates the PWM control signals and inverter
PCB is achieved with fiber optic wires. Six fiber optic wires, for one phase leg, are available
for control, see Fig. 5.1.3, three PWM signals and another three signals for enable or disable
the command for every two transistors S1/S1C, S2/S2C, S3/S3C used in order to implement PWM
strategies which requires turning off both of the complementary transistors.
One point that must be taken in consideration must be the signal inversion of the fiber optic.
The receivers make the signal inversion, if they have no signal on the fiber optic gives on the
output a high signal. Therefore the PWM command from DSP was inversed. This inversion
could be made software, like in this implementation was done, or hardware using
supplementary components after the receivers output in order to correct the inversion.
Fig. 5.1.3. Fiber optic bus for one phase leg
For implementation of PWM strategies, one DSP platform from Texas Instruments was used
(TMS320F28335).
‐ 43 ‐
ANPC 2008 The interface between DSP and fiber optic wires was a custom solution in order to be possible
a three phase implementation of different PWM command strategies. One board with 16 fiber
optic transmitters was designed in order to connect all 12 PWM outputs of the DSP board and
another 4 CAPTURE outputs that can be used like asynchronous PWM outputs (using counter
only in up-count mode), or can be used like GPIO outputs, see Appendix B. This board was
powered from the DSP platform with 3.3V voltage. The voltage was achieved by setup the
jumper JR4 from P8, see TMS320F28335 technical reference.
5.2. Software implementation
For generating the PWM control signals the DSP platform TMS320F28335 from Texas
instruments was used. Features of the board are: 150 MHz CPU frequency, 32 bits CPU data
bus, floating point unit, harvard architecture bus, 12 ePWM outputs (6 modules with 2 PWM
outputs), three timers, 16 ADC inputs with 12 bits resolution, connection through USB.
The package which includes the DSP board (eZdSP SYSTEM KIT) is provided by Spectrum
Digital and in this package one CD with software, drivers and also examples are provided.
These examples are very useful to learn and understand how the system works and they can
be very useful to create custom code by modifying a similar example in order to obtain the
expected result. For this implementation the example “epwm_updown_aq” was used in order
to obtain symmetrical PWM outputs for control.
Implementation for PWM strategies was developed in Code Composer Studio v3.3, software
provided by Texas Instruments. The code was totally build in C++, the conversion in
assembly is being made by Code Composer Studio (CCS).
5.2.1. General setups one DSP program
Using DSP platforms, a lot of registers bits must be defined. For build a custom code from
zero bits defined will take too much time, therefore an example is very good to use because a
lot of work is already done.
‐ 44 ‐
ANPC 2008 Before setting up the PWM module, a lot of setting related to systems controls interrupts,
multiplexing of I/O pins. Therefore for a better understanding of the DSP setup a very quick
description of the program will be shown further.
The structure of a program is usually composed from a few parts which are located:
•
before main program
•
main program
•
after the main program
In the code before main program are included the header files that are used for the code,
global variables and some parameters can be defined. Header files consist in bit definition of
the registers or special function that can be used in program.
In main program is made the setup of the registers. Firstly the system control registers are
defined, controls like: watch dog timer, phase-locked loop, peripheral clocks. After that, the
GPIO pins multiplexers must be defined for the needs of the program (input/output/pwm/cap).
The most important thing after that will be the setup of interrupts; firstly all the interrupts
control registers and then the interrupt vector table. Then the pointers to the interrupt
subroutines will be defined.
Next step is to define the device peripherals that will be used (example: PWM modules). After
all this initializations, the user specific code will be done (example: enable the interrupts and
real time events). If the interrupts will be used for the code then the main program will be
finished with an idle loop where the program will stay there forever until the processor is
halted. For every cycle in loop the interrupts that have been established will make the pointer
to the interrupt subroutine where some logical code can be implemented to obtain the desired
result. This ends the main program.
In the part after main program the interrupt subroutines will be defined, to “tell” to the CPU
what to do in the interrupt. Additional functions can be defined, function for initializations or
calculations (functions that can be called in main program of even in the interrupt
subroutines).
‐ 45 ‐
ANPC 2008 5.2.2. Settings for PWM modules
Basically the principle of implementing the PWM on DSP or other board (FPGA) is the use of
one clock that oscillates with some frequency and with one register who counts the number of
oscillations, virtual it can be seen like a counter that “counts up” to a value then again from
zero, down from a value to zero, or the symmetrical way – up to a value and down to zero. If
the counter is used in up or down count mode then the PWM will be asymmetrical, else if the
up-down mode is used then the PWM will be symmetrical. Using another register the value of
the counter is compared the value of this register (compare register) and a high or low state
will be generated to the output.
The PWM module consists in some submodules like: Time-Base, Counter-Compare, ActionQualifier, Dead-Band Generator, PWM-Chopper, Trip-Zone and Event-Trigger.
In Time-Base submodule the frequency of the PWM carrier can be defined. Basically the
desired frequency of the carrier can be defined calculating the number of the counts in one
carrier period. If up-down count mode is used, for a desired fPWM frequency the Time Base
Period Register (TBPRD) which is the value of the half of a PWM period is [14]:
TBPRD =
f CLK
,
2 × f PWM
fCLK – frequency of the clock;
fPWM – frequency of desired carrier.
The clock frequency has been defined to be the maximum frequency of this CPU which is
150 MHz.
With Time Base Phase Register (TBPHS) can be defined a delay between two PWM modules.
Also in this submodule the synchronization between modules can be defined. This
synchronization can be used in order to reduce de number of the counters used but the first
compare point can be lost and this should be taken in consideration. Setups for
synchronization and counter mode the Time Base Control Register (TBCTL) has to be
defined.
Counter-Compare submodule consists of two registers used for comparison with counter.
These two registers will contain the duty cycle of the PWM.
‐ 46 ‐
ANPC 2008 Action-Qualifier submodule is used in order to define what to do when the value of the
counter is equal with the compare registers. For example on count up the PWM output on the
event will give an high state and on count down the PWM output will be set to a low state.
The Dead-Band Generator submodule can be used for a software delay between PWM 1A and
PWM 1B the two PWM outputs of one module. In implementation for this project this module
wasn’t used because the dead time was generated hardware.
PWM-Chopper submodule is an optional block that can be bypassed if it’s necessary to use.
Here some additionally setups can be made for carrier frequency, first pulse of PWM,
different duty cycles starting with different pulses can be made.
Trip-Zone submodule can be used for protection, if a fault is happening in program this
module can force the PWM output to high, low or high impedance state. Also this module can
be optional.
Event-Trigger is a very important submodule because with his registers can be defined when
the interrupt will be, that means it can be defined when the duty cycle will be changed.
Interrupts can be done one “zero event”, when the counter reach the zero value, or one
“TBPRD” or when the compare register is equal with the counter. Also can be defined how
many times will be received the interrupts, one every period, once at two periods or once at
three periods, therefore here the duty cycle update can be changed. In this implementation
interrupt on every event have been chosen [20].
5.2.3. Sinusoidal PWM implementation
Classical methods for implementing the sine wave like a reference for PWM are using one
Sine Look up Table [14]. In this implementation wasn’t used a sine look up table because the
implementation platform TMS320F28335, 32 bits floating point operation, allow us a floating
point calculation of the variables so the sine wave will be calculated in the interrupt
subroutine. Using the classical method for a online modify of the carrier frequency or the sine
frequency there should be made some interpolations or picking some of the sine values from a
bigger resolution table. The advantage of this implementation is that the sine wave is
calculated in the interrupt, one interrupt is made one per two carrier cycles so in the next time
the calculated value can be verified, and the most important thing is the possibility of
modifying the carrier frequency, the sine frequency and amplitude in real time mode.
‐ 47 ‐
ANPC 2008 For a better control of the sine wave, the positive reference and negative reference have been
virtually separated. The separation has been made depending of the sine wave resolution;
which is naturally equal with the frequencies rapport:
Sine _ Re solution =
f PWM
f Sine
Therefore the positive sine will be between 0 and
f PWM
, and negative sine will be between
2 × f Sine
⎛ f PWM
⎞
f
⎜⎜
+ 1⎟⎟ and PWM . Must be mentioned, that after all the calculation in floating point the
f Sine
⎝ 2 × f Sine
⎠
results must be converted in integer because the counter can’t have floating point values, just
integers. This thing is happening because basically a timer oscillates between high state and
zero state (+3.3V and 0V) and the register who manages the counts must take integer values.
Implementation of the sine wave in digital can be made in two ways: offset to the entire sine
(negative and positive) or making the offset just for negative sine. The second solution was
chosen, but the disadvantage of this solution is that if just one carrier will be used to compare
the output voltage will not be symmetrical. In order to avoid this inconvenient, even if the
reference wave was modified two carriers will be used and the output voltage will be
symmetrical. This thing can be achieved by using a 180 degrees phase delay between carriers,
using two timers or only one timer with synchronization and phase delay. In Fig. 5.2.1. is
shown the implementation used.
Fig. 5.2.1. Digital PWM implementation
The implementation of sine wave is made using “math.h” header file that contains the sin
function operator in floating point. The implementation of the duty cycle is:
‐ 48 ‐
ANPC 2008 ⎡ ⎛
⎞⎤
⎟⎥
⎢ ⎜
2 ⋅ π ⋅ j ⎟⎥ ⎛ f CLK
⎜
⎢
τ = sin ⎜
⋅⎜
f PWM ⎟⎥ ⎜⎝ 2 ⋅ f PWM
⎢
⎟⎥
⎢ ⎜ f
⎣ ⎝ Sine ⎠⎦
⎞
⎟⎟ ⋅ a
⎠
τ – duty cycle;
⎡ f
⎤
j = ⎢0, PWM ⎥ ;
⎣ f Sine ⎦
a – amplitude of sine wave in relative units.
So, modifying fPWM the switching frequency of the transistors can be controlled, modifying
fSine the frequency of the reference wave can be controlled, and modifying a the amplitude of
the reference wave can be controlled. These parameters can be changed online from some
analogical inputs.
5.2.4. Practical implementation of PWM
In Chapter 3 were shown four PWM strategies. Only three from four strategies can be
implemented on the hardware solution adopted because of the restriction for safety made with
dead time generator (see 5.1.2.). The problem was to PWM1, is the strategy that is used for
NPC converter and it cannot be tested because the switches S2 and S2C can’t be both in
conduction in the same time. Further is shown the implementation of some PWM strategies.
Implementing PWM 2
For implementing this strategy for one phase leg, at least 2 PWM signals must be used in
order to control S1/S1C and S3/S3C and another 3 digital outputs to control S2/S2C and enable
signals for S1/S1C and S3/S3C. If the resources are enough, PWM signals can be used with full
or empty duty cycle.
One PWM output will control S1/S1C just a half of a period (first half when reference is
positive) and then the PWM command doesn’t maters because the output will be disabled
from the dead time generator, and the other PWM output will control S3/S3C only in the
second half of period (when the reference is negative) and when the reference is positive the
output will be disabled.
‐ 49 ‐
ANPC 2008 The enable signals will be some triangular waveforms with the frequency equal with the
reference frequency.
In implementation that has been made, 5 PWM outputs have been used, three PWM modules
have been used, the A pins used for PWM control and the pins B used for enable. The
switches S2/S2C are controlled by the third PWM.
In this implementation in order to have a symmetrical voltage, if in figure 5.2.1., the second
half is saw in mirror it can be observed that the duty cycle becomes always positive and the
second carrier becomes identical with the first one. This means that the reference wave will be
modified again with this logic.
Implementing PWM3
For this strategy only one PWM module and one GPIO output for a phase leg can be enough.
With the A signal (which has a higher resolution possibility - HRPWM) switches S2/S2C are
controlled and with the signal B the control of S1/S1C. For S3/S3C was used one GPIO output.
The reference wave implemented is the same like in fig. 5.2.1.
5.3. Summary
The implementation has been separated in two parts: hardware and software. In hardware
implementation an explanation of operating mode for gate drives and dead time generator was
detailed, a short calculation of losses have been done for choosing the heat sink and the fiber
optic bus between DSP and inverter’s PCB has been described. In software implementation
has described the PWM implementation step by step on DSP, explaining all the modules with
their operation. A short description of some PWM strategies that have been implemented was
been done.
‐ 50 ‐
ANPC 2008 Chapter 6. Laboratory
In this chapter the laboratory experimental results will be presented
DC LINK CAPACITORS 2X300VX5A POWER SUPPLY LOW POWER SIDE SUPPLY TEMPERATURE SENSOR DSP WITH FIBER OPTIC INTERFACE CONVERTER
RESISTIVE INDUCTIVE LOAD Fig. 6.1. Laboratory setup
6.1. Implementation for PWM 2
The DPS PWM output signal, gate signals and output voltage and current for PWM 2 strategy
will be shown further.
6.1.1. DSP output signals
Because the signals who reaches the dead time generator are reversed by fiber optic receivers
all the output signals from DSP are inversed. This thing is a disadvantage because the control
becomes more complicated, but is an advantage for the enable signals because for a high input
‐ 51 ‐
ANPC 2008 the controlled outputs will be enable. Also using this dead time generator, even if the PWM
command strategy is wrong will be no problem because the complementary switches can’t be
both of them in conduction in any condition and the short circuit is avoid.
Thus, on every output channel from DSP, a high output will be a low input to inverter so the
six switches of this converter are controlled with three signals. For example the control for S1
and S1C on a low output from the DSP S1 will be on and S1C off and respectively for a high
output S1C will be on and S1 off. If the PWM command requires both of these switches to be
off the enable signal will be high from DSP. The only restriction that is for this
implementation is to avoid short circuit by turning on S1 and S1C or S3 and S3C. For symmetry
the same logic was implemented for S2 and S2C even if it’s not required, this is the reason that
PWM 1 was not implemented.
In figure below can be observed that for a better visualization when the switches S1 and S1C
are not in conduction a low logic was generated. If the signal were a high it was the same
result because the enable signal from the dead time generator will disable the output.
Fig. 6.1.1. DSP output signals for PWM 2; Ch1 – S3/S3C; Ch2 – ENA S3/S3C;
Ch3 – S1/S1C; Ch4 – ENA S1/S1C
‐ 52 ‐
ANPC 2008 In figure 6.1.1. are shown the PWM output signals. Three PWM modules were used –
ePWM1 (1A – S3/S3C and 1B – ENA S3/S3C), ePWM2 (2A – S1/S1C and 2B – ENA S1/S1C),
ePWM3 (3A – S2/S2C) – the third signal for switches S2/S2C is not shown in figure above
because the signal is identical with 2B – ENA S1/S1C shown on Ch4.
6.1.2. Test waveforms for PWM 2
Test conditions:
Load:
VDC = 600V
R = 27.4 Ω
fSW = 5 kHz
L = 58.7 mH
M = 0.8
Fig. 6.1.2. Ch1 – Output voltage; Ch2 – Load current
‐ 53 ‐
ANPC 2008 (a)
(b)
(c)
Fig. 6.1.3. (a) Ch1 – VCE,S1 , Ch2 – Load current, Ch3 – VCE,S3C; (b) Ch1 – VGE,S1 , Ch2 – Load
current, Ch3 – VGE,S3C; (c) Ch1 – VGE,S1C , Ch2 – Load current , Ch3 – VGE,S3
Figure 6.1.3. (a) shows exactly how the states are made in this strategy, the positive voltage
by clamping between switches S1 and S1C switching between + and 0, and the negative
voltage be clamping between S3 and S3C switching between – and 0.
In figure 6.1.4. can be observed the switches temperature. The switches are numbered from
left to right like this: S1, S1C, S2, S2C, S3, S3C ; them can be identified from previous figure,
fig.2.1.7. from chapter 2. The loss distribution is good, with reservation that from a
mechanical mistake the switch S1C is very close to S2.
‐ 54 ‐
ANPC 2008 Fig. 6.1.4. Infrared picture at VDC = 600V, IRMS = 5A, M = 0.8, fC = 5kHz using PWM 2
6.2. Implementation for PWM 3
6.2.1. DSP output signals
For this implementation just three PWM outputs are necessary, the PWM signals without any
enable signals. Therefore two PWM modules were used: ePWM1 (1A – S2/S2C and 1B –
S1/S1C), ePWM2 (2A – S3/S3C)
In figure 6.2.1. are the control signals, in first half the reference is positive, the signals for
S1/S1C and S3/S3C are low and this results S1 and S3 on, the signal for S2/S2C, when is low the
S2 is on and when is high S2C is on, and complementary when the reference wave is negative
for S1/S1C and S3/S3C.
‐ 55 ‐
Fig. 6.2.1. DSP output signals for PWM 3; Ch1 – S2/S2C; Ch2 – S1/S1C;
Ch3 – S3/S3C;
6.2.2. Test waveforms for PWM 3
Fig. 6.2.2. Ch1 – Output voltage; Ch2 – Load current
‐ 56 ‐
ANPC 2008 ANPC 2008 The tests for this strategy are made in the same conditions: VDC = 600V, fSW = 5 kHz, M = 0.8,
R = 27.4 Ω, L = 58.7 mH.
In figure 6.2.2. it can be observed the effect of the inductance load, the current is inductive
and the angle between the fundamental voltage and current makes the current negative when
the voltage is still positive and then the recovery diodes are in conduction and the voltage
drop on the diodes makes the output voltage bigger when the current is negative.
(a)
(b)
Fig. 6.2.3. (a) Ch1 – VCE,S1; Ch2 – Load Current; Ch3 – VCE,S2C ; (b) Ch1 – VGE,S1; Ch2 –
Load Current; Ch3 – VGE,S2C
Fig. 6.2.4. Infrared picture at VDC = 600V, IRMS = 5A, M = 0.8, fC = 5kHz using PWM 3
‐ 57 ‐
ANPC 2008 From the infrared picture using this strategy it can be observed that on this frequency the
switching losses are more important in comparison with conduction losses so the switches S2
and S2C that switch at nominal frequency, in comparison with the other switches that switch at
reference wave frequency, have a higher temperature.
6.3. Implementation for PWM 4
6.3.1. DSP output signals
For this PWM strategy five PWM outputs were used. Three PWM modules – ePWM1 (1A –
S1/S1C and 1B – ENA S1/S1C), ePWM2 (2A – S3/S3C and 2B – ENA S3/S3C), ePWM3 (3A –
S2/S2C). The reason for establishing this order was the delay between carriers, so these three
PWM modules are in synchronism and the last one is with phase delay. If one module is setup
with phase delay the next module which is in synchronizations keeps the same delay or can be
higher.
Fig. 6.3.1. DSP output signals for PWM 4; Ch1 – S1/S1C; Ch2 – ENA S1/S1C;
Ch3 – S2/S2C; Ch4 – ENA S3/S3C
‐ 58 ‐
ANPC 2008 In figure above are shown the control signals for PWM 4. The signal for S3/S3C is not shown
but it’s the same like the signal for S1/S1C from Ch1.
6.3.2. Test waveforms for PWM 4
In figure 6.3.2. is the test result for this strategy. Test conditions: VDC = 600V, fSW = 5 kHz,
M= 0.8; load R = 27.4 Ω, L = 58.7 mH. If we look in the same time to this figure and the
figures before (Fig. 6.1.2. and Fig 6.2.2.) it can be observed the doubling apparent switching
frequency using this strategy with ANPC Converter.
Were also made some measurements in order to prove the advantage that can bring this
strategy, for the same output current IRMS = 4A, VDC = 600V, running PWM2/3 with 10kHz
and PWM 4 with 5kHz the output parameters are the same and the input power was measured.
PPWM2/PWM3 = 1350W; PPWM4 = 1310W
These measurements proves that using PWM4 for control the switching losses are diminished,
not at a half value because in PWM 4 four switches switch at the nominal frequency and two
have the average frequency the half of nominal switching frequency.
Fig. 6.3.2. Ch1 – Output voltage; Ch2 – Load current
‐ 59 ‐
ANPC 2008 In figures 6.3.3.(a), (b) and (c) it can be observed the collector to emitter voltages for some
transistors. The switching frequency is 5 kHz.
In fig. 6.3.3.(d) are the gate to emitter voltages for transistors S3C and S1, and here can be
observed the operation of the gate drives optocouplers used in this implementation. On
VGE = 15V the transistor is in conduction and respectively on VGE = −15V transistor is
blocked (for example, see fig. 6.3.3. (a) – Ch1 – VCE,S1, and (d) – Ch3 – VGE,S1).
(a)
(b)
(c)
(d)
Fig. 6.3.3. (a) Ch1 – VCE,S1 ; Ch2 – Load current; Ch3 – VCE,S3C ; (b) Ch1 – VCE,S1C ;
Ch2 – Load current; Ch3 – VCE,S3 ; (c) Ch1 – VCE,S2C ; Ch2 – Load current; (d) Ch1 – VGE,S2C ;
Ch2 – Load current; Ch3 – VGE,S1
‐ 60 ‐
ANPC 2008 Fig. 6.3.4. Infrared picture at VDC = 600V, IRMS = 5A, M = 0.8, fC = 5kHz using PWM 4
Fig. 6.3.4. Infrared picture on the converter low power side
6.4. Summary
The test results of three PWM strategies were presented, starting with control signals from
DSP for each of them. Waveforms for tests when power was applied are presented.
Measurements were made in order to prove the advantage using PWM4 strategy.
‐ 61 ‐
‐ 62 ‐
ANPC 2008 ANPC 2008 Chapter 7. Conclusion
A small comparison between theoretical simulations and practical tests will be done.
Summary of the report and future work will be also presented.
7.1. Comparison between simulations and test results
The simulations were made in order to prove the proper practical operation for the same
conditions like in laboratory tests: VDC = 600V, fSW = 5 kHz, M= 0.8; load R = 27.4 Ω,
L = 58.7 mH. In these simulations are also included: diode forward voltage drop VFM = 2.5V,
collector to emitter saturation voltage VCE(on) = 3.17 V [16], and dead time td = 1.55 μs.
7.1.1. PWM 2
Fig. 7.1.1. Simulation result for PWM 2 strategy
It can be observed firstly from the simulation, Fig. 7.1.1., that when the current is negative the
current will flow through recovery diodes and then the voltage will be shifted up with 5V
‐ 63 ‐
ANPC 2008 (2.5V per diode, two diodes in conduction). Also when in conduction are transistors the
voltage will be shifted down, when the voltage is positive, with collector to emitter saturation
voltage which is 3.17V. In test result, see Fig. 6.1.2., this is not so clear but if a zoom will be
made this thing could be proved.
7.1.2. PWM 3
Fig. 7.1.2. Simulation result for PWM 3 strategy
In this implementation the reference wave was modified like in fig. 5.2.1., making an offset to
the negative sine wave. The result can be saw in fig. 6.2.2., and it is not quite good because
the negative voltage, exactly in the middle of it, where the duty cycle is maximum the voltage
stays to much in direct current and because of this the shape of the current is not so good as
expected. Therefore for this strategy the negative load current has a bigger peak value then the
positive load current, also the mean values for voltage and current are negative and them
should be zero or very close to zero.
‐ 64 ‐
ANPC 2008 7.1.3. PWM 4
Fig. 7.1.3. Simulation result for PWM 4 strategy
In the same conditions this strategy was simulated. The print step was delayed with 40ms
because in simulation the start is different (see fig. 7.1.2.). It can be observed the resolution
differences in comparison with the previous strategies even on 5 kHz switching frequency.
This strategy can be attractive for high power application where the switching frequency is
limited because the transistors must block a big voltage and also the current that must be
interrupted is big and the dynamic operations are more slowed because the switching losses
are very high [11]. Therefore, for a switching frequency of 1 kHz the difference between first
two strategies and the last one will be very important.
7.2. Summary
An introduction in three level converters concept and operation was made. A comparison
between the popular three level converters showing the advantages and disadvantages for
every topology was presented. Four strategies that can be implemented on ANPC converter
were shown. Simulations for them in order to prove their operation has been made, and were
‐ 65 ‐
ANPC 2008 also used to show the differences between them. A description of hardware implementation
with all the components showing their functionality was made. The software implementation
using TMS320F28335 platform was made; the functionality and the way of setup the PWM
modules were presented. In final the laboratory setup was described, the PWM outputs from
DSP were shown for all three strategies implemented and the test results have been presented.
In the end a small comparison between simulation waveforms and test waveforms was
discussed.
7.3. Future Work
¾ Over current and under voltage protection
¾ Implementation of an input that can change the switching frequency on the fly
¾ Open loop tests
¾ Three phase implementation using in control a particular 3L Space Vector Modulation
¾ Measurements interface for analog input of DSP
¾ Grid connection for wind or solar applications
¾ AC Drive control implementation
‐ 66 ‐
ANPC 2008 References
[1] Baker R.H.: Electric Power Converter, U.S.Patent Number 3 867 643, Feb.1975
[2] Dan Floricau, Guillaume Gateau, Mariana Dumitrescu, Remus Teodorescu, “A new
stacked NPC converter: 3L-topology and control” IEEE European Conference on Power
Electronics and Applications, 2007
[3] Thomas Brückner, Steffen Bernet, Peter K. Steimer, “ Feedforward Loss Control of ThreeLevel Active NPC Converters” IEEE Transactions on industrial applications, Vol. 43, No. 6,
November/December 2007.
[4] Jose Rodrigues, “Tutorial on multilevel converters”. (CD)
[5] Dietmar Krug; Mariusz Malinowski; Steffen Bernet; “Design and comparison of medium
voltage multi-level converters for industry applications” Industry Applications Conference,
39th IAS Annual Meeting. Conference Record of the 2004 IEEE Volume 2,
2004 Page(s): 781 - 790 Vol.2.
[6] Thomas Brückner, Steffen Bernet, Henry Güldner, “The Active NPC Converter and Its
Loss-Balancing Control”, IEEE Transactions on industrial electronics, Vol. 52, No. 3, June
2005.
[7] Keith Corzine, ”The Power Electronics Handbooks”, Chapter 6, CRC Press, 2002.
[8] Muhammad H. Rashid, ”Power Electronics Circuits, Devices, and Applications”, Third
Edition, Pearson Education International.
[9] Nabe, A., Takahashi, I., and Akagi, H., ”A new neutral-point clamped PWM inverter”,
IEEE Transactions on Industry Applications, 1981.
[10] Muhammad H. Rashid, ”Power Electronics Handbook”, Academic Press, 2001
‐ 67 ‐
ANPC 2008 [11] Thomas Brückner, Steffen Bernet, Peter K. Steimer, ”The Active NPC Converter for
Medium-Voltage Applications” Industry Applications Conference, 2005. Fourtieth IAS
Annual Meeting. Conference Record of the 2005 IEEE Volume 1, 2005 Page(s): 84 - 91
Vol.1.
[12] D. Floricau, E. Floricau, M. Dumitrescu, ”Natural Doubling of the Apparent Switching
Frequency using Three-Level ANPC Converter”, International School on Nonsinusoidal
Currents and Compensation - ISNCC, 10-13 June 2008, Lagow, Poland.
[13] D.Floricau, E.Floricau, G.Gateau, ”Three-level SNPC Commutation Cell: Features and
Control”, IEEE International Symposium on Industrial Electronics, ISIE'08, 30 June-2 July,
2008, Cambridge, UK.
[14] Liu Jian, Yin Xianggen, Zhang Zhe, Xiong Qing, “Study on Theory and Key
Technologies of Full Digital SPWM Implementation for Three-Level Neutral Point Clamped
Inverter”, IEEE International Conference on Communications, Circuits and Systems,
ICCCAS 2007
[15] Mika Ikonen, Ossi Laakkonen, Marko Kettunen, ”Two-level and three-level
converter comparison in wind power application”, Department of Electrical
Engineering, Lappeenranta University of Technology, P.O. Box 20, FI-53851 Lappeenranta,
Finland
CD:
[16] IRG4PH20KD DataSheet - Insulated Gate Bipolar Transistor with ultra soft recovery
diode
[17] HCPL-3150 DataSheet - IGBT Gate Drive Optocoupler
[18] IA0515S DataSheet - XP DC_DC Converter
[19] IXDP631 PI DataSheet - Dead time generator for PWM controls
[20] TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference
Guide
‐ 68 ‐
ANPC 2008 Appendix A
ANPC Design
Fig.B.1. ANPC PCB Design
‐ 69 ‐
GND
P0R10201
HCPL_1
P0HCPL0108
1P0HCPL0101
8
N/C VCC P0HCPL0107
2 P0HCPL0102
7
Anode Vo
R1_2
P0R10202
267
3 P0HCPL0103
6
Cathode VoP0HCPL0105
4P0HCPL0104
5
N/C
VEE
P0HCPL0106
P0C10402P0C10401
P0R902
R9
1k
1
P0DC/DC0101
DC
C1_4
10uF
2
P0DC/DC0102
P0R20202
3 P0HCPL0203
6
Cathode VoP0HCPL0205
4P0HCPL0204
5
N/C
VEE
P0R1002
P0C20402P0C20401
P0R1001
P0REC0ENA0R0OUT
1
P0DC/DC0201
C2_4
10uF
P0S1c02
220uF
2
P0DC/DC0202
DC
P0R301
P0R1201
P0R701
C3_4
10uF
P0REC0ENA0S0OUT
P0R40201
P0R702
P0R40202
C7_2
100pF
O
DC
A
100pF
GND
P0R401
1
P0DC/DC0401
DC
C4_1
220uF
56
S2c
IRG4BC20KD
P0R402
DC/DC_4
GND
P0C70101 P0C70102
C4_3
1uF
R4
P0S2c02
HCPL_4
P0HCPL0406
3 P0HCPL0403
6
Cathode Vo
P0HCPL0405
4P0HCPL0404
5
N/C
VEE
P0C40402P0C40401
P0C70201P0C70202
2
P0DC/DC0302
267
C7_1
SFH551/1V-1
P0DC/DC0305
P0HCPL0408
1P0HCPL0401
8
N/C VCC P0HCPL0407
2 P0HCPL0402
7
Anode Vo
R4_2
P0REC0ENA0S0GND
220uF
GND
90.9k
XTAL
P0XTAL02
1
2
P0XTAL01
P0REC0ENA0S0Vcc
5
4
P0DC/DC0303
3
C3_2
B
P0DC/DC0304
GND
GND
R7
GND
C8_4 REC_ENA_S R12
1k
DC
P0S202
P0C30102P0C30101
56
P0C40102P0C40101
P0R1202
GND
1
P0DC/DC0301
IRG4BC20KD
P0S201
P0S2c01
P0C40202P0C40201
VCC
P0C30402P0C30401
P0REC0S0OUT
S2
220uF
P0R302
DC/DC_3
GND
C3_1
P0S203
3 P0HCPL0303
6
Cathode VoP0HCPL0305
4P0HCPL0304
5
N/C
VEE
VCC
C3_3
1uF
R3
P0*01
P0REC0S0Vcc
P0C80401
P0R30202
P0HCPL0306
R
VCC P0*018
P0*02
ENAR
RU P0*017
P0*03 S
RL P0*016
P0*04
ENAS
SU P0*015
P0*05 T
SL P0*014
P0*06
ENAT
TU P0*013
P0*07
OUTENA
TL P0*012
P0*08
P0*011
/RST
OSCOUT
P0*09
GND
XTLINP0*010
1k
HCPL_3
C4_2
P0S2c03
*
R11
SFH551/1V-1
P0C80400
C2_2
5
4
P0DC/DC0203
3
267
Dead Time Generator
P0REC0S0GND
P0C90402P0C90401
IRG4BC20KD
P0S1c01
P0C30202P0C30201
P0R1102
REC_S
P0R1101
P0C80301
P0C80300
P0C90302 P0C90301
B
100n
P0R202
S1c
P0DC/DC0205
P0HCPL0308
1P0HCPL0301
8
N/C VCC P0HCPL0307
2 P0HCPL0302
7
Anode Vo
R3_2
P0R30201
22u
220uF
GND
GND
C9_4
DC
C2_1
P0DC/DC0204
GND
GND
SFH551/1V-1
100n
P0R201
56
P0C30302P0C30301
P0C80201
P0C80200
P0C90202P0C90201
1k
R2
DC/DC_2
GND
REC_ENA_R R10
C2_3
1uF
P0C20102P0C20101
HCPL_2
P0REC0ENA0R0GND
22u
2.2uF
A
P0C20202P0C20201
P0R20201
P0REC0ENA0R0Vcc
C8_3
C1_2
DC
P0HCPL0206
C9_3
IRG4BC20KD
P0S101
5
4
P0DC/DC0103
3
267
100n
P0R102
P0DC/DC0105
P0HCPL0208
1P0HCPL0201
8
N/C VCC P0HCPL0207
2 P0HCPL0202
7
Anode Vo
R2_2
GND
22u
S1
2.2uF
P0S1c03
GND
GND
SFH551/1V-1
C8_2
C1_1
GND
P0REC0R0OUT
P0REC0R0GND
C9_2
8
P0DC/DC0104
P0REC0R0Vcc
100n
P0R101
56
P0C20302P0C20301
REC_R
P0R901
P0C80101
C8_1
P0C80100
22u
P0C90102 P0C90101
C9_1
C1_3
0.1uF
R1
DC/DC_1
GND
A
7
P0S102
6
P0S103
5
P0C10102P0C10101
4
P0C10202P0C10201
3
P0C10302P0C10301
2
P0C40302P0C40301
1
220uF
5
4
P0DC/DC0403
3
P0DC/DC0405
P0DC/DC0404
C4_4
10uF
2
P0DC/DC0402
DC
P0REC0ENA0T0Vcc
P0REC0ENA0T0OUT
100n
P0LED 102
P0LED 101
LED2
VCC
P0LED201
1
P0DC/DC0501
C5_4
10uF
GND
GND
P0R60201
2
P0DC/DC0502
P0S302
P0C50102P0C50101
P0S303
P0C50202P0C50201
P0C50302 P0C50301
DC
HCPL_6
P0R60202
3 P0HCPL0603
6
P0HCPL0606
Cathode Vo
4P0HCPL0604
5
P0HCPL0605
N/C
VEE
P0C60402P0C60401
VCC
2 P0Supply02
1 P0Supply01
1
P0DC/DC0601
C6_4
10uF
GND
C6_3
1uF
R6
P0R601
56
DC/DC_6
GND
D
5
4
P0DC/DC0503
3
1P0HCPL0601
8
P0HCPL0608
N/C VCC
2 P0HCPL0602
7
P0HCPL0607
Anode Vo
GND
Supply
220uF
P0DC/DC0505
267
SFH551/1V-1
C5_2
P0DC/DC0504
R6_2
P0REC0ENA0T0GND
DC
P0S301
GND
P0LED202
GND
56
S3
IRG4BC20KD
P0R502
DC/DC_5
GND
220uF
DC
2
P0DC/DC0602
C6_1
P0S3c02
1k
GND
750
P0R501
C5_1
220uF
S3c
IRG4BC20KD
P0R602
P0S3c01
C6_2
P0S3c03
P0R1402
Reset Button
REC_ENA_T R14
P0R1401
P0C80601
P0C80600
P0C90602P0C90601
22u
C8_6
P0HCPL0506
3 P0HCPL0503
6
Cathode Vo
P0HCPL0505
4P0HCPL0504
5
N/C
VEE
C5_3
1uF
P0C60102P0C60101
20
C9_6
267
R5
P0C60202P0C60201
R10
LED 1
P0R801
P0R1002
VCC
GND
P0R50202
R8
10k
P0Reset Button01P0Reset Button02
P0R1001
P0REC0T0GND
GND
P0C60302P0C60301
R9
P0R50201
P0R802
100nF
C
HCPL_5
P0HCPL0508
1P0HCPL0501
8
N/C VCC
P0HCPL0507
2 P0HCPL0502
7
Anode Vo
R5_2
P0C30302P0C30301
P0REC0T0OUT
SFH551/1V-1
GND
GND
P0C50402P0C50401
1k
P0REC0T0Vcc
100n
GND
C3_3
R13
P0R902
P0C80501
REC_T
P0R901
22u
C8_5
P0C80500
C9_5
P0C90502 P0C90501
C
P0R1301
P0R1302
GND
GND
220uF
5
P0DC/DC0604
4
P0DC/DC0603
3
P0DC/DC0605
D
DC
GND
Title
GND
Size
A2
Date:
File:
1
2
3
4
5
6
Number
Active NPC Schematic
Revision
10-Jun-08
Sheet of
F:\Proiect Diploma\..\Schematic ANPC.SchDoc
Drawn By:
7
8
Appendix B
Fiber Optic interface Design
Fig. B.1. Fiber optic interface design
‐ 71 ‐
ANPC 2008 ANPC 2008 Appendix C
CD
The attached CD contains:
¾ The report in PDF format
¾ DataSheets folder – contains datasheet for the components that are used
¾ DSP Work folder – contains the programs developed for PWM strategies
¾ Altium Designer Work folder – contains the design files
¾ Literature folder – contains the literature that are not from IEEE
¾ Simulations folder – contains the PSIM files for simulations
¾ Texas Instruments folder – contains the guides used to develop the programs and
some technical documentation for the used platform
‐ 72 ‐