An On-Chip, Attofarad Interconnect Charge-Based Capacitance Measurement
(CBCM) Technique
James C. Chen, Bruce W. McGaughy, Dennis Sylvester, and Chenming Hu
Dept. of EECS, University of California Berkeley, 211-37 Cory Hall #1772,
Berkeley, CA 94720-1772, FAX: (510) 642-2759, Phone: (510) 642-8861,
Email: jamesc@cory.eecs.berkeley.edu
Abstract
II. Methodology
In this paper, a sensitive and simple technique for
parasitic interconnect capacitance measurement with
0.01fF or 10 aF sensitivity is presented. This on-chip
technique is based upon an efficient test structure
design. No reference capacitor is needed. The measurement itself is also simple; only a DC current meter is
required. We have applied this technique to extract various interconnect geometry capacitances, including the
capacitance of a single Metal 2 over Metal 1 crossing,
for an industrial double metal process.
The improved test structure is shown in Figure 1. It
consists of a pair of NMOS and PMOS transistors connected in a “pseudo” inverter configuration (each has
its own gate input). The pseudo inverter structure on
the left is used as a reference to achieve the highest resolution. This left test structure is identical to the right in
every manner except that it does not include the target
capacitance to be characterized. For example in Figure
1, the left structure does not include the Metal 1 to
Metal 2 overlap capacitance to be measured.
NWELL
VDD(No Cap)
VDD(Cap)
I. Introduction
A
As integrated circuits become increasingly laden
with metal interconnects, the resulting inter-metal
capacitances are rapidly becoming the bottleneck in the
design of faster chips. Past on-chip interconnect capacitance techniques have relied on either a reference
capacitor and/or a complicated test-structure design
and measurement setup [1,2,3]. Other methods usually
require more elaborate test structure designs [4].
Besides consuming large area, these techniques usually
provide only pico-farad resolution capabilities.
A method was introduced [5] to account for the
deficiencies of the above methods. In this paper, we
will not only introduce an improved version of the test
structure layout, but provide an on-chip signal generator and an entirely new measurement scheme as well.
The resolution limit of our methodology is estimated to
be 0.01fF, hence making it more than adequate for
characterizing parasitic interconnect capacitances. We
call this technique Charge-Based Capacitance Measurement (CBCM).
V2
Signal
Generator
V1
Metal 1
AAAA
AAAAAAA
AAA
Metal 2
I’
A
I
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
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AA
AA
AA
AA
Figure 1. Proposed test structure for interconnect
capacitance characterization.
The V1 and V2 signals of Figure 1 consists of two nonoverlapping signals shown in Figure 2. These signals
can be either generated off-chip or on chip (Figure 3).
The purpose of these non-overlapping waveforms is to
ensure that only one of the two transistors in the basic
test structure is conducting current at any given time.
Thus, short-circuit current from Vdd to ground is eliminated. When the PMOS transistor turns on, it will
This work is supported by SRC contract IJ-148-A and
HP under the MICRO program.
0-7803-3393-4/96/$5.00 (c) 1996 IEEE
Figure 3. On-chip signal generator for V1 and V2 with surrounding test structures.
draw charge from Vdd to charge up the target interconnect capacitance.
Vdd
V1
(NMOS)
0
Vdd
V2
(PMOS)
0
Freq
t1 t2
t3 t4
Time
I – I′ = I
net
I
= C⋅V ⋅f
net
dd
(1)
(2)
In order to verify that the extracted capacitance
value is accurate, we propose a new, self-checking
extraction scheme. Inet is plotted as a function of Vdd
for specific frequency values (Figure 4). The value of C
can then be extracted by dividing the slope of the fitted
line by the appropriate frequency value. Alternatively,
Inet can also be plotted as a function of frequency for
specific values of Vdd (Figure 5). The value of C can
then be extracted by dividing the slope by the appropriate Vdd value. An average of all these values is then
taken to be the extracted capacitance value.
Figure 2. NMOS and PMOS transistors are driven
by non-overlapping signals. These signals ensure
that there is no short circuit current.
This amount of charge will then be subsequently discharged through the NMOS transistor into ground. An
ammeter can be placed at the source of the PMOSFET
(or, alternatively at the source of the NMOSFET) to
measure this charging current. The actual waveform of
this charging current is of no consequence - only its DC
or average current value needs to be measured. DC current can be easily obtained from any modern current
meter. The difference between the two DC current values in Figure 1 is used to extract the target interconnect
capacitance as shown by Eqs. 1 and 2 below.
Figure 4. Inet plotted as a function of Vdd for three
frequency values. The interconnect capacitance is
extracted from the slope.
0-7803-3393-4/96/$5.00 (c) 1996 IEEE
total capacitance as a function of distance is plotted in
2
Figure 6. An approximate 1 ⁄ d dependence was
observed.
1----2
d
Metal 2
1.5µ
µm
Figure 5. Inet plotted as a function of frequency for
seven Vdd values. Capacitance is extracted from the
slope.
d
1.5µ
µm
III. Application and Results
A test chip (Figure 3) was fabricated in an industrial
0.8µm, double metal technology with many interconnect
test structures. One of these structures was a single overlap of Metal 1 and Metal 2 with an area of 1.5µm X
1.5µm or 2.25µm2 (Figure 1). The proposed measurement/extraction scheme (Figures 4 and 5) was used. The
resulting capacitance readings are summarized in Table
1 below.
Slope Data Used for Extraction
Extracted
Capacitance (fF)
Inet vs. Vdd for Frequency=5.0MHz
Inet vs. Vdd for Frequency=1.0MHz
Inet vs. Vdd for Frequency=0.6MHz
Inet vs. Frequency for Vdd=5.0V
Inet vs. Frequency for Vdd=4.5V
Inet vs. Frequency for Vdd=4.0V
Inet vs. Frequency for Vdd=3.5V
Inet vs. Frequency for Vdd=3.0V
Inet vs. Frequency for Vdd=2.5V
Inet vs. Frequency for Vdd=2.0V
Average
0.4523
0.4407
0.4412
0.4535
0.4399
0.4399
0.4395
0.4425
0.4429
0.4390
0.4431
Table 1. Summary of interconnect capacitances
extracted from the slopes of Figures 4 and 5. A small
deviation of less than 2% is observed about the average value.
An average value of 0.44fF was obtained. This technique was also applied to characterize the inter-wire
capacitance between two parallel Metal 2 lines as a
function of their separation distance, d. The increase in
Figure 6. Measured Metal 2 inter-wire capacitance
versus separation distance, d. The dimensions of
each wire is 135µ
µm x 1.5µ
µm.
The total capacitance between a Metal 2 line and the
silicon substrate was also measured as a function of
drawn width (Figure 7). Unit area as well as fringe
capacitance per unit length can be easily extracted.
Lastly, Figure 8 shows measured capacitances as a
function of total overlaps between Metal 1 and Metal
2. A saturating effect can be seen for the first time.
Slope/Length =
Capacitance/Unit
Area = 0.0196fF/µ
µm 2
Length=135µ
µm
W
Intercept/2*Length =
Fringe Capacitance =
0.0419fF/µ
µm
Substrate
Figure 7. Measured Metal 2 capacitance over silicon substrate as a function of drawn width. The
length is 135µ
µm. Unit area and fringe capacitance
per unit length can be easily determined.
0-7803-3393-4/96/$5.00 (c) 1996 IEEE
is simple and direct. With signal generators integrated
on-chip, only a DC current meter is required. A selfchecking extraction algorithm ensures that the
extracted capacitance value is robust and accurate.
Many interconnect capacitances parasitics were measured using this technique.
135µ
µm
Metal 2
VI. References
Metal 1
Substrate
Number of Metal 1 Lines
Figure 8. Measured Metal 1 to Metal 2 overlap
capacitances with a constant Metal 2 length of 135µ
µm
and Metal 1 width of 1.5µ
µm. The spacing between
Metal 1 lines is varied. A saturating effect can be
seen.
IV. Discussion
The resolution limit of CBCM is the mismatch of the
drain junction and overlap capacitances between the two
sets of transistors of the test structure.
For example, the measured DC current for the
pseudo inverter with and without the target interconnect
capacitance is given by Eqs. 3 and 4, respectively. C is
the unknown capacitance to be measured and C’ is the
MOSFET gate to drain overlap capacitance plus drain
junction capacitance plus any other parasitic capacitances. Ideally, if the two pseudo inverters are perfectly
matched, the C’ term would be completely subtracted
out (see Eq. 1). In reality, there will be a small mismatch
between the parasitic capacitances, C’, of the two identical pseudo inverters positioned close to each other.
Assuming C’ to be around 1fF and the mismatch to be
1%[3], the resolution capability of this method would be
0.01fF.
I = ( C + C′ ) ⋅ V
I′ = C′ ⋅ V
dd
dd
⋅f
⋅f
[1]. A. Khalkhal and P. Nouet, “On-Chip Measurement of
Interconnect Capacitances in a CMOS Process,” Proc.
IEEE 1995 Int. Conf. on Microelectronic Test Structures,
vol. 8, March 1995.
[2]. G.J. Gaston and I.G. Daniels, “Efficient Extraction of
Metal Parasitic Capacitances,” Proc. IEEE 1995 Int.
Conf. on Microelectronic Test Structures, vol. 8, March
1995.
[3]. J.B. Shyu, G.C. Temes, and F. Krummenacher, “Random Effects in Matched MOS Capacitors and Current
Sources,” IEEE Journal of Solid State Circuits, vol. sc19, no. 6, pp. 948-955, December 1984.
[4]. C. Kortekaas, “On-Chip Quasi-Static Floating-Gate
Capacitance Measurement Method,” Proc. IEEE 1990
Int. Conf. on Microelectronic Test Structures, vol. 3,
March 1990.
[5]. Bernard Laquai, Harald Richter, and Bernd Hofflinger,
“A New Method and Test Structure for Easy Determination of Femto-Farad On-Chip Capacitances in a MOS
Process,” Proc. IEEE 1992 Int. Conf. on Microelectronic
Test Structures, vol. 5, March 1992, pp.62-66.
(3)
(4)
V. Conclusion
In this paper, a new technique, CBCM (ChargeBased Capacitance Method), for characterizing interconnect capacitances is presented. This technique has an
estimated sensitivity of 0.01fF. The measurement setup
0-7803-3393-4/96/$5.00 (c) 1996 IEEE