NXP Dual PCB
Configurable
Logic
Printed circuit board (PCB)
configurable Logic function
The NXP dual PCB configurable device is a multi gate, multi function logic device
with two configurable gates that can each be individually configured by the PCB
layout into one of seven unique functions.
KEY FEATURES
APPLICATIONS
• Wide supply voltage range from 0.8 V to 3.6 V
• ESD protection 5000 V
• Low static power consumption; ICC = 0.9 µA (maximum)
•Latch-up performance exceeds 100 mA per
JESD 78 Class II
• Inputs tolerate voltages up to 3.6 V
• Low noise overshoot and undershoot < 10% of VCC
•IOFF circuitry provides partial power-down mode
operation
• Specified from -40 ºC to +125 ºC
•Industrial
•Smart phones, tablets, and PCs
•Digital cameras
•Wearables and portable medical devices
•Other low voltage applications
BENEFITS
•Two PCB configurable functions in one package
•PCB layout configurable
•Reduces inventory and assembly costs
•High noise immunity
•Wide range of functions (7 x 7)
ENDLESS POSSIBILITIES
The NXP dual PCB configurable device is a multi gate, multi
function logic device with Schmitt-trigger inputs. Each device
contains two configurable gates which can be individually
configured into one of seven different functions per device.
Each family (-57, -58, -97, -98) device contains a selection
of seven logic functions from the total library of 18 unique
functions. Some of the basic functions available are; AND,
OR, NAND, NOR, XNOR, Inverter, Buffer and Mux. Each
family device offers a different variety of available functions.
The desired function is selected by how the PCB layout
connects the three input pins of each configurable gate.
74AUP1G04 (Inverter)
74AUP1G00 (NAND)
724AUP1G02 (NOR)
VCC
C
Y
B
A
A
B
Y
C
GND
Figure 1. 74AUP2G57 dual PCB configurable logic function block diagram
74AUP2G57
Figure 2. Space saving comparison for dual PCB configurable vs. discrete
implementation.
Available functions
B
C
Y
B
C
Y
A
C
A
C
Y
Y
B
C
Y
B
Y
A
Y
B
C
Y
B
Y
A
Y
Y
B
C
Y
B
Y
A
Y
Y
B
C
Y
B
Y
A
Y
74AUP2G57
B
C
B
C
Y
A
C
Y
A
C
B
C
Y
B
C
Y
B
C
Y
Y
A
C
Y
Y
A
C
Y
Y
A
C
Y
A
C
B
C
Y
A
C
Y
B
C
Y
A
C
Y
B
C
Y
A
C
Y
Y
A
C
74AUP2G58
B
C
74AUP2G97
74AUP2G98
A
C
A
C
B
A
C
Y
B
A
C
Y
B
C
Y
Y
Note: Each family device (-57/-58/-97/-98) implements two independent copies of the above PCB configurable logic gates into one package.
Package suffix
Package
Width (mm)
Length (mm)
Height (mm)
Pitch (mm)
www.nxp.com
DP
GM
GU
GF
10-pin (TSSOP)
10-pin (XQFN)
10-pin (XQFN)
10-pin (XSON)
SOT552-1
4.90
3.00
1.10
0.50
SOT1049-1
1.55
2.00
0.50
0.50
SOT1160-1
1.40
1.80
0.50
0.40
SOT1081-2
1.00
1.70
0.40
0.35
© 2014 NXP Semiconductors, B.V.
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The informa-
Date of release: October 2014
tion presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be
Document order number: 9397 750 17615
changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey
Published in the USA
nor imply any license under patent or other industrial or intellectual property rights.