Potential and limitation of RF CMOS Technology
and expectation for new passive devices
Akira Matsuzawa
Department of Physical Electronics
Tokyo Institute of Technology
2004. 03. 02
TITech A. Matsuzawa
1
Contents
• Current status of RF CMOS technology
• Feature of RF CMOS technology
–
–
–
–
Comparison with bipolar
Scaling rule
RF CMOS circuits
Architecture
• Expectation for new passive devices
– Inductor, resonator, switches
– Needs for reconfigurable RF circuits
• Summary
2004. 03. 02
TITech A. Matsuzawa
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Current status of RF CMOS chip
RF CMOS was an university research theme, however
currently becomes major technologies in the wireless world.
• Current products
–
–
–
–
–
Bluetooth: 2.4GHz, CSR etc., major
Wireless LAN: 5GHz, Atheros etc., major
CDMA : 0.9GHz-1.9GHz, Qualcomm, becomes major
Zigbee: 2.4GHz, not yet, however must use CMOS
TAG: 2.4GHz, Hitachi etc., major
Major Cellular phone standard, GSM uses SiGe-BiCMOS technology
2004. 03. 02
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Why CMOS?
• Low cost
– Must be biggest motivation
– CMOS is 30-40% lower than Bi-CMOS
• High level system integration
– CMOS is one or two generations advanced
– CMOS can realize a full system integration
• Stable supply and multi-foundries
– Fabs for SiGe-BiCMOS are very limited.
Æ Slow price decrease and limited product capability
• Easy to use
– Universities and start-up companies can use CMOS with
low usage fee, but SiGe is difficult to use such programs.
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Wafer cost example
The wafer cost of SiGe BiCMOS is 30-40% higher than CMOS at the same
generation, however almost same as one generation advanced CMOS.
30%
45%
0.
25
Si
G
e_
BC
0.
25
_S
iG
e_
BC
0.
18
um
_C
0.
15
um
_C
0.
13
um
_C
2004. 03. 02
45%
Low cost
SiGe 23%
0.
25
_C
0.
35
_C
4500
4000
3500
3000
2500
2000
1500
1000
500
0
TITech A. Matsuzawa
7M
6M
5M
4M
3M
Dataquest March 2001
+SiGe estimation
5
RF CMOS device technology
RF CMOS needs some process options,
however significant cost increase can’t be accepted.
Varactor
Hi-Q inductor
High Rsub
Small loss
ESD
Thicker Metal
Small
Mismatch
RF
RF
CMOS
CMOS
Higher
voltage
High-R
Larger
Cap.
Conventional
ConventionalCMOS
CMOStechnology
technology
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MOS vs SiGe-Bip
MOS
Gm
fTpeak
SiGe-Bip
Ids
Ids
≈
⎛ Veff ⎞ 100mV
⎜
⎟
⎝ 2 ⎠
4x
Almost same
1
≈ 2
Wb
Ids
Ids
≈
UT 26mV
vsat
∝
Lg
Lower and low Id
2
Fmin
≈ 1+ 2
⎛f⎞
2Gp
+ 0.7⎜⎜ ⎟⎟
gm
⎝ fT ⎠
(larger gm)
2x
V*fT
2004. 03. 02
100VGHz
TITech A. Matsuzawa
2
⎛f ⎞
Gp
≈ 1+ 2
+ 0.25⎜⎜ ⎟⎟
2gm
⎝ fT ⎠
200VGHz
7
MOS vs SiGe-Bip
MOS
Same
SiGe-Bip
Rg,Rb
Much better
1/f noise
Mismatch
mV ≈
Tox(nm)
LW (um)
Better
(SiGe-BiCMOS)
Cost
Low gm or larger current
Voltage lowering
Geometry dependence
Low performance and low cost?
2004. 03. 02
High gm or smaller current
Low noise and mismatch
Less geometry dependence
High performance and high cost?
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Feature of CMOS technology
• Pros
–
–
–
–
–
–
–
Can use a switch and a voltage controlled conductance
Smaller distortion
No carrier accumulation
Can use switched capacitor circuits
Can increase fT by scaling
Easy use of complementally circuits
Easy integration with digital circuits
• Cons
–
–
–
–
–
2004. 03. 02
Low gm/Ids
Larger mismatch voltage and 1/f noise
Lower operating voltage with scaling
Difficult to enable impedance matching
Easily affected by substrate
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Principal design for RF CMOS
•
Use small size devices and compensate the accuracy and 1/f
noise degradation.
– Small parasitic capacitance is imperative.
• Smaller capacitance is needed to keep higher cutoff frequency under the
lower gm condition
– Small size results in increase of the mismatch voltage and 1/f noise
• Should be addressed by analog or digital compensation,
not by increase of device size.
•
Keep the voltage swing on ahigh as possible to realize higher SNR
– The noise level is higher and gm is lower than those of bipolar.
•
Use digital technology rather than analog technology
– Performance increase and power and area decrease are promised by
scaling. Analog is not so.
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Scaling Rule: Basic principle of LSI technology
Scaling rule can improve almost all the performances of LSI
Scaling also realizes higher integration and lower LSI cost.
L
tox
W
Scaling
2004. 03. 02
Device/Circuit parameter
Scaling Factor
Device dimensions L, W, Tox
1/S
Doping concentration
S
Voltage
1/S
Field
1
Current
1/S
Gate Delay
1/S
Power dissipation/device
1/S2
TITech A. Matsuzawa
S≈ 2
11
Scaled CMOS technology
Current Scaled CMOS technology is very artistic.
Matsushita’s 0.13um CMOS technology
Gate
SiO2
Seven lattices
Si
100nm
Transistor
2004. 03. 02
Cu Interconnection
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Performance trend of micro-processors
Performance of micro-processors has increased with device scaling.
Operating frequency
21264
IBM
1GHz
Merced
High-end
700MHz
PC
P7
21264
21164
500MHz
400MHz
300MHz
US-3
R14000
P6MMX2
PPC604e
US-2
R12000
P6 P6
21164
PPC750
Embedded
R4400
Pentium MMX R10000
R10000 SA110
P6
V830R
R5000
SH4
s
US
ar
SA110
e
V832
R4300
2y
21164
NEC
200MHz 21064
R4400
Pentium
100MHz
V830 R4300
es
m
i
2t
SH3
R4200
SH3
SuuperSparc
R3900
R3000 V810
SH2
/
1994
1995
1996
1997
1998
1999
2000
2001
2002
(CY)
Year
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TITech A. Matsuzawa
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GHz operation by CMOS
Cutoff frequency of MOS becomes higher along with technology scaling
and now attains over 100GHz.
0.13um
100G
0.18um
0.25um
Frequency (Hz)
50G
20G
fT : CMOS
fT : Bipolar (w/o SiGe)
fT /10 (CMOS )
0.35um
RF circuits
10G
5G
Cellular
Phone
CDMA
fT /60 (CMOS )
5GHz W-LAN
Digital circuits
gm
fT ≡
2πCin
vsat
fTpeak ≈
2πLeff
2G
1G
IEEE 1394
D R/C for HDD
500M
200M
100M
1995
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2000
2005
TITech A. Matsuzawa
Year
14
Vdd and CMOS scaling limits
Lowest analog operating voltage is 1.2V -1.8V.
Thus 0.18um – 0.13um must be a scaling limit for analog.
50 GHz-100 GHz is an available fT in CMOS technology.
Analog
(Upper)
アナログ（上限）
3
Analog
(Lower)
アナログ（下限）
2
1
Digital
(Lower)
デジタル（下限）
0
1
2004. 03. 02
ITRS ‘99
Digital （Upper） Technology
node
デジタル（上限）
テクノロジーノード
Supply voltage (V)
Technology node (0.1um)
4
2
‘00
3
4
5
6
7
‘05
8
TITech A. Matsuzawa
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10
11
12
‘10
13
14
15
15
Difficulty of low voltage analog
Low voltage swing results in low SNR, because noise can’t be scaled.
SNR (dB)
N=2
95.918
100
90
VFS=5V
VFS=3V
14bit
VFS=2V
SNRC ( 1 , 2 , C)
SNR (dB)
SNRC ( 2 , 2 , C)
VFS=1V
80
12bit
SNRC ( 3 , 2 , C)
SNRC ( 5 , 2 , C)
nkT
V =
C
2
n
⎛ CVFS2 ⎞
⎟⎟
SNR(dB) = 10log⎜⎜
⎝ 8nkT ⎠
70
10bit
60
51.938 50
0.1
0.1
0.1
1
1
10
C
10
100
100
100
Capacitance (pF)
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Cost up issue by analog parts
The cost of mixed A/D LSI will increase when using deep sub-micron
device, due to the increase of the cost of non-scalable analog parts.
Large analog may be unacceptable.
Some analog circuits should be replaced by digital circuits
I/O
Analog
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Wafer cost increases 1.3x
（0.35um : 1） for one generation
Digital
0.35um
0.25um
0.18um
0.13um
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.35um
Chip area
2004. 03. 02
0.25um
0.18um
0.13um
Chip cost
TITech A. Matsuzawa
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Minimum noise figure: Fmin
Fmin has been improved , however saturated at 1dB.
Technical points
F
γ
≈1+
α
min
High fT and low gate resistance.
Small current in substrate.
PAD and ESD structure.
8.0
7.0
M2
Imput L1
M1
Ls
Rsub
Fmin (dB)
Output
Cpi
2
⎛ fo ⎞ ⎛ 2
αδ
⎞
⎜⎜
⎟⎟ ⎜ + gm R e q ⎟ +
⎠ κ gm R e q
⎝ fT ⎠ ⎝ κ
6.0
5.0
4.0
3.0
2.0
1.0
0.0
1
0.5
0.35
0.25
0.1
Gate length (μm)
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Substrate effect on NF in MOS
NF in MOS is very low at on a chip measurement,
But becomes very large when packaged!
NFmin@5GHz，0.18um
This is due to the substrate RF power loss
Packaged
On chip
MOS
（Substrate loss shall be added, when packaged）
・Packaged：NFmin=1.6dB
・On chip：NFmin=0.4dB
2004. 03. 02
TITech A. Matsuzawa
E.Morifuji, et al., SSDM98 pp.80-81
19
Mixer
The passive mixer can be realized by CMOS only.
High linearity, no 1/f noise effect, and low power are realized.
Active mixer (same as bipolar)
Larger power
Larger distortion
Larger 1/f noise
High conversion gain
High isolation
Passive mixer (MOS only)
Low power
High linearity
No 1/F noise
No conversion gain
No isolation, Bi-directional
Vin
R
R
L
L
Vo
Lo
Lo
Lo
Vin
Vo
Lo
Lo
Vo
Vo
Lo
Lo
Vin
Vin
2004. 03. 02
TITech A. Matsuzawa
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1/f noise
1/f noise of MOS is larger than that of bipolar.
For the lower 1/f noise, the larger gate area is needed.
S vf Δ f
,
LW f
S vf ∝ Tox2
Nch 0.4um/1.0um
1E-13
W/L=800/0.4
Vdd=3V
Id=1mA
1E-14
1E-15
nMOS
1E-16
1E-17
pMOS
1E-18
1E-19
1E+02
Bipolar
1E+03
1E+04
1E+05
1E+06
1E+07
Input referred noise voltage (V2/Hz)
Input referred noise voltage (V2/Hz)
Nch/Pch 0.4um
1E-13
1E-14
1E-15
L=0.4um
1E-16
1E-17
L=1.0um
1E-18
Bipolar
1E-19
1E+02
1E+03
1E+04
1E+05
1E+06
1E+07
Frequency (Hz)
Frequency (Hz)
2004. 03. 02
nMOS
Vdd=3V
Id=1mA
2
V nf2 =
TITech A. Matsuzawa
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CMOS oscillator circuits
E. Hegazi, ISSCC 2001
Basic
Low power (gm is higher)
Low noise by filtering
Vo
Vo
Vo
L
L
C
C
L
C
C
Vo
Vo
Vo
L
L
Vc
Vc
L
Vc
C
C
Hi-Z at 2fo
Cs
Vb
Lx
Vb
Vb
(a)
2004. 03. 02
Cx
(b)
TITech A. Matsuzawa
(c)
22
Oscillator phase noise progress
Phase noise in CMOS oscillator becomes lower than that of bipolar.
The larger voltage swing in MOS Oscillator realizes lower oscillation phase noise.
(High Q inductance is also very effective to reduce phase noise)
1 1
⋅ 2
2
Vo Q
⎛ fo ⎞
⋅ ⎜⎜ ⎟⎟
⎝ fm ⎠
■Si-bipolar/BiCMOS
-90.0
SSB Phase Noise
[dBc/Hz](@１GHz,10mW,600kHz)
L ( fm ) ∝
◆CMOS
▲SiGe-BiCMOS
-100.0
-110.0
-120.0
-130.0
-140.0
-150.0
1994
2004. 03. 02
1995
1996
TITech A. Matsuzawa
1997
Year
1998
1999
2000
2001
2002
23
Architecture 1
Simpler architecture should be chosen to reduce power, area, and cost.
1) Super Heterodyne
RF IRF
（Larger power, cost）
RF IRF
LNA
1st Mixer
IF SAW
VGA
2nd Mixer
LPF
ADC
To Digital
2) Homodyne (Zero IF)
20 MHz
250 MHz
1-2 GHz
1.2-2.2 GHz
1st Synthesizer
2nd Synthesizer
（Lower power and cost, however... , ）
LNA
Mixer
LPF
VGA
DC offset
Lo leak
1/f noise
ADC
To Digital
1-2 GHz
Synthesizer 1-2 GHz
3) Low IF
Digital processing
(Middle position）
LNA
1-2 GHz
Mixer
BPF
VGA
Mixer
LPF
50 MHz
Synthesizer
2004. 03. 02
ADC
1-2 GHz
TITech A. Matsuzawa
OSC
24
Architecture 2
Analog circuits have been replaced by digital circuits.
Small analog and big digital is a technology direction.
4) Low IF with ΣΔADC
LNA
ΣΔADC
BPF Quantizer
Mixer
1-2 GHz
Digital processing
Mixer
LPF
50 MHz
OSC
1-2 GHz
Synthesizer
5) Digital architecture
LNA
ΣΔADC
Sampled
data LPF
LPF Quantizer
Digital processing
Mixer
LPF
1-2 GHz
Bluetooth receiver
0.13um CMOS
1.5V
OSC
Synthesizer
1-2 GHz
K. Muhammad (TI), et al., ISSCC2004, pp.268
2004. 03. 02
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Technology edge RF CMOS LSI
Many RF CMOS LSIs have been developed for many standards
Wireless LAN, 802.11 a/b/g
0.25um, 2.5V, 23mm2, 5GHz
Discrete-time Bluetooth
0.13um, 1.5V, 2.4GHz
M. Zargari (Atheros), et al., ISSCC 2004, pp.96
2004. 03. 02
K. Muhammad (TI), et al., ISSCC2004, pp.268
TITech A. Matsuzawa
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Advantage of SiGe Bi-CMOS
SiGe Bip has a great advantage in power consumption
Alcatel1)
Process
CMOS
0.25um
Oki
CMOS
0.35um
Broadcom Conexant Mitsubishi
CMOS
0.35um
SiGe-BiCMOS Si-BiCMOS
0.5um
0.5um
40.1mm2
18.0mm2
Rx_Sens.
-80dBm
-77dBm
-80dBm
-78dBm
-80dBm
Tx_Power
+2dBm
+2.5dBm
+5dBm
+2dBm
0dBm
Rx
50mA
47mA
46mA
12mA
34.4mA
Tx
70mA
66mA
47mA
16.4mA
44.0mA
2.5V
2.7-3.3V
3V(?)
1.8-3.6V
2.7-3.3V
Chip sizeﾞ
Id
Vdd
2004. 03. 02
17.0mm2
TITech A. Matsuzawa
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Potential and limitation of RF CMOS
• Potential
– RF CMOS are going to be a major in the wireless products.
– SiGe Bi-CMOS technology will be used for only extremely low
noise and low power RF products.
– 60GHz or 100GHz CMOS circuits has already developed.
• Limitation
– For low noise and low power characteristics in RF circuit, SiGe
bipolar technology must be better than CMOS.
– High power PA will not be integrated on scaled CMOS chip, due to
low efficiency and needs low voltage operation.
– Use of further advanced technology beyond 90nm would be limited.
This is because low analog operating voltage of less than 0.9V and
chip and development cost increase.
2004. 03. 02
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Expectation for new passive devices
This would sound inconsistent with RF CMOS technology
RF CMOS technology is going to reducing analog and passive
components.
•
However, passives are still important
– High Q inductance
• VCO: reduce power and phase noise
• LNA: reduce power and noise figure
– Tunable inductor
• Multi frequency, yet single inductance.
• Reconfigurable RF circuits
– RF band pass filter
– RF switches
• TX/RX
• Select frequency bands to address multi-standards
• Reconfigurable RF circuits
– On chip solid reference Oscillator
2004. 03. 02
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Inductor
Q of inductor determines almost all the performance of RF
oscillator. Q is conventionally less than 10.
Noise:
Vo
Vo
L
Inductor
Vc
C
L
1
Sφ ∝ 2
Q
C
Current
1
I∝
Q
Vb
RF-VCO
RF-CMOS LSI
2004. 03. 02
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30
RF application of flip chip technology
High performance RF circuit has been realized by using the flip chip technology.
Qmax=63 @9.2GHz
W.P.Donnay, et al., ISSCC 2000, WA 19.1
2004. 03. 02
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Variable Inductor
Sliding plate can vary inductance by 50%.
Wide tunable range VCO (2.4GHz to 5.1GHz) has been realized.
h=10μm
Sliding
Conductor plate
x
20μm
4μm
2004. 03. 02
TITech. Masu Lab.
50%
450μm
2.4GHz to 5.1GHz
TITech A. Matsuzawa
32
RF MEMS switch
Mechanical low-loss integrated switch enables;
Select or change inductance and capacitance
Select signals and circuits;
As a result, enables reconfigurable RF circuits
J. DeNatale, ISSCC 2004, pp. 310
2004. 03. 02
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Micromechanical-Disc Reference Oscillator
MEMS technology will realize an on-chip solid reference oscillator
Fo=61MHz
Q=48,000
-145dBc/Hz far-end
-115dBc/Hz @ 1KHz
Yu-Wei Lin, et al., ISSCC 2004, pp. 322
2004. 03. 02
TITech A. Matsuzawa
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Multi-standard issue
Reconfigurable RF circuit is strongly needed for solving multi-standard issue.
Multi-standards and multi chips
Future cellular phone needs
11 wireless standard!!
IMT-2000
RF
IMT-2000
BB
Current
GSM
RF
GSM
BB
Bluetooth
RF
Bluetoth
BB
MCU
GPS
RF
GPS
BB
Power
Unification
Future
Reconfigurable
RF
DSP
Yrjo Neuvo, ISSCC 2004, pp.32
Unified wireless system
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Summary
• RF-CMOS technology
– Becomes major
•
•
•
•
Performance increase and full system integration due to scaling
Development of suitable circuits and architecture
Small analog and large digital is a right way
Low cost and huge supply capacity
– However, some issues
• For low power and now noise, SiGe Bi-CMOS is better
• Limited use of further scaled CMOS beyond 90nm
• Expectation of new passive device
– Great demand for reconfigurable RF circuits:
• Switches for the reconfigurability
• On chip RF filter and Oscillator
• High quality and tunable inductance
2004. 03. 02
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36