Control Design of PWM Converters:
The User Friendly Approach
Prof. Sam Ben-Yaakov
Email: sby@ee.bgu.ac.il;
Web: http://www.ee.bgu.ac.il/~pel/
Seminar material download: PET06
Power Electronics Technologies Conference
Long Beach CA, October 2006
 All rights reserved. Duplication or copying is not permitted
without written permission by author
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[2]
Motivation
Most switch mode systems need to operated
in closed loop
Performance largely dependent on the Compensator
(feedback) design
Loop control design is conceived as “black magic”
OR requiring tedious analytical derivations
Digital control is becoming relevant
1
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[3]
Objective
To present a user friendly version of control
loop design including both analog and digital
control
Based on:
Intuition
Simulation
Simple calculations
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[4]
Outline
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Basics of feedback theory and graphical representation
Relationship between LoopGain and dynamic response
PWM converters as feedback systems
Voltage Mode (VM) control
Current Mode (dual loop) control
Simulation tools
Average models
Analog compensator networks
Digital control
Q&A
2
[5]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
1. Basics of feedback theory and graphical
representation
[6]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Block diagram of a feedback systems
(one loop)
Sε
Sin +
- S
f
A OL
Sout
β
A CL =
So
Sin β⋅ A
So
A OL
=
Sin 1 + β ⋅ A OL
=
OL >>1
1
β
LG ≡ β A OL
So
Sin β⋅ A
= A OL
OL << 1
3
[7]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Block Diagram
Sin
Sε
+
H1
P
H2
K
Sout
- S
f
n
i
1111
=
PPPP
KKKK ffff
PPPP1111 HHHH G
HHHH HHHH L
oooo
SSSS SSSS
L
C
AAAA
=
+
1
2
142
4
3
(((( ))))
[8]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Effect of Feedback
Sin
Sε
+
Sout
P
- S
f
H2
A CL =
So
P
=
Sin 1 + H2 P K
123
K
ACL
=
LG( f )>>1
1
H2 K
LG(f )
4
[9]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PWM Converter
βe
βm
[10]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Block diagram concepts
Sε
+
H2
H1
P
+
+
Sout
A CL =
- S
f
K
So
H1 P
=
S in 1 + H 1 P K
123
LG ( f )
Power
Vin
Vo
Power
stage
C
d D
MOD
βm
ve Ve
βe
vo
R1
R3
+
-
Sin
Vin
Vref
A CL
LG ( f ) >> 1
=
1
K
R2
5
[11]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Audio susceptibility
Sin
Sε
+
Vin
H2
H1
P
+
+
Sout
- S
f
K
Vin
Sout
+
H2
- S
f
So
H2
=
Vin 1 + LG
H1
P
K
[12]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Sin
+
Sε
H1
P
S out
- S
f
K
S′in +
S′ε
Sout
P
- S′
f
H1
A CL =
Sout
H1 P
1
=
→
Sin
1 + k H1 P
k
K
≠
But loop gains are equal:
A′CL =
Sout
P
1
=
→
S′in
1 + H1 P
H1 k
LG(f ) = H1 K P
6
[13]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Block diagram division
S′in +
B
S′ε
- S′
f
A
P
H1
Sout
K
LG(f ) = A B
A – known (power stage + divider)
B – unknown (have to be designed)
[14]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
A [ dB]
Graphical representation of BA
conventional method
A
AB [ dB]
f [Hz ]
AB
B [dB ]
B
f [Hz ]
f1
f2
f1
f2
f [Hz ]
f3
f3
Tedious – need to re-plot BA
Analysis (not design) oriented
Requires iterations
7
[15]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Graphical Representation of BA
A [dB ]
A
40dB
− 20 dB / dec
20log A − 20log
1
= 20log(BA)
B
20logA = 20log
1
⇒ B⋅ A = 1
B
BA = 1
1
B
LG( f ) = BA
20dB
A
B
>1
BA < 1
fo [Hz ]
fo = 1kHz
10 kHz
[16]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Stability of Feedback System
H(s) =
bm sm + bm−1sm−1 + ... + 1
an sn + an−1sn−1 + ... + 1
jω
σ
− Zero
− Pole
α
RHP solutions include the term sin(ωt) e αt
8
[17]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Stability Criterion
A CL =
H1 K
1 + LG(f )
The system is unstable if {1+LG(f)} has roots
in the right half of the complex plane.
Nyquist criterion is a test for location of
{1+LG(f)} roots.
Nyquist criterion is normally translated into
the Bode plane (frequency domain)
[18]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Nyquist
Im[LG(f )]
unit circle
-1
Φm
f=0
Re[LG(f )]
|LG|
Stable
9
[19]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Nyquist
Im[LG(f )]
Φm
unit circle
-1
f=0
Re[LG(f )]
Oscillatory
[20]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Nyquist
Im[LG(f )]
Φm
unit circle
-1
f=0
Re[LG(f )]
Phase Lead
Φm
Unstable
Phase Lag
The culprit: Phase Lag
Phase Lead in LG can help stabilize a system
10
[21]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Bode plane
BA
BA = 1
φo
ϕm
ϕm = ϕ|BA|=1 − (−180o ) = ϕ|BA|=1 + 180o
[22]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Bode plane
BA
BA = 1
φo
ϕm
ϕm = ϕ|BA|=1 − (−180o ) = ϕ|BA|=1 + 180o
11
[23]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Minimum Phase Systems
no Right Half Plane Zero (RHPZ)
A [dB]
− 20db / dec
− 40db / dec
f1
f2
f [Hz ]
phase
f [Hz ]
0
− 45
o
− 90o
− 135 o
− 180 o
[24]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Rate of closure (ROC)
(minimum phase systems)
BA dB
+ 20 db
− 20 db
dec
− 40 db
dec
− 20 db
dec
dec

f 
f 
f
 1 + j  ⋅  1 + j  ⋅  1 + j  ⋅ ⋅ ⋅ ⋅ ⋅
f
f
f
k
1 
2  
3 
BA = 
⋅ ⋅⋅ =


f 
f 
f
f
 1 + j  ⋅  1 + j  ⋅  1 + j  ⋅ ⋅ ⋅ ⋅ ⋅
1+ j 

f1  
f2  
f3 
fp 


12
[25]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Application of the 1/B curve
Rate of closure
dB
rate of closure
A
− 20 dB / dec
1
B
− 40 dB / dec
f1
f [Hz ]
f2
Rate of closure of BA is the difference
between the A and B slopes
No need to re-plot BA
Design oriented approach
[26]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Stability Criterion
0 db dec
A db
s
− 20 db dec
u
s
+ 20 db dec 0 db
u
dec
− 20 db dec s
1
B
− 40 db dec
− 40 db dec
− 60 db dec
s
f
db
If rate of closure − 20 db dec system is stable
13
[27]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Phase Margin Examples
A
dB
20 dB / dec
20 dB / dec
1
B
ϕ m = 90 o
ϕ m = 90 o 0 dB / dec
0 dB / dec
ϕ m = 45 o
− 20 dB / dec
ϕ m = 45 o
− 40 dB / dec
− 20 dB / dec
ϕ m = 90 o
− 20 dB / dec
ϕ m = 45 o
− 60 dB / dec
f
[28]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Phase Margin Calculation
A[dB]
p
1
B
− 20 dB / dec
− 40 dB / dec
p
z − 20 dB / dec
p
p
− 40 dB / dec
z
f [Hz ]
fO
For minimum phase systems history is not important
14
[29]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Approximate Phase Margin Calculation
A[dB]
p
1
B
− 20 dB / dec
− 40 dB / dec
p
z − 20 dB / dec
p − 40 dB / dec
f [Hz]
z
p
Phase lag in A
fO
Phase lead in B
Get the accurate phase at intersection by simulation
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[30]
Design Steps
A
| BA |
1/B
Draw A
Select cross point of BA (<< than fs/2, for PWM)
Select B shape
15
[31]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Stability of a Source-Load System
Front
End
Converter
ZS
POL
ZL
POL
BUS
POL
ZL → negative resistance
[32]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
System stability
ZS
Vex
V
O
IO
Vex +
-
1
ZS
Z
L
V
O
LoopGain =
Z
IO
L
1
ZL
ZS
Convenient way to examine the LG stability is the Nyquist
stability test
16
[33]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
2. Relationship between Loop Gain
and dynamic response
[34]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Response in Closed Loop
Sin
S
ε
H1
A
Sout
Sf
K
1
Desired : ACL =
K
1
What we get : ACL = ⋅
K s2
ω02
ACL =
1
+
s
ω0 Q
1
1
⋅
for ϕm ≥ 50o
K s +1
ω0
ACL (0 ) =
1
K
for ϕm ≤ 50o
+1
For small ϕm, ACL behaves
as a second order system
17
[35]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Overshoot and Q in Closed Loop
in Response to step in Sin
Q≅
cosϕ m
for ϕm < 50o
sinϕm
Design target ϕm ≥ 45o
[36]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Load-Step Response
Zo
Sin
S
ε
Sout
A
H1
∆I
Sf
K
∆I
Sout
Zo
A
Sout
Zo
=
∆I
1 + A ⋅ H1 ⋅ K
1424
3
LG
H1
K
Small-signal output impedance
18
[37]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Load-Step Response
Zof
Affected by:
Output impedance
ESR of output
capacitor
Slew rate of inductor
[38]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Output Impedance
(Immunity to load changes)
0
40
0
ZOf
ZO
-100
-40
1.0Hz
1.0KHz
0 db( V(OUT_S)/i(V5))
Frequency
1.0MHz
-200
1.0Hz
1.0KHz
db( V(OUT_S)/ i(V5))
Frequency
1.0MHz
A
v
Zo
Z of = out =
∆io
1+ A
B
{
-50
1/B
-100
1.0Hz
1.0KHz
db(v(out)/V(LG_IN))
db( V(OUT)/ V(LG_OUT))
Frequency
1.0MHz
LG
Buck converter – small signal
19
[39]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Audio-Susceptibility (Line Regulation)
(Immunity to input voltage changes)
Vin
H2
+
Vref
PS
Comp
-
Vout
+
Sf
K
Vout
H2
=
Vin 1 + LG(f )
Large LG reduces susceptibility
[40]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Steady-state (DC) Error
Power
Vin
Vo
Power
stage
d D
MOD
ve Ve
βm
Sε =
R1
R3
+
-
C
βe
vo
Sin
+
Sε
H1
P
Sout
- S
f
Vref
R2
K
Sin
1 + LG
Sε is the offset between the
sampled output and reference
Small DC error for large LG(0)
20
[41]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Dynamic Response
Summary
Systems that have a slope of –20 db/dec are easy to control
Response is largely determined by LG(f)
Desired LG:
LG as large as possible at low frequencies
(small DC errors)
LG of large BW - intersection point of A and 1/B
(quick response, fast recovery, rejection of Vin changes)
Phase margin > 450
(reasonable overshoot)
The culprit: Phase delay in LG
[42]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Nyquist
Im[LG(f )]
Φm
unit circle
-1
f=0
Re[LG(f )]
Φm
Design target ϕm ≥ 45o
21
[43]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
3. PWM converters as feedback systems
Issues:
Stability
Rejection of input voltage variations (audio
susceptibility)
Immunity to load changes
Quick response to reference change - good
tracking.
[44]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PWM converter in closed loop
Power
Vin
Vo
Power
stage
MOD
βm
ve Ve
+
-
d D
R1
R3
C
βe
vo
Vref
R2
Small signal responses
Linearization around operating point
22
[45]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Type of Blocks
Small Signals (Perturbation) Responses
Power
Vin
Vo
Power
stage
MOD
βm
ve Ve
+
-
d D
R1
R3
C
βe
vo
Vref
R2
Power stage is a Switching System (may be non linear)
Feedback is an analog or digital controller
Modulator: mixed mode
Linear control theory based design → small signal response
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[46]
Small-Signals (Perturbation) Responses
Analytical
solutions
Simulation
Injection of sinusoidal perturbation
AC analysis of behavioral average model
This
seminar promotes the simulation approach
23
[47]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Small signal response of the modular
Power
Vin
Vo
Power
stage
βm
Relationship
ve Ve
+
-
MOD
R1
R3
C
d D
vo
βe
Vref
R2
between ve and d (Km =d/ve)
[48]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Ve
Small d
t
D
Zoom
t
D
d
t
d is the AC component of D
24
[49]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Modulator
Vt =
(Vp − Vv )t
Ts
Vt = Ve =
Oscillator
+ Vv
(Vp − Vv )ton
Ts
+ Vv
t on
(V − Vv )
= Don = e
Ts
Vp − Vv
d=
ve
v
= e
Vp − Vv Va
Km =
d
1
=
ve Va
[50]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
THE CONTROL DESIGN PROBLEM
CONTROL
DESIGN
KNOWN
βm
βe
vo
(f ) − Ana log Function βm = d
ve
ve
A → Power Stage ; B → compensator
25
[51]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
4. Voltage mode (one loop) control
[52]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Vin
Block diagram
(power )
Vo , v o
(power )
The power conversion system
Vref
Controller
26
[53]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Buck small-signal frequency response
(CCM)
L
S
D
D
Io i
o
Vo
C
vo
RL
ESR
d
MOD
vex
VD
[54]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Buck frequency response (CCM)
vo
, dB
d
-40dB/dec
3
20
0
1
-20dB/dec
Unstable
-20
2
-40
100
1k
10k
100k
f, Hz
Second order plus zero due to ESR of CO
27
[55]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Vin
d
ve
Dependence on Vin
40
Vin:
5V
10V
15V
0
Magnitude
-40
-80
db(V(a))
0d
Phase
-100d
SEL>>
-200d
10Hz
100Hz
p(V(a))
1.0KHz
10KHz
100KHz
1.0MHz
Frequency
[56]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
d
ve 40
Effect of Load
RL=
10Ω - CCM
50 Ω - DCM
100 Ω - DCM
0
-40
Magnitude
-80
db(V(a))
0d
-100d
Phase
SEL>>
-200d
10Hz
100Hz
p(V(a))
1.0KHz
10KHz
100KHz
1.0MHz
Frequency
28
[57]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Buck Derived Converters
Forward
Half bridge (HB)
Full Bridge (FB)
Simulation is the simplest way to
obtain the transfer functions
[58]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Boost Power Stage
Small signal response
50
Magnitude
0
-50
DB(V(OUT)/V(DON))
0d
Phase
-200d
SEL>>
-400d
10Hz
100Hz
10KHz
p(V(OUT)/V(DON))
Frequency
1.0MHz
RHPZ – non minimum-phase system
29
[59]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
CM Boost
40
0
SEL>>
-40
DB(V(OUT)/V(verror))
0d
-100d
-200d
10Hz
100Hz
10KHz
p(V(OUT)/V(verror))
Frequency
1.0MHz
[60]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Buck-Boost (Flyback) Power Stage
0d
-100d
SEL>>
-200d
p(V(OUT)/V(don))
40
0
-40
10Hz
100Hz
DB(V(OUT)/V(don))
10KHz
1.0MHz
Frequency
RHPZ
– non minimum-phase system
30
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[61]
5. Current Mode (dual loop) control
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[62]
Current Feedback
The
problem of voltage mode control:
Transfer function is second order
Solution: Add current Feedback
System
order is reduced for each state
variable (inner loop) feedback
31
[63]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
The effect of current feedback
Io i
o
L
S
Vin
Vo v
o
C
D
D
RL
N
d
AMP
Vε
MOD
io
1
=
ve N
Ve v
e
For ‘strong’ feedback
LG >> 1 vε → 0
1
io = ve
N
[64]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Transfer function with closed Current Loop
L
S
Vin
Io i
o
Vo v
o
C
D
D
d
RL
N
AMP
Vε
MOD
Ve v
e
ve
N
Co
vo
ve
RL
N
RL
1
2π ⋅ CoRL
First order system !
32
[65]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Current Mode
io
L
vo
S
Co
RL
inner
loop
K
d
AMP
Vε
MOD
ve
outer
loop
AMP
Flat
vref
First order
[66]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
The advantages of current feedback
vo
ve
vo
ve
− 20 db dec
− 40 db dec
− 20 db
Typical power stage
VM
− 40 db dec
dec
Same power stage
(outer loop) with
CM
33
[67]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
7. Peak Current Mode (PCM) control
[68]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PCM Modulator
D
d
Ve , v e
Vo
= f (Don ) is the same !
Vin
34
[69]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Implementation CM Boost
L
Driver
FF
S
Rf
R
Cf
comp
RS
Clock
Error AMP
Vref
Some controllers have amplifiers for sensed current
[70]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
The nature of Subharmonic Oscillations
IL
Ve
The geometric explanation
D<0.5 ∆I2<∆I1
∆I1
∆I2
TS
IL
t
Ve
∆I1
D>0.5 ∆I2>∆I1
∆I2
t
For
D>0.5 need slope compensation
35
[71]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Extra delay in PCM (Ridley)
PCM is a current sampling process
Subject to sampling delay
Delay was derived by Ray Ridley
Important for frequencies above fs/10
Mostly of theoretical importance
[72]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Average Current Mode (ACM)
Block diagram
Vo
PWM mod
Zinv
Z fv
-
+
Z fi
+
Vref
Current sample is filtered first attenuate high frequency (fS)
36
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[73]
PCM and ACM
Both are current feedbacks
Both reduce the order of system
The difference is in BW of the
current feedback loop
Both increase the output impedance
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[74]
Advantages of peak CM (PCM)
∗ Cycle by cycle protection
∗ Better dynamics
Disadvantages
∗ Leading edge spike
∗ Subharmonic oscillations
37
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[75]
6. Simulation tools
General purpose simulators
Dedicated simulators
PC and web based simulators
This seminar promotes PC based general
purpose simulators
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[76]
Why Simulation
•
•
•
Most control design methods apply graphical
representations of transfer functions
One can get the plots from analytical
expressions or by simulation
Simulation is the easiest way to get “A” (the
small signal response of the power stage)
38
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[77]
Computer Simulation of Power Conversion Systems
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[78]
Desired Simulator’s Features
for Power Electronics Systems
• Convergence
• Physical models
• Small signal analysis
• Interfaces
• Run time
• Behavioral models
• Statistical and optimization analysis
• Discrete domain simulation capabilities
39
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[79]
Some Popular Modern Simulators
SPICE Based (Berkeley)
• PSPICE – MicroSim - Orcad - Cadence
• ICAP/4 – Intusoft
• MICROCAP - Spectrum
Others
• PSIM - Powersim
• Simplorer -Ansoft
• PLECS -Plexim
Power IC Models Library
• AEi – Design Automation
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[80]
PSPICE – The Physical Simulator
• Most popular
• SPICE based simulator (Berkley)
• Used extensively for circuit simulation
• Extensive physical models libraries
• Behavioral models (ABM)
• AC analysis
• Statistical analysis
• Optimization tool
• Some PWM models
• MATLAB/Simulink interface
40
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[81]
Working with PSPICE
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[82]
PSPICE Convergence Problems
• Very common in switched circuits simulation
41
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[83]
AEi Power IC Library
• PWM controllers are not included in PSPICE libraries
• AEi’s library supports Power Electronics
150 SPICE Models for Popular Power ICs
Regulators, Controllers, Switchers
FET Drivers
Support for Capture and Schematics
Symbols
Example Applications schematics/simulations
Documentation
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[84]
PSIM -The Switching Circuit Simulator
• Disregards switching instances
• Fast and effective time domain algorithm
• Constant time step approach
• Transient (time domain) based AC analysis
• User friendly intuitive interface
• Generic models: passive, switchers, motors
• Analog Behavior Models library
• Simulink interface
• Interface to magnetics program
• Prone to errors in simulation results
• Simple output graphics utility
42
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[85]
PSIM AC Model
Excitation
source
• Multiple time-domain runs are used to obtain AC
response
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[86]
PLECS – The MATLAB Plug-In
• Power tool-kit for SIMULINK
• Allows the simulation of power stage as integrated
part of MATLAB (SIMULINK) simulation without
introducing extra delays
• Ideal for investigating digital control loops in power
systems
• Only generic models
• Simulink interface for both schematic and
graphics
43
[87]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PLECS Circuit as a Simulink Block
PLECS Circuit
Ground
C2
C: 10e-9
R3
R: 10e3
I
II
Mutual
Ind. 2
C1
C: 22e-6
Am2 A
Llkg
3
I_L2
R1
R: 23
Vm1 V
1
Vout
D1
V_dc
V: 300
Am1 A
2
I_L1
D2
Output
Voltage
Vout
I_L1
4
D
MOSFET1
V Vm2
m
1
Gate
s
Sawtooth PWM
PLECS
Circui t
Gate
Primary
Current
D
0.724 Constant1
5
GateOut1
I_L2
Saturati on
GateOut1
Secondary
Current
Circui t
Ground1
num(s)
-K-
s+2.564e5
Saturation1
Gain
Transfer Fcn
5
Drain
Voltage
Constant
[88]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PSPICE cycle-by-cycle model
Vin Snubber
V(%IN+, %IN-)*100k
PWM
IN- OUTIN+ OUT+
E1 ETABLE
(0,0) (15,15)
4.3105Vdc
secondary
C3
10k
2
out
R14
10
D5
MUR160
1
L1
10n
V6
L2
0.5m
2
1
R7
0.5m
2
10m
IC = 48
C2
0.002m
22u
V4
V7
23
R2
L3
V1 = 0
V2 = 5
D3
MBR360
R3
1
TD = 0
300Vdc
TR = 9.999u
TF = 0.0009u
Vd
gate
PW = 0.1n
0
M3
IRF830
K K1
K_Linear
COUPLING = 1
PER = 10u
0
L1 = L1
L2 = L2
0
R11
10k
eaout
C5
R6
10n
20K
R9
C4
10k
3.9n
ETABLE
R13
OUT- INOUT+ IN+
E2
80
Vref
5Vdc
(4.36,4.36) (9.2,9.2)
EA
R12
V5
V(%IN+, %IN-)*100k
0
0
1.2k
0
• Uses physical level models of “real” devices
44
[89]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PSIM Flyback cycle-by-cycle model
(Time Domain)
Demo
Real time: 3 ms
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[90]
PSIM
DCM cycle-by-cycle simulation results
Rload=220Ω
• Textbook waveforms
45
[91]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PSPICE vs. PSIM Flyback
cycle-by-cycle simulation results
[92]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PSPICE vs. PSIM Flyback
cycle-by-cycle simulation results
4.0A
Primary current
2.0A
0A
-2.0A
4.0A
Secondary current
2.0A
0A
-2.0A
47.8V
Output voltage
47.7V
47.6V
47.5V
2.95
2.96
PSIM
PSPICE
2.97
2.98
2.99
3.00
Time, [ms]
46
[93]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Small Signal (AC) Analysis
(Needed for Control Design)
Two Alternatives:
1. Full switched circuit:
Injection of a sinusoidal perturbations
PSPICE manually
PSIM automatic
2. Average Model
PSPICE AC analysis
(linearization by simulator)
PSIM automatic transient injection
[94]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Small signal response by injection of
sinusoidal perturbations ( time domain)
L
S
D
D
Io i
o
Vo
C
ESR
vo
RL
d
MOD
vex
VD
Transient simulation – any simulator
47
[95]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PSIM Realization (Buck)
[96]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
60
50
40
30
20
10
0
-10
-20
dB
3V
20mV
Boost
PSPICE
PSIM
50.0
[V]
Gain, [dB]
Power-Stage small signal transfer function
By injection of sinusoidal perturbation - PSIM & PSPICE
45.0
100
1K
40K
10K
Phase, [deg]
Vpk-pk: 3V
257µS
20
[mV]
Frequency, [Hz]
0
Sinus excitation
0
Vpk-pk: 20mV
-20
3.61
-50
4.00
5.00
6.00
6.75
Time, [ms]
257µS*1.5kHz*360
-100
0
PSPICE
PSPICE
PSIM
-150
-200
-250
Output voltage
47.5
100
1K
10K
40K
Frequency, [Hz]
48
[97]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
The Behavioral Approach
Average Model of Flyback - PSPICE
out
47.99V
R3
10m
in
0.001
E1
IN+ OUT+
IN- OUTEVALUE
300.0V
{Vin}
47.99V
G1
1
L1
IN- OUTIN+ OUT+
{Lmain}
V4
R4
R2
22u
47.99V
C1
23
GVALUE
2
0V
0V
{Vin*V(d)-V(out)*V(doff)/n}
137.9mV
{I(L1)*V(doff)/n}
0
d
PARAMETERS:
V5
ETABLE
0.01Vac
E2
V2
min(1-V(d),(2*{Lmain*fs}*I(L1)/(V(in)*V(d))-V(d)))
IN+ OUT+
IN- OUT-
doff862.1mV
n=1
Vin = 300V
fs = 100kHz
Lmain = 0.5m
0.1379
0
0
Duty cycle generator
• Average models can be applied to obtain frequency
response – AC analysis (to be discussed later)
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[98]
Signal injection versus Average model
Signal
injection
Applies the switching schematics as is
Takes a long time to run
Noisy at high frequency
Average model
Runs very fast
Need to built a behavioral equivalent
Some topologies/controllers are not easy to
convert to average circuits
49
[99]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
vout
d
Gain, [dB]
PSIM vs. PSPICE AC Comparison
50
40
30
20
10
0
-10
-20
-30
PSPICE
PSIM
100
1k
10k
Frequency, [Hz]
100k
1k
10k
Frequency, [Hz]
100k
Phase, [deg]
0
-50
-100
-150
-200
-250
100
PSPICE
PSIM
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[100]
Behavioral average modeling
of switch mode systems
Applications:
• DC transfer functions
• Transient (large signal, time domain) phenomena
• Small signal (AC, time domain) transfer functions
Not applicable to:
• Switching details, rise and fall times, spikes
• Device characteristics and losses
• Subharmonic oscillations
• Conduction losses can be accounted for
• HF ripple can be estimated
50
[101]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
7. Average Models
The Switched Inductor Model (SIM) Strategy
Identify the switched assembly
Replace the switching part by a continuous
behavioral (analog) equivalent circuit
Leave the analog part as-is
Run the combined circuit on a general purpose
simulator
The modeling methodology presented in this seminar is
highly ‘portable’, independent of simulator
Demonstration by PSPICE Ver. 10.5 (Demo Edition)
[102]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
The switched inductor model
Switched
Assembly
Vin
D
Vo
+
−
Modulator
VE
Control
• The problematic part : Switched Assembly
• Rest of the circuit continuous - SPICE compatible
• The objective : translate the Switched Assembly
into an equivalent circuit which is SPICE
compatible
51
[103]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Average Simulation of PWM Converters
b
t on
d
L
Ib
+
−
IL
Vin
Buck
Vout
d
IL
+
−
RLoad
Cf
IC
L
a
Ib
Vin
c
Vin
+
−
t on
d
Ib
IL
c
L
IC
Cf
IC
Cf
Vout
RLoad
b
Boost
b
c
Vout
RLoad
a
Buck − Boost
[104]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Possible switch modes
L
b
a
b
L
TON
TDCM
c
a
TOFF
c
TON - switch conduction time
TOFF - diode conduction time
TDCM - no current time (in DCM)
52
[105]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
The Switched Inductor Model (SIM) (CCM)
The concept of average signals
Ia
a
L
TON
TOFF
b Ib
c Ic
Ia
Ia
t
Ib
Ib
t
Ic
Ic
t
[106]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Objective : To replace the switched part
by a continuous network
Ia
a
L
TON
TOFF
b Ib
c Ic
⇓
b Ib
Ia
a
?
c Ic
53
[107]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Average current
Ia
TON
L
a
b Ib
Ib =
IL TON
TS
c Ic
IL
I a = IL
= ILDon
Don =
I
Ib
IL
Similarly :
Ic =
IL TOFF
TS
TON
TS
Ib
= ILDoff
TON
TS
[108]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Toward a continuous model
b I b = I L ⋅ D on
I a = IL a
c I c = I L ⋅ D off
⇓
Gb
Ia
a
b
Ib
Ga, Gb,Cc - current
dependent sources
Ga ≡ IL
Ga
G b ≡ IL ⋅ Don
Gc
c
Ic
Gc ≡ IL ⋅ Doff
54
[109]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
IL derivation
dIL V
=
dt L
⇒
d IL
dt
=
V
L
X = X = Average value
VL
IL
IL
VL
IL
VL
V
t
[110]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Average inductor voltage
VL
V(a, b )
V (a,b )
b
L
a
c
V(a, c )
V (a, c )
Ton
Toff
Ts
V L=
V(a, b) ⋅ Ton + V(a, c ) ⋅ Toff
=
TS
= V(a, b) ⋅ Don + V(a, c ) ⋅ Doff
55
[111]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
The Generalized Switched Inductor Model
(GSIM) Model
a
Ga
b
L
c
IL
b
Gb
L
a
EL
Gc
rL
c
Ga = IL
Gb = IL ⋅ Don
Topology independent !
Gc = IL ⋅ Doff
V L = V(a, b) ⋅ Don + V(a, c ) ⋅ Doff
[112]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Example: Implementation in Buck Topology
L
S
b
1. The formal approach
Vin
a
V(a, b)
b
Gb
Vin
Ro
EL
L
Gc
c
Ga = I(L)
Ro
IL
Ga
Co
Co
c
Vo
a
V(a, c )
Gb = I(L) ⋅ Don
rL
Gc = I(L) ⋅ Doff
E L = [ V0 − Vin ] ⋅ Don + [ V0 − 0 ] ⋅ Doff
56
[113]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Implementation in Buck Topology
2. The intuitive approach - by inspection
S
L
Vin
D C
o
Vo
Ro
L
Ein = Vin ⋅ Don
Gb
Gb = IL ⋅ Don V
in
Ein + Vo → VL
IL
Vo
Co
Ein
Ro
Polarity: (voltage and current sources) selected by inspection
[114]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Boost
L
Vin
D
S
Vo
Co
Ro
L
IL ⋅ Doff
Vo
Co
Vin
Ro
Doff ⋅ Vo
• Emulate average voltage on inductor
• Create IL dependent current sources
57
[115]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Making the model SPICE compatible
IL Don
Gb
Ll
IL and DON are time dependent Variables {IL(t), DON (t) }
DON is not an electrical variable
[116]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
In SPICE environment
⇓
Gvalue
V(Don ) ∗ I(Ll )
+
−
Don
Source
Ll
Name of node : " Don "
Don is coded into voltage
58
[117]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Running SPICE simulation
DC (steady state points) - as is
TRAN (time domain) - as is
AC ( small signal) - as is
• Linearization is carried out by simulator !
[118]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Discontinuous Model (DCM)
L
a
IL
IL
TON
b
TOFF
c
Ipk
T'off = Ts − Ton
t
Ton
Toff
D'off =
Toff
Ts
Doff
Ts − TN
= 1− Don
Ts
≠ 1 - Don
59
[119]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
The combined DCM / CCM model
b
L
a
Ga
Gb
b
L
a
c
Gc
c
Ga ≡ IL
Gb ≡
IL Don
Don + Doff
Gc ≡
IL
rL
IL Doff
Don + Doff
VL = V(a, b) Don + V(a, c) Doff

Doff = min(1 − Don ),

 2ILLfs


− Don  
 V(a, b)Don

Prof. S. Ben-Yaakov , Control Design of PWM Converters
[120]
Synchronous Power Stages
(diode replaced by switch)
Only two stated for switched inductor:
open and closed
No third state as in DCM
Use CCM model
60
[121]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Example: Buck Converter
L out
Vin puls
D1
Vo
R esr
RL
Cout
Vin
D
PWM
MOD
Vex
VD on
[122]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
File: Buck_cy_by_cy.OPJ
Cycle by Cycle simulation
of PWM Buck converter
buck_cy_by_cy.sch
Rinductor
{Rinductor}
Vin
{Vin}
+
in
-
VD
0
+-
PW = 5u
PER = 10u
+
-
+
Sbreak-X
S1
-
PARAMETERS:
VIN = 10v
Lout
a
Dbreak
D1
{Lout}
out
PARAMETERS:
LOUT = 75u
COUT = 220u
RLOAD = 10
Cout
{Cout}
RLoad
Resr
{Resr}
{RLoad}
PARAMETERS:
RESR = 0.07
RINDUCTOR = 0.1
PARAMETERS:
FS = 100k
TS = {1/fs}
61
[123]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Power Start-Up at Constant Don
10V
0V
V(out)
DCM to CCM
10A
0A
-10A
0s
2.0ms
4.0ms
6.0ms
-I(Lout)
Time
[124]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Zooming up
500mA
250mA
0A
1.535ms
1.625ms
-I(Lout)
1.750ms
1.862ms
Time
62
[125]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Average model
SIM
R dson
Vin
Rdson b
c
b
Co
rc
a
Ga
Gb
rL a
L
Ro
IL
Co
rc
Gc
L
Ro
EL
c
Vin
Vo
rL
[126]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
File: Buck.OPJ
Average simulation by SIM-Model
of PWM Buck converter
GVALUE
Dbreak
Vin
{Vin}
+
D1
-
1V
Gb
IN+
OUT+
INOUT-
Don
NODESET= 5
a
{Rinductor}
Lout
{Lout}
IC = 0
EVALUE
V(Don)*V(a,b)+V(Doff)*V(a,c)
0
PARAMETERS:
VIN = 10v
VDON = 0.5
Ga
GVALUE
OUT+
IN+
OUTIN-
Cout
{Cout}
RLoad
Resr
{Resr}
I(Lout)
{RLoad}
PARAMETERS:
LOUT = 75u
COUT = 220u
RLOAD = 10
PARAMETERS:
RESR = 0.07
RINDUCTOR = 0.1
Doff
EDoff
- +
+
EL
INOUTIN+
OUT+
Gc
a
Rinductor
GVALUE
c
INOUTIN+
OUT+
V(Doff)*I(Lout)/(V(Don)+V(Doff))
VDon
c
b
+
V(Don)*I(Lout)/(V(Don)+V(Doff))
b
buck.sch
Vexcitation
-
{VDon}
IN+
OUT+
INOUT-
PARAMETERS:
FS = 100k
TS = {1/fs}
etable
0
min(2*abs(I(Lout))*Lout/(Ts*(vin-V(a))*V(Don))-V(Don),1-V(Don))
• Don coded into voltage
• Doff for CCM/DCM
63
[127]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Inductor
Rinductor
{Rinductor}
Lout
{Lout}
EL
IN+
OUT+
INOUT-
EVALUE
V(Don)*V(a,b)+V(Doff)*V(a,c)
[128]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Input side
V(Don)*I(Lout)/(V(Don)+V(Doff))
b
GVALUE
Vin
{Vin}
GVALUE
c
Dbreak
+
-
D1
INOUTIN+
OUT+
INOUTIN+
OUT+
Gc
V(Doff)*I(Lout)/(V(Don)+V(Doff))
Gb
0
64
[129]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Output side
+
NODESET= 5
a
Ga
GVALUE
OUT+
IN+
OUTIN-
Cout
{Cout}
RLoad
Resr
{Resr}
{RLoad}
I(Lout)
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[130]
DC Sweep plus Parametric (on Rload)
65
[131]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Sweeping Rload Constant Don
10V
8V
Diode losses
DCM
6V
CCM
4V
1.0
10
100
1.0K
V(out)
RLoad
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[132]
Transient Analysis –Power Turn-On
66
[133]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Power Start-Up at Constant Don
10V
5V
0V
V(out)
10A
5A
SEL>>
0A
0s
2.0ms
4.0ms
6.0ms
-I(Lout)
Time
[134]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Comparing Cycle-by-Cycle to Average Simulation
766mA
400mA
0A
-268mA
1.625ms
-I(Lout)
1.750ms
1.875ms
Time
67
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[135]
AC Analysis
The Real Strength of Average Simulation
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[136]
Linearization
• The circuit is linearized by simulator (elements,
devices and expressions)
• Numerical linearization !
e.g. a source f(x,y,z) is replaced by:
f ( X + ∆X , Y , Z ) − f ( X , Y , Z )
x
∆X
f ( X, Y + ∆Y, Z) − f ( X, Y, Z)
+
y
∆Y
f ( X, Y, Z + ∆Z) − f ( X, Y, Z)
+
z
∆Z
• Transparent to user
68
[137]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PSpice simulations examples
Buck Average
Buck Cy by Cy
[138]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Boost
a
L main
D1
c
Vin puls
R esr
Vin
Cout
D
PWM
MOD
b
Vo
RL
Vex
VD on
69
[139]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Boost Simulation
SIM-Model under CCM & DCM
for PWM Boost converter
Boost.sch
{Rinductor}
a
Vin_pulse
Vin_DC
b
GVALUE
I(Lmain)
+-
EL
IN+
OUT+
INOUT-
+
IN+
OUT+
INOUT-
+
{Lmain}
Dmain
Dbreak
Rsw
{Rsw}
Gb
INOUTIN+
OUT+
GVALUE
Gc
INOUTIN+
OUT+
GVALUE
out
Cout
{Cout}
RLoad
Resr
{Resr}
V(Don)*I(Lmain)/(V(Don)+V(Doff))
V(Doff)*I(Lmain)/(V(Don)+V(Doff))
Don
EDoff
- +
VDon
Lmain
(V(Don)*V(a,b)+V(Doff)*V(a,c))
0
1V
c
1
EVALUE
Ga
-
{Vin_DC}
Rinductor
Doff
IN+
OUT+
INOUT-
Vexcitation
-
{VDon}
etable
0
PARAMETERS:
VIN_DC = 10v
VDON = 0.5
{RLoad}
PARAMETERS:
LMAIN = 75u
COUT = 220u
RLOAD = 10
PARAMETERS:
RESR = 0.07
RINDUCTOR = 0.1
RSW = 0.1
PARAMETERS:
FS = 100k
TS = {1/fs}
min(2*I(Lmain)*Lmain/(Ts*v(a,b)*V(Don))-V(Don),1-V(Don))
[140]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
100V
ESR of Cout
100mΩ
10 mΩ
1mΩ
1.0V
10mV
V(out)
0d
-200d
SEL>>
-400d
1.0Hz
100Hz
P(V(out))
10KHz
1.0MHz
Frequency
RLoad= 10Ω
70
[141]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
DCM
1.0V
DCM
V(out)
0d
SEL>>
-100d
1.0Hz
P(V(out))
1.0KHz
1.0MHz
Frequency
RLoad = 1000Ohm
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[142]
PSpice simulation example
Boost simulation
71
[143]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Modulators – The Duty Cycle Generators
POWER STAGE
V in
V out
Power
Input
D ON
Duty Cycle
'D'
Generator
V
E
Error Ampl.
VL
IL
Vref
ref
• General representation of a switch mode
DC-DC converter
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[144]
PWM MODULATOR - Voltage Mode
D
V − VM
= K M (voltage mode) = E
Ve
VP − VM
ve
d
=
Ve VP ⋅ VM
72
[145]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Coding
Vo
Vin
+
−
D Modulator
KM
K M (voltage mod e ) =
Control
VE − VM
Vp − VM
D coded into voltage
0 ≤ VD ≤ 1
[146]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Duty Cycle Limiter
• Behavioral dependent source ETABLE
E1
IN+
OUT+
INOUTETABLE
V(%IN+, %IN-)
TABLE = (0.1,0.1) (0.9,0.9)
Out
0.9
0.1
0.1
0.9
In
73
[147]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Average Current Mode
Vo
Vin
+
−
D Modulator VE
Control
KM
• VE is a function of Vo and IL
• ‘Control’ is the original analog circuit
• Same modulator as in voltage mode
[148]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Peak Current Mode Control
L=195 µ
D
C=2000 µ
28v
+
Rs
25m Ω
R c =0.012 Ω
R o =11.2 Ω
R1
47.5 Ω
R 2 =2.5k Ω
+
++
3.25
FF
+
V p =0.25v
C f =0.23 µ R f =72.2k Ω
+
2.8v
74
[149]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Current Mode CCM
I(L)
V (Don) + V (Doff )
V ( a, b ) 

TS MC + KS

2L 

V ( Ve ) − KS
EDon =
V(V)
KS = Current Loop Gain
MC = Slope Compensation
TS = Switching Period
L = Inductance of main inductor
|I(L)| = Average inductor current
If your can write an expression, it can be modeled !
[150]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
File: CM-Boost.opj
SIM-Model under CCM & DCM
for Current-Mode PWM Boost converter
Schematic file name: CM-Boost\CM-Boost.sch
Power stage
a
in
lin
Vin_pulse
Ed_c
+-
{lin}
d_c
IN+
OUT+
INOUT-
Vin_DC
Red_c
etable
{Vin_DC}
1k
1/(v(don)+v(doff))
out
v(doff)*i(vl)/(V(Don)+V(Doff))
rind
1m
ELs
+
IN+
OUT+
INOUT-
-
evalue
+
{resr}
resr
0V
-
Gdoff
vl
OUTINOUT+
IN+
cout
gvalue
{cout}
min(abs((2*i(vl)*lin/(ts*v(don)*(v(in)-v(sw))))-v(don)),1-v(don))
Edoff
IN+
OUT+
INOUT-
Verror
+ +
1k
IN+
OUT+
INOUT-
etable
V13
-
Redoff
Edon
PARAMETERS:
KS = 81.25m
TS = 40u
MC = 6250
1
doff
etable
{RL}
v(sw)*v(don)+(v(c)+v(out))*v(doff)+v(in)*(1-v(don)-v(doff))
Vexatation
1.09
DCG - CM
don
sw
1k
Redon
fs*(v(Verror)-ks*i(vl)*v(d_c))/(mc+ks*(v(in)-v(sw))/(2*lin))
rsw
{rsw}
Gsw
OUTINOUT+
IN+
gvalue
i(vl)*v(d_c)
c
d1
Dbreak
RL
Gd
OUTINOUT+
IN+
gvalue
PARAMETERS:
LIN = 195u
RSEN = 0.025
FS = {1/ts}
PARAMETERS:
RSON = 1m
RSW = {rson+rsen}
RL = 11.2
PARAMETERS:
RESR = 0.012
COUT = 2m
VIN_DC = 28
i(vl)*v(d_c)
Doff CCM/DCM
75
[151]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Inductor
a
in
lin
Vin_pulse
{lin}
+-
Vin_DC
{Vin_DC}
rind
1m
ELs
+
IN+
OUT+
INOUT-
-
evalue
27.99V
+
0V
-
vl
0V
v(sw)*v(don)+(v(c)+v(out))*v(doff)+v(in)*(1-v(don)-v(doff))
[152]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Duty Cycle Generator
min(abs((2*i(vl)*lin/(ts*v(don)*(v(in)-v(sw))))-v(don)),1-v(don))
Edoff
IN+
OUT+
INOUT-
doff
etable
Redoff
1k
0V
Edon
IN+
OUT+
INOUT-
etable
don
1k
Redon
fs*(v(Verror)-ks*i(vl)*v(d_c))/(mc+ks*(v(in)-v(sw))/(2*lin))
76
[153]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
50
0
SEL>>
-50
vo
d
vo
ve
db(V(OUT))
db(V(OUT)/ V(DON))
0d
-200d
vo
ve
vo
d
-400d
10Hz
100Hz
10KHz
p(V(OUT)) p(V(OUT)/ V(DON))
Frequency
V(out)/V(Don)
V(out)/V(Verror)
1.0MHz
as normal
lower order
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[154]
PSpice simulation example
CM-Boost
77
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[155]
Models of IC Controllers
Vendors do not supply simulation models of IC
controllers
Large signal controllers’ models are supplied with
some simulators (e.g. PSIM)
Average models ( applicable for small signal
analysis) are available from AEi
It is easy to build your own behavioral average
models (for control)
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[156]
The Power Stage small-signal response
A prerequisite for control design
Can be obtained by analytical derivations/expressions
By Simulation
– On switched model (cycle by Cycle)
– Average models
78
[157]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Feedback Loop Design
of PWM Converters
1.
2.
3.
4.
AOL
Find A(f) of Power
stage
Decide on f0
Choose type of
compensating
network
Calculate feedback
network
Close loop
Bandwith f o
|βA|
1/β
Break frequency not
important,
as low as possible
Make βA as large as possible
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[158]
The Relationship to PID
H(s ) =
=
vcomp
ve
K d ⋅ s2 + K p ⋅ s + K I
s
ω z1,2 =
− Kp ±
K
= Kp + I + s ⋅ K d =
s
=
K d (s + ωz1) ⋅ (s + ω z2 )
KI
s
(Kp )2 − 4KdKI
2K d
79
[159]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
The Relationship to PID
=
K d ⋅ s2 + Kp ⋅ s + K I
s
=
K d (s + ω z1) ⋅ (s + ω z2 )
KI
s
Vcomp
Ve
[dB]
f1
f2
[160]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
The Relationship to PID
Vcomp
Ve
f1
f2
[dB]
1
B
80
[161]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
The Relationship to PID
Vo
d
[dB]
- 40
dB
dec
- 20
Prof. S. Ben-Yaakov , Control Design of PWM Converters
dB
dec
[162]
BW Limitations
(of LG, crossing of A and B)
PWM is a smapled data sysyem .
Nyquist sampling theorem applies
Cross over frequency fo (A, B, LG ) < fs/2
In practice fo < 10 fs/2
81
[163]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
8. Analog compensator networks
[164]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Possible phase compensation schemes
Lag (A)
Ao =
fp =
Rf
Rin
1
2πC f R f
82
[165]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Lag (B)
40
R2
0
out1
0V
R1
V10V
1Vac
0Vdc
1k
C1
100k
E1
10n
0V
IN+ OUT+
IN- OUTEVALUE
V(%IN+, %IN-)*1E6
-40
db(V(out1))
0d
-50d
SEL>>
-100d
10Hz
100Hz
p(-V(out1))
10KHz
1.0MHz
Frequency
[166]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Lag – Lead (B)
1
β
f
A o = A OL (ampl.)
1
fL =
2πC f R f
R
A2 = f
Rin
β
20 db dec
A0
f2
f1
f
A2
83
[167]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Lag-Lead (B)
100
R9
0V
0V
1g
R3
50
C2
out2
10k
R4
V20V
1Vac
0Vdc
1k
10n
0
db(V(out2))
E3
0d
IN+ OUT+
IN- OUTEVALUE
V(%IN+, %IN-)*1E6
-50d
SEL>>
-100d
10Hz
100Hz
p(-V(out2))
10KHz
1.0MHz
Frequency
[168]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Double zero compensation scheme
R3
R1
A OL
C 2 > C3
R1< R 2
1
2 π f ⋅ R 2C3
R3
R2
β
64748 64748 6474
8 64748
1
1
1
1
<
<
<
2π ⋅ R 3C2 2π ⋅ R 2C1 2π ⋅ R1C1 2π ⋅ R 3C3
3 1424
3 14243
14243 1424
1
2 π f ⋅ R 2C3
− 20
dB
dec
1
β
84
[169]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Double Zero (B)
R8
40
1g
C4
100p
C5
V3 0V
1Vac
0Vdc
R5
C3
100k
10n
20
out3
0
E2
0V
10n
0V
R7
db(V(out3))
IN+ OUT+
IN- OUTEVALUE
V(%IN+, %IN-)*1E6
1k
R6
100d
100k
0d
SEL>>
-100d
10Hz
100Hz
p(-V(out3))
0
10KHz
1.0MHz
Frequency
[170]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Double Zero- Alternative
C4
100p
C3
R4
10n
22k
C2
R9
R8
1k
100k
1n
out1
EVALUE
R10
1k
2.5
IN- OUTIN+ OUT+
V2
E2
Don
V(%IN+, %IN-)*1000k
0
85
[171]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Application of Double Zero Compensator
A
-20db/drc
-40db/dec
1/β
Rate of closure
20 db/dec
Phase advance by compensator
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[172]
Voltage Mode Control
Compensator Design Example
VM Regulator
86
[173]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Obtaining the Loop Gain by Simulation
Sin
+
Sε
Sout
PS
H
- S
f
K
LG =
Sf
Sε
[174]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Loop Gain by Simulation
SS
Sin
+
Sε
- S
f
COMP
S′f
+
+
S′ε
PS
H
Sout
K
S′
LG = f
S′ε
87
[175]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Loop Gain by Simulation
Sin +
Sε
-
PS
H
Sf
K
S ′ε
Sout
+ S ′f
+
SS
LG =
S′f
S′ε
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[176]
Loop-Gain
Getting Loop-Gain under closed loop response {A(f)*B(f)}
Vin=0
LG(f) = V1/V2
88
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[177]
Rules for Getting Loop-Gain by Simulation
The relevant analysis is .AC
• Locate the AC source at the output of a low impedance
device (could be real or behavioral)
• Set the AC value to any value (1 V is fine)
• Make sure that there are no other AC sources in the
system
• Check bias point (.OUT file)
• Remember that the classical stability criteria take into
account the phase reversal (1800)
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[178]
PSpice Simulation
VM Regulator
89
[179]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PSIM Demonstration
Large signal
Small signal
Schematic
Schematic
Probe
LoopGain
TF
Probe
Probe
[180]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Peak and Average Current Mode
Vo
IL
IL/Ve flat
inner loop
D
MOD
Ve
Vref
outer loop
Two step design: inner loop and outer loop
90
[181]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
The advantages of current feedback
(PCM or ACM)
 Vo 
 
 Ve 
− 40 db dec
− 20 db dec
 Vo 
 
 Ve 
Typical power stage VM
− 20 db dec
− 40 db dec
Same power stage
(outer loop) with CM
With closed inner-loop
[182]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Inner Loop design
Average Current Mode
µ
Ω
Vac = 1V ; Vc =Constant (operating point) ; KS= 1/20
91
[183]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
out
L1
R1
Co
in
{Lin}
0.1
E1
{Co}
IN- OUTIN+ OUT+
OUT+IN+
OUT- IN-
Inductor
Section
V1
GVALUE
EVALUE
Ro
{Ro}
Resr
G1
.02
0
V(Doff)*V(out)+V(in)*(1-V(Don)-V(Doff))
V(Doff)*I(L1)/(V(Don)+V(Doff))
100Vdc
0
Output
Section
0
0
E4
IN+ OUT+
IN- OUT-
Don
ETABLE
V(Ve)
Duty Cycle
Generator
0
E5
IN+ OUT+
IN- OUT-
Doff
ETABLE
0
Ve
min(2*i(L1)*{Lin}/({Ts}*V(Don)*V(in)+0.1m)-V(Don),1-V(Don))
PARAMETERS:
Lin = 1m
Co = 450u
Ts = 10u
Ro = 610
V3
1Vac
DC = 0.74Vdc
0
[184]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
The response for inner loop design
80
I(L1)/V(Ve)
40
(13.154K,13.335)
0
-40
10Hz
100Hz
DB(I(L1)/(V(Ve)))
1/β
1.0KHz
10KHz
100KHz
1.0MHz
Frequency
F=13kHz; Gain= -13.3db=0.22
92
[185]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
E2
Rin
Rf
Cf
15k
68k
820p
ks
IN+ OUT+
IN- OUTEVALUE
I(L1)/20
Cfh
Ve_out
V2
62p
Ve
0
1Vac
0Vdc
0
Vc
Error
Amplifier
E3
IN+ OUT+
IN- OUTEVALUE
1E6*V(%IN+, %IN-)
0
PARAMETERS:
V3
Lin = 1m
Co = 450u
Ts = 10u
Ro = 610
0Vac
DC = 0.12Vdc
0
• The error amplifier (For KS =1/20)
[186]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
80
I(L1)/V(Ve)
40
(12.761K,13.564)
0
1/β
(2.9126K,10.624)
-40
10Hz
100Hz
DB( I(L1)/V(Ve))
10KHz
-DB( V(VE_OUT)/I(L1))
Frequency
1.0MHz
93
[187]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
40
I(L1)/V(Vc)
0
-40
10Hz
100Hz
DB( I(L1)/V(Vc))
10KHz
Closed inner Loop
1.0MHz
Frequency
[188]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
V in
VO
L
1m H
D
CO
4 70 µ F
RO
1 60 Ω
R in
C fh
Rf
Cf
V E _O U T
VE
D
KM
VC
Vac = 1V ; Vc =Constant (operating point) ; KS= 1/20
94
[189]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
LoopGain
100
(12.467K,72.211m)
0
-100
DB(V(VE_OUT)/V(Ve))
180d
(12.467K,60.107)
90d
SEL>>
0d
10Hz
100Hz
p(V(VE_OUT)/V(Ve))
Phase margin 600
10KHz
1.0MHz
Frequency
[190]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Nyquist Plot
20K
0
-20K
-40K
-20K
0
20K
IMG(-V(VE_OUT)/V(Ve))
R(-V(VE_OUT)/V(Ve))
40K
Imaginary(LG) versus Real(LG)
95
[191]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Nichols Plot
100
Phase margin
0
-100
-200d
-150d
-100d
db(V(VE_OUT)/V(Ve))
p(-V(VE_OUT)/V(Ve))
-50d
-0d
|LG| versus Phase(LG)
[192]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Closed Inner Loop
(Tracing)
40
I(L1)/V(Vc)
0
-40
10Hz
100Hz
DB( I(L1)/V(Vc))
10KHz
1.0MHz
Frequency
96
[193]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
L1
R1
{Lin}
0.1
Closed Inner Loop
in
E1
OUT+ IN+
OUT- INEVALUE
Rect. line
V(Doff)*V(out)+V(in)*(1-V(Don)-V(Doff))
Abs(310*Sin(6.28*50*time))+0.01
Inductor
Section
E2
0
Rin
Rf
15k
68k
Cf
ks
IN+ OUT+
IN- OUT-
820p
IC = -1v
EVALUE
I(L1)/20
Cfh
Ve_out
V2
62p
Ve
0
1Vac
0Vdc
0
Error
Amplifier
Vc
E3
IN+ OUT+
IN- OUTEVALUE
1E6*V(%IN+, %IN-)
0
PARAMETERS:
Lin = 1m
Co = 450u
Ts = 10u
Ro = 610
Abs(2.4*Sin(6.28*50*time)/20)+0.01
• Toward Power factor Correction (open loop)
[194]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Transient Simulation -CCM
4.0A
0A
I(L1)
-4.0A
I(L1)
1.0V
Don
0.5V
0V
V(Don)
1.0V
SEL>>
0V
10ms
20ms
V(Doff)+ V(Don)
Don +Doff
30ms
40ms
50ms
Time
In CCM: Don+Doff = 1
97
[195]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Transient Simulation - CCM/DCM
4.0A
0A
I(L1)
-4.0A
I(L1)
1.0V
Don
0.5V
0V
V(Don)
1.0V
Don +Doff
SEL>>
0V
10ms
20ms
V(Doff)+ V(Don)
30ms
40ms
50ms
Time
After changing Lm to 300µH
[196]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Three Loops Feedback PFC System
(Conventional CCM)
RECTIFIER
Lin
+-
AC
PWM
R2 M
Cout Rload
R3
RS
+ -
R1
Dout
R4
Ref
98
[197]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
UC3854 Based Average Model
POWER STAGE
AC in
rec
sw
i L(t)
Rci
Rm
AC in
Rff1
f1
R
Cff 2
ff1
Rcz
cai
+
Eca -
Gm
E ff
C. ERR. AMP
SQR-DIV-MUL
FF. LPF
Cvf
vaout
D
+
ff3
Vout
Rvf
caout
_ Ccp
C0
Gsw
Ccz
pci
cap
Rff2 f
R0
+
Esw -
ret Rs
lineret
C
Lbst
t
line
Vline
FILTER & LOAD
out
Vout
+
-
Rff
Rvi
_
van
+
vap
+ Vref
Eva -
PWM
Rvd
V. ERR. AMP
[198]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
CCM - Based on UC3854
out
L1
sw
Gsw
{Lin}
line
+
V1
rec
E1
+-
0V
OUTINOUT+
IN+
V_Iac
+
-
V_Iin
{Rac}
Rs
IN+
OUT+
INOUT-
Rm
4k
Rvf
Rcz
620p
vaout
Eva
caout
Ccp
van
Cvf
47n
OUT+
IN+
OUTIN-
Rvd
10k
62p
Evalue
Eca
Gm
INOUTIN+
OUT+
Gvalue
INOUTIN+
OUT+
cap
f1
Cff1
0.1u
vap
1000*V(%IN+, %IN-)
Evalue
Riv
+
Vref
-
7.5V 1Meg
1E6*V(%IN+, %IN-)
E6
I(V_Iac)*(V(vaout)-1)/(pwr(V(f),2))
Rff1
910k
Rvi
511k
180k
Ccz
24k
cai
I(L1)*V(Line)/abs(v(line))
out
Evalue
V(Doff)*V(out)+V(rec)*(1-V(Don)-V(Doff))
Rci
4k
0V
rec
+-
Esw
{Rs}
G3
V4
IC = 390
Racl
ret
INOUTIN+
OUT+
{2*Ro}
Co
{Co}
V(Doff)*I(L1)/(V(Don)+V(Doff))
Evalue
abs(V(line))
gvalue
R18
Ro
{Ro*2}
Gvalue
IN+
OUT+
INOUT-
IN+
OUT+
INOUT-
Don
Doff
EDoff
IN+
OUT+
INOUT-
etable
Etable
Rff2
f
(V(caout)-1.1)/5.4
min(2*I(L1)*{Lin}/({Ts}*v(rec)*V(Don)+0.1m)-V(Don),1-V(Don))
91k
Cff2
Rff3
0.5u
20k
PARAMETERS:
Vrms = 230V
RO = 610
CO = 450uF
TS = 10uF
PARAMETERS:
RS = 0.25
RAC = 910k
Lin = 1m
Av_Model_UC.opj
99
[199]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Voltage Control Loop
out
390.0V
R3
Gsw
{ESR}
OUTINOUT+
IN+
Ro
{Ro}
0V
Gvalue
0V
Output Section
390.0V
Co
{Co}
IC = 390
out
V(Doff)*I(L1)/(V(Don)+V(Doff))
Rvf
Excitation
van
7.614V
V13
Eva
vaout
ba_out
1Vac
0Vdc
Cvf
{Fed_Cap}
Rvd
10k
OUT+
IN+
OUTIN-
7.614V
Error Amplifier and
Compensation Network
Rvi
511k
180k
7.500V
7.492VR2
0V
vap
Evalue
1000*V(%IN+, %IN-)
0V
1Meg
+
Vref
-
7.5V
[200]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Input Voltage Step Response:
115Vrms to 230Vrms
400V
0V
SEL>>
-400V
Input Voltage
v(line)
10A
Input Current
0A
-10A
400ms
450ms
i(V_Iin)
500ms
550ms
600ms
650ms
700ms
Time
Pout=250W, Slew Rate=160V/mS
100
[201]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Input Voltage Step Response:
115Vrms to 230Vrms
400V
0V
Input Voltage
-400V
v(line)
425.0V
Output Voltage
412.5V
400.0V
SEL>>
375.0V
400ms
450ms
v(out)
500ms
550ms
600ms
650ms
700ms
Time
Pout=250W, Slew Rate=160V/mS
[202]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Current Loop Gain at Different Input Voltages
200
0
SEL>>
-200
db(v(ba_out)/v(Don))
0d
-100d
-200d
10Hz
100Hz
1.0KHz
10KHz
p(v(ba_out)/v(Don))-180
Frequency
100KHz
1.0MHz
Vin=50V, 100V, 200V, 300V
101
[203]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Loop Gain of Voltage Control Loop
0
-100
SEL>>
-200
db(v(ba_out)/v(vaout))
0d
Φm=650
-200d
-400d
100mHz
1.0Hz
10Hz
100Hz
p(v(ba_out)/v(vaout))-180
Frequency
1.0KHz
10KHz
[204]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PSpice simulation
PFC-AC
PFC-TRAN
102
[205]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
CCM Control Concept with no Sensing
of Input Voltage
I in
L
D
IL
Vac
Low Pass
Filter
Ro
Co
SW
Vin
Vo
Doff
KM PWM
I L (av)
Ve
M
E/A
Vref
[206]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Average Model
L1
R1 0.1
in
Out
{Lin}
G1
GVALUE
Vrms*1.414*abs(sin(6.28*50*time))
R6
{res}
C1
OUTINOUT+
IN+
Iin
THD meter
1mF
V(OUT)*V(doff)+V(in)*(1-V(Don)-V(Doff))
IC = 390
i(l1)*(sin(6.28*50*time)/abs(sin(6.28*50*time)))
i(L1)*v(Doff)/(v(don)+v(doff))
0.99
0.99
don
0
Ipk
1-I(L1)*v(k)
doff
0
v(in)*v(don)*{Ts}/{Lin}
min(1-v(don),2*I(L1)/(v(Ipk)+1u)-v(Don))
Out
R3
V(%IN+, %IN-)*100k
14
eao
k
V1
ba_in
1
(14-V(%IN))*14m
770k
E1
ba_out
OUT+
IN+
OUTIN-
1Vac
0Vdc
EVALUE
PARAMETERS:
Lin = 1m
res = {380*380/P}
Ts = {1/100k}
Vrms = 220
R4
C2
V2
+
-
5
10k
3.3u
P = 1kW
0
103
[207]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Input Behavior at Different Line Voltages
Rectified Input Voltage
300V
200V
100V
SEL>>
0V
v(in)
20A
Inductor Current
10A
0A
730ms
740ms
I(L1)
760ms
780ms
800ms
Time
Pout=1kW, Vin=80Vrms, 230Vrms, 265Vrms
[208]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Loop Gain of Current Control Loop
100
0
SEL>>
-100
db(v(ba_out)/v(Don))
100d
0d
Φm=900
-100d
1.0Hz
10Hz
100Hz
1.0KHz
p(v(ba_out)/v(Don))+180
Frequency
10KHz
100KHz
104
[209]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Current Loop Transfer Function
-30
-40
-60
30Hz
iL/vin=const
100Hz
db(i(l1)/v(in))
1.0KHz
10KHz
100KHz
Frequency
[210]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PSpice simulation
PFC_no_sens-AC
PFC_no_sens-TRAN
105
[211]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Conventional Border Line Control Method
L
Vac
D
DRIVER
Cout Rload
R1
Zero
Detector
R
R2
-
QS
Ref
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[212]
MC33261 Based Average Model
106
[213]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
MC33261 Based Average Model
Out
1.414*{Vrms}*abs(sin(6.28*50*time))
L1
in
iload
R1
{Lin}
0.1
PARAMETERS:
0Vdc
Lin = 0.87m
R10
{nom_load}
G1
GVALUE
THD
THD meter
i(l1)*(sin(6.28*50*time)/abs(sin(6.28*50*time)))
Vrms = 220
P = 175W
OUTINOUT+
IN+
Nom_load = {Vo*Vo/P}
C1
{Cout}
V(OUT)*V(doff)+V(in)*(1-V(Don)-V(Doff))
Rsense = 0.1
Cout = 180u
Vo = 400
IC = 400
i(l1)*v(Doff)/(v(don)+v(doff))
1
1
Doff
Don
1-v(Doff)
0
2*i(L1)*{Rsense}*V(in)/(v(Curr_tresh)*v(out))
0
2
Out
Curr_tresh
10n
in
3
I1
0.5m
R2
1.3meg
V(%IN2)*0.62*
(V(%IN1) -2.5)
1.6meg
E1
R6
Q2
2
1
5.7
ea
Q2N2222
C3
0
R4
C2
1.59u
inv
OUT+ IN+
OUT- IN-
1k
Q2N2222
Q1
2.1
R3
Error Amplifier
0
0
EVALUE
V(%IN+, %IN-)*17783
ref
0
V2
10n
+
-
2.5
R5
10k
C5
12k
0.68u
0
[214]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PSpice simulation
PFC_bord-AC
PFC_bord-TRAN
107
[215]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Border Line Control Concept with no
Sensing of Input Voltage
[216]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Principle of Operation
Vin
t
Iin
Ipk(t)
Iav(t)
t
V
Ipk ( t ) = 2Iav ( t ) = in Ton
L
Vin ( t )
= const. if Ton = const.
Iav ( t )
108
[217]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
MC33260 Based Average Model
Io = f(Vout)
E
Don
=
T
on
T +T
on
off
EDoff =
Toff
Ton + Toff
[218]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
MC33260 Based Average Model
Out
L1
in
{Lin}
R1
iload
IC =
0.1
1.4*{Vrms}*abs(sin(6.28*50*time))
0Vdc
THD
THD meter
R10
{nom_load}
G1
GVALUE
OUTINOUT+
IN+
V(OUT)*V(doff)+V(in)*(1-V(Don)-V(Doff))
C1
{Cout}
i(l1)*(sin(6.28*50*time)/abs(sin(6.28*50*time)))
IC = 400
i(l1)*v(Doff)/(v(don)+v(doff))
1
PARAMETERS:
Don
Ton
Lin = 320u
0
CT = 2.7n
Vrms = 220
v(Ton)/(V(Ton)+V(Toff))
v(Vcontrol)*200u*{Cch}/(2*i(V_Io)*i(V_Io)+10n)
P = 80
Nom_load = {Vo*Vo/P}
Rsense = 1
1
Toff
Doff
Cout = 47u
Vo = 400
Cch = {15p+CT}
0
v(Toff)/(V(Ton)+V(Toff))
2*i(L1)*{Lin}/(v(out)-v(in))
Out
R3
1meg
ABM3
TABLE1
R6
Vreg
i(V_Io)
In
Out
0
1.5v
194u
1.5v
200u
0v
300k
Vcontrol
C3
680n
0
R5
1meg
2.6V +
-
V_Io
0
109
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[219]
Combined Stage
(Boost-Flyback)
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[220]
Principle of Operation
ON:
OFF:
• CB serves as output capacitor for Boost Section and as
input voltage source for Flyback section.
110
[221]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Average Model
Boost Inductor Section
R1
in
L1
1
2
{L1}
0.1
310*abs(sin(6.28*50*time))
V(Vc)*V(Doff1)+V(in)*(1-V(Don)-V(Doff1))
Boost Output Section
Flyback Input
Voltage Section
NODESET= 500
+
PARAMETERS:
Vc
L1 = 50u
n=7
L2 = 100u
I(L2)*V(Don)/(V(Don)+V(Doff2))
R4
Ts = {1/100kHz}
C1
1meg
I(L1)*V(Doff1)/(V(Don)+V(Doff1))
50u
IC =
0
out
Flyback Inductor Section
I(L2)*{n}*V(Doff2)/(V(Don)+V(Doff2))
V(Vc)*V(Don)
V(out)*{n}*V(Doff2)
L2
R2
1
2
{L2}
C2
0.01
R3
100u
IC = 50
Load Section
50
0
min((2*I(L1)/(V(pk1)+0.1m)-V(Don)),1-V(Don))
V(in)*V(Don)*v(Ts)/{L1}
1
pk1
Doff1
1
0
E1
0.2/5
Don
Boost Doff Generator
v(out)*5/50
R6
OUT+ IN+
OUT- IN-
0
1k
0
EVALUE
V(%IN+, %IN-)*1e5
R5
min((2*I(L2)/(V(pk2)+0.1m)-V(Don)),1-V(Don))
V(Vc)*V(Don)*{Ts}/{L2}
1
V2
5
Doff2
pk2
330k
0
C3
1u
Flyback Doff Generator
0
Feedback and Don Generator
[222]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
min((2*I(L1)/(V(pk1)+0.1m)-V(Don)),1-V(Don))
V(in)*V(Don)*v(Ts)/{L1}
1
pk1
Doff1
Doff Generator
for Boost Section
0
Boost Doff Generator
min((2*I(L2)/(V(pk2)+0.1m)-V(Don)),1-V(Don))
V(Vc)*V(Don)*{Ts}/{L2}
1
Doff2
Doff Generator for
Flyback Section
pk2
0
Flyback Doff Generator
1
0.2/5
E1
Don
OUT+ IN+
OUT- IN-
0
Error Amplifier
and Don
generator
v(out)*5/50
R6
1k
0
EVALUE
V(%IN+, %IN-)*1e5
R5
V2
5
330k
Voltage
Divider
C3
1u
0
Feedback and Don Generator
111
[223]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Behavior at Different Power Levels
62.5V
Output Voltage
50.0V
37.5V
v(out)
1.0A
Inductor Current
0.5A
SEL>>
0A
671.4ms
680.0ms
I(L1)
690.0ms
700.0ms
710.0ms
721.4ms
Time
Vin=230V, Pout=100W, 50W
[224]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Combined Stage
(SEPIC with Transformer)
D in
LB
LF
Df
C out R load
SW
Vac
n:1
CB
E/A
+ -
PWM
Ref
112
[225]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Principle of Operation
ON:
OFF:
(ILB +ILF)⋅n2
Vout
n
[226]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Average Model
Vc
L1
R1
in
1
I(L2)*V(Don)/(v(doff2)+v(don))
2
R4
0.0001
{Vrms}*1.414*abs(sin(6.28*50*time))
{L1}
0
140u
C1
IC =
1meg
V(in)*(v(Don)+V(Doff1))-(V(out)*{n}+v(Vc))*V(Doff1)
I(L1)*V(Doff1)/(v(doff1)+v(don))
0
out
V(Vc)*V(Don)-V(out)*{n}*max(V(Doff2),V(Doff1))
L2
1
2
R2
C2
{L2}
0.5
0
PARAMETERS:
R3
10m
IC = 19
L1 = 90u
n=6
L2 = 225u
Vrms = 265
Load = 5
Ts = {1/90kHz}
{load}
0
I(L1)*V(Doff1)*{n}/(v(doff1)+v(don))+I(L2)*V(Doff2)*{n}/(v(doff2)+v(don))
V6
1
ba_in
Don
0
0.495/5
E1
ba_out
OUT+ IN+
OUT- IN-
1Vac
0Vdc
EVALUE
0
v(out)*5/19
R6
10k
V(%IN+, %IN-)*1e5
C4
1u
V2
5
R5
900k
0
min((2*I(L1)/(V(pk1)+0.1m)-V(Don)),1-V(Don))
V(in)*V(Don)*{Ts}/{L1}
min((2*I(L2)/(V(pk2)+0.1m)-V(Don)),1-V(Don))
1
V(Vc)*V(Don)*{Ts}/{L2}
1
Doff1
pk1
pk2
doff2
0
0
113
[227]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Behavior at Different Power Levels
500mA
Inductor Current
250mA
0A
I(L1)
25V
Output Voltage
20V
15V
SEL>>
10V
640.0ms
v(out)
650.0ms
660.0ms
670.0ms
679.7ms
Time
Vin=230V, Pout=70W, 50W
[228]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PSpice simulation
PFC_DCM - avg
PFC_DCM - CBC
114
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[229]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[230]
9. Digital Control
Analog/continuous control
LG(s ) = K tKMPS(s )B(s )
115
[231]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Digital/discrete control
1
2NPWM
2NA/D
VA/D
LG = K tKMK A/D e- s∆TPS(s )B(z )
e - s∆T ⇔
1
z
• Sampling and computation delay
• Additional gain – KA/D
[232]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Sampling Issues
ZOH
Time
∆T
116
[233]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
ZOH
fs=10KHz
500Hz
1.5KHz
2.5KHz
[234]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Sampling Delays
TS =
1
fS
D (n)
D (n+1)
Time
A/D computation
sample (n)
output
PWM (n+1)
sample (n+1)
sample (n+2)
(result of sample (n))
Sampling rate = fs
117
[235]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Slow Sampling Rate
TS =
1
fS
D (n)
D (n)
A/D
D (n+1)
Time
output
PWM (n+1)
computation
sample (n+1)
(result of sample (n-1))
sample (n)
Sampling rate =
fs
2
[236]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Compensation network, continuous
R1
C
Ve(t) R2
-
Vc(t)
+
K=
R1
R2
τ = R1C
− KVe (t ) = τ
Differential equation:
Integral equation:
Laplace transform:
Transfer function:
Ve (t )
dV (t ) V (t )
= −C c − c
R2
dt
R1
dVc (t )
+ Vc (t )
dt
− K ∫ Ve (t )dt = τ ∫ dVc (t ) + ∫ Vc (t )dt
−
K
1
Ve (s ) = τVc (s ) + Vc (s )
s
s
Vc (s )
K
=−
Ve (s )
sτ + 1
118
[237]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Discretization rules
Differential equations transforms to difference equations
dV (t )
V [n] − V [n − 1]
⇒
dt
∆T
Integral equations transforms to summations
∫ V (t )dt ⇒ ∆T
n-1
∑ V[k ]
k = -∞
Z-transform is the discrete time dual of the Laplace transform
V (s ) =
∞
∫ V (t )e
∞
− st dt ⇔ V (z ) =
∑ V[k]z −k
k =-∞
-∞
Transfer functions are represented in Z
[238]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
jω
Im[ z ] 1
S plane
Z plane
unstable
stable
σ
stable
Re[ z ]
-1
1
unstable
−1
-1
vo
1
z
=
=
v e z + a 1 + az −1
v o (1 + az −1 ) = v e z −1
v o = v o (n − 1) ⋅ a + v e (n − 1)
Unstable if a>1
119
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[239]
The intuitive meaning of the z operator
s ⇒ derivative operator; z ⇒ Delay operator
vo
z
(z) = 2
vin
z −1
vo
z−1
(z) =
vin
1 − z −2
vo (1− z−2 ) = vin z−1
vo = vo z−2 + vin z−1
vo = vo (n − 2) + vin (n − 1)
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[240]
Continuous to discrete transformation
• Pole-Zero matching
• Zero Order Hold (ZOH)
• Trapezoid (bilinear) transformation
120
[241]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Pole-Zero matching
• Map discrete poles/zeros by
zi = e si∆ T
• For complex s-domain roots
si = ai + jbi → zi = e ai∆ T e jbi∆ T
• Maintain same DC gain
G(s ) s=0 = G(z ) z =1
Vc (s )
K
KP
Z
=
→
Ve (s ) sτ + 1
z − e − ∆T τ
Vc (s )
V (z )
= c
→ P = 1 − e − ∆T τ
Ve (s )|s =0 Ve (z )| z =1
(
)
Vc (z ) K 1 − e − ∆T τ
m
=
=
−
∆T
τ
Ve (z )
z −n
z−e
1


 ai = ; bi = 0 
τ


m, n - constants
[242]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Zero Order Hold (ZOH)
Hold equivalent = sampled area
z −1
s⇔
∆T
Transfer function:

Vc (z )
K ∆T 
1

=
Ve (z ) ∆T + τ  z − τ

∆T + τ



m
=
z
−n



Vc (s )
K
=
Ve (s ) sτ + 1
Vc (z )
K
=
z
−
1
Ve (z )
τ +1
∆T
K ∆T
τ + ∆T
τ
τ + ∆T
121
[243]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Trapezoid (bilinear) transformation
Hold equivalent = sampled area
Vc (s )
K
=
Ve (s ) sτ + 1
Transfer function:
s⇔
2 z −1
∆T z + 1
K ∆T 2
τ + ∆T 2
Vc (z )
K
=
Ve (z ) 2τ z − 1 + 1
∆T z + 1
Vc (z )
K ∆T 2  z + 1 
=


Ve (z ) τ + ∆T 2  z − 1 
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[244]
Comparison of hold types
fs=50KHz
Vc (s )
10
=
Ve (s ) 0.1s + 1
122
[245]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Effects of sampling rate
Hold Type: ZOH
Discretization:
Inherent Phase-lag
[246]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
A/D and PWM Resolution
The Limit Cycle Problem
duty/Vc
Stable output
Oscillatory output
[mV/bit]
123
[247]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
No Limit cycle rules
One bit of the DPWM should change Vo
by less than 1 bit of the A/D
Taking into account the system gains
KPSK t qDPWM < q A/D
Compensator must include integral action
(included in PID)
System must satisfy Nyquist criterion
1 + A(s)B(s) > 0
Stability
1 + A(s)B(s) ≠ 0
Oscillations
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[248]
Digital Compensator Design Methods
Frequency domain based
Pole location in z plane
Time domain design
124
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[249]
Frequency domain design
1. Design a frequency domain controller (Bode,
Nichols, etc.)
2. Refinement: take into account the sampling and
computational delays
3. Translate the analog controller into a Z equivalent
4. Simulate by numerical simulator (e. g. MATLAB)
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[250]
Frequency domain design
References
[1] V. Yousefzadeh, W. Narisi, Z. Popovic, and D.
Maksimovic, “A digitally controlled DC/DC converter
for an RF power amplifier”, IEEE Trans. on PE, Vol.
21, 1, 164-172, 2006.
[2] G. F. Franklin, J. D. Powell, M. L. Workman, Digital
control of dynamic systems, 3rd edition, Prentice Hall,
1998.
[3] B. J. Patella, A. Prodic, A. Zirger, and D. Maksimovic,
“High-frequency digital PWM controller IC for DC-DC
converters”, IEEE Trans. on PE, Vol. 18, 1, 2, 438446, 2003.
125
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[251]
Z Plane Design
Using the MATLAB SISO tool
1.
2.
3.
4.
5.
Define the system structure
Define the Plant response
Define the compensator template
Select the analysis view (Root Locus, Bode, Nichols)
Insert design constraints (gain, BW, PM, settling time,
Natural frequency, etc.)
6. You can use the GUI to change pole/zero locations
(either in S or Z and observe the resulting closed loop
response
• Trial and error procedure
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[252]
MATLAB SISO tool
References
[1] O. Garcia, A. de Castro, A. Soto, J. A. Oliver, J. A.
Cobos, J Cezon, “Digital control for power supply of a
transmitter with variable reference”, IEEE Applied
Power Electronics conference APEC-2006, 14111416, Dallas, 2006.
[2] The Mathworks, Matlab control toolbox user guide,
available at www.mathworks.com.
126
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[253]
Time domain Discrete Controller Design
● Digital compensator operates in the sampled-data domain
● Direct controller design - does not involve errors related to
approximations (s to z)
● When working in the time domain, system attributes such
as bandwidth and phase margin seem artificial
● Relevant parameters are: rise time, overshoot etc.
● Improved performance of the closed loop system
compared to other discrete design approaches
● Does not involve trial and error procedure
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[254]
Time domain Discrete Controller Design
References
[1] G. F. Franklin, J. D. Powell, M. L. Workman, Digital control of
dynamic systems, 3rd edition, Prentice Hall, 1998.
[2] J. R. Ragazzini and G. F. Franklin, Sampled-data control
systems, McGraw-Hill, 1958.
[3] J. G. Truxal, Automatic feedback control systems synthesis,
McGraw-Hill, 1955.
[4] B. Miao, R. Zane, and D. Maksimovic, “Automated Digital
Controller
[5] Design for Switching Converters”, IEEE Power Electronics
Specialists Conference, PESC-2005, 2729-2735, Recife,
2005.
[6]
M.
M. Peretz and S. Ben-Yaakov, Time domain design of
NEW
digital compensators for PWM DC-DC converters, IEEE
Applied Power Electronics conference APEC-2007, In
Press.
127
[255]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Time domain Discrete Controller Design
• Plant transfer function (continuous): A(s)
• S to Z transformation: A(s) -> A(z)
• Defining the desired closed loop response: ACL(s)
• S to Z transformation: ACL(s) -> ACL(z)
• Ideal controller:
A CL (z ) =
A CL (z )
A (z )B (z )
1
→ B (z ) =
1 + A (z )B (z )
1 − A CL (z ) A (z )
[256]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Closed-loop response
45o < ϕm < 90o
2nd order system
1
s2
ωn 2
+
s
+1
ωnQ
Design constraint:
System will have the
characteristic equation
128
[257]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Describing the closed-loop response by
time domain characteristics
Step Response
1.6
2nd order system
Vo (s )
1
=
2
d (s )
s
s
+
ωn2
1.4
1.2
1
ω nQ
+1
0.8
0.6
0.4
0.2
Rise time:
Overshoot
1.8
1.8
tr ≈
⇒ ωn ≈
ωn
tr
π
−
2Q
Mp = e
1
1−
4Q2
0
0
5
10
15
20
25
30
35
Time (sec)
( ) 2
 ln Mp
1+ 
 π
⇒ Q= −
ln Mp
2
π
( )


[258]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Describing the desired ACL in Z
• Second order characteristic equation sets the ACL(z)
denominator (a0, a1, a2)
s2
ωn 2
+
s
ωn Q
+1
2
Z b z + b1z + b 2
→ 0
a 0 z 2 + a1z + a 2
• To derive the complete ACL equation (i. e. numerator)
additional constraints are to be satisfied:
• Stability at infinity (bounded system)
ACL(z)|z=∞ = 0
• Steady state error to step
ACL(z)|z=1 = 1
• Response to ramp (velocity constant) dACL(z)
dz
1
|z=1 K V
=
129
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[259]
Template-oriented controller
•Ideal controller to satisfy the design constraints
ACL (z )
1
B(z )ideal =
1 − A CL (z ) A (z )
This design method suffers from:
• controller implementation on digital platform vary by
design (plant, ACL, etc.)
• High order - too many parameters – long computation
time
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[260]
Template-based controller
● In each computational event, only data points
around the sampling instant are considered
● The controller uses only information that is in the
vicinity of the sampling instant and is blind to all
other information
● The implemented finite difference equation can be
based on a short-term time response of the
system rather than on the full response
130
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[261]
A look at the step response of B(z)ideal
Objective:
• Find a compensator template that will match (or will be
close to) the the ideal response – at least at the first few
samples
• The compensator should have fewer computation cycles
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[262]
The answer - PID controller
PID template: continuous
s2
Vc (s ) ωc 2
=
Ve (s )
+
s
+1
ωc Q
s
PID template: discrete p-z matching
Vc (z ) a + bz −1 + cz −2
=
Ve (z )
z −1 − z −2
Taking into account the sampling delay (A/D)
Vc (z ) a + bz − 1 + cz − 2
=
Ve (z )
1 − z −1
131
[263]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PID controller
Difference Equation (will be implemented on the
digital platform)
Vc [n] = Vc [n - 1] + aVe [n] + bVe [n - 1] + cVe [n - 2]
Only 3 samples!!!
Only 4 computations!!!
[264]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Extracting PID coefficients (a, b, c)
Amplitude
Ideal
PID
132
[265]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PID coefficients extraction procedure
Vc [n] = Vc [n - 1] + aVe [n] + bVe [n - 1] + cVe [n - 2]
n=0
n=1
n=2
Vc [0] = Vc [- 1] + aVe [0] + bVe [- 1] + cVe [- 2]

Vc [1] = Vc [0] + aVe [1] + bVe [0] + cVe [- 1]
V [2] = V [0] + aV [2] + bV [1] + cV [0]
c
e
e
e
 c
[266]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Design example
Vo = 5V Switching frequency=sampling rate= 50KHz
Tr=100u
Mp=10%
A CL (z) =
0.5044 z + 0.4123
z 2 − 1.403z + 0.4956
133
[267]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Amplitude
Plant response
PS(s) =
3.333 ⋅ 108
2
s + 2500 s + 1.333 ⋅ 10
8
ZOH
PS(z) =
0.06548 z + 0.06459
z 2 + 1.908z + 0.96
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[268]
Ideal controller response
B(z) =
0.5044z3 - 1.375 z 2 + 1.271z - 0.3958
0.06548 z3 - 0.1249 z 2 + 0.05945 z
134
[269]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Extracting PID coefficients (a, b, c)
B(z )F =
3.4 − 6.15z −1 + 2.93z −2
1 − z −1
[270]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Closed loop response
St ep Response
1. 4
Ideal
1. 2
Amplitude
1
PID
0. 8
0. 6
0. 4
0. 2
0
0
0. 5
1
1.5
Time (sec)
2
2.5
3
x 10
-3
135
[271]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Closed loop step response - results
Reference is stepped from 5V to 6V
[272]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
PM=40
BW=4KHz
Phase (deg)
Magnitude (dB)
A look at the frequency domain
136
[273]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Experimental
PM=33
BW=3.2KHz
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[274]
Load step
PID coefficients
a=3.4
b=-6.15
c=2.93
Vout
137
[275]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Slower Response
Switching frequency=sampling rate= 50KHz
Vo = 5V
Tr=500u
Mp=0%
No over shoot
[276]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Controller response
Derived PID:
B(z )S =
1.52 − 2.81z −1 + 1.38z −2
1 − z −1
138
[277]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Closed loop
St ep Response
1. 4
1. 2
A mplitude
1
0. 8
0. 6
0. 4
0. 2
0
0
0. 5
1
1.5
Time (sec)
2
2.5
3
x 10
-3
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[278]
Closed loop step response - results
Reference is stepped from 5V to 6V
139
[279]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
A look at the frequency domain
PM=80
BW=800Hz
[280]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Experimental
PM=80
BW=1.5KHz
140
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[281]
Load step
PID coefficients
a=1.52
b=-2.81
c=1.38
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[282]
Comparison to analog design
The analog controller was set to have the same
bandwidth as the digital design
Load step applied: 1A to 1.5A
141
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[283]
Load step - analog (Spice simulation)
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[284]
Load step - analog
142
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[285]
Load step digital
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[286]
Thank you for Your Attention
Thanks to the Israeli Science Foundation for
supporting our research
143
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[287]
10. Q&A
Prof. S. Ben-Yaakov , Control Design of PWM Converters
[288]
Sort Biography of Presenter
Prof. Shmuel (Sam) Ben-Yaakov
BSc degree in Electrical Engineering from the Technion, Haifa Israel, in 1961
MS and PhD degrees in Engineering from the UCLA, in 1967 and 1970
respectively.
Full Professor at the Department of Electrical and Computer Engineering, BenGurion University of the Negev, Beer-Sheva, Israel,
Heads the Power Electronics Group of BG University
Published over 250 scientific and technical papers in leading journals and
conferences
Holds about 20 patents (as an inventor)
Consultant to companies worldwide on design-oriented theoretical issues in
the areas of analog and power electronics as well as on product development.
Founder and CTO of Green Power Technologies Ltd. (http://www.g-p-t.com)
Present research interests include: power electronics aspects of piezoelectric
elements, analog and digital control, power factor correction, lighting
electronics, soft switching and active thermal cooling.
144
[289]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Primary to secondary isolation
The problem :
D
Converter
RO
Filter
VO
Isolation
barrier
[290]
Prof. S. Ben-Yaakov , Control Design of PWM Converters
Alternative
Pin
A
C
Vo
Power
stage
isolation
feedback
-
D
+
feedback
Vo
Power
stage
Vref
+
isolation
Vref
D
D
Vo
Power
stage
D Gain +
feedback
isolation
-
Gain
feedback
+
Vref
B
Vo
Power
stage
isolation
+
-
Vref
145