Galvanic Isolation of a 1394
Node
Burke Henehan
Texas Instruments
bhenehan@ti.com
Can I Teach What You Need to Know in
1/2 Hour?
n NO
n
n
n
NO
Need to Read App Note and Sections
of 1394-1995 & P1394a (in app note)
Will Cover the Most Asked Questions &
Newly Added Information
w When Might I Need Isolation?
w How Does Bus Holder Isolation Work?
w What Signals Do I Need to Initialize?
w Do I need a large Cap to Decouple GNDS?
w How Do I Check Isolation?
The Problem:
n
All PHYs on a single 1394 bus must be
at the same GND potential for speed
signaling (and other thresholds &
levels) to function correctly.
w In the 6-pin cable this is accomplished by
connecting all PHY GNDs together using
the cable GND of the cable power-GND
pair.
w In the 4 pin cable this is done using the
cable shields.
Does a 1394 Std. Require Isolation?
n
n
n
1394-1995 can be construed to
require Isolation. But industry
interpretation is that it is NOT
required.
1394a Explicitly states isolation is NOT
required by the Standard and removes
most mention of it.
The Microsoft/Intel PC99 specification
does NOT require isolation
Does a 1394 Node Require Isolation?
n
A Node MAY require Isolation if it can
be connected to another non-isolated
node that COULD connect its PHY
ground to its chassis (“green wire”)
GND. OR if the second node’s PHY
GND could be connected to another
device that could be connected to
chassis GND; OR if that device could
have its GND connected to another
device’s chassis GND; OR ...
No Galvanic Isolation
P e rsonal C o m p u t e r
P e rsonal C o m p u t e r
o r U .S. Printer
Phy
Phy
Grounded
A C Input
G rounded
A C Inp u t
1 3 9 4 Cable
L o g ic G r o u n d
Figure 1. N o Galvanic Isolation
Potential Ground Loop
nf - Penalties of Ground Loops
n
n
n
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Degradation of data signals on the
cable
EMI from the cable
Ground currents high enough to
damage components in the system
If the potential difference is large
enough, a personal shock hazard.
Node Only Powered by Cable with No
External Connections - No Isolation
Needed
D igital V C R
C a m era
Phy
A C Input
Isolated
P o w er
S u p p ly
Phy
1 3 9 4 C a b le
L o g ic G r o u n d
F i g u r e 3 . L e a f N o d e N o t R e q u i r i n g I s o la tio n
Example: When Might I Need Galvanic
Isolation of the 1394 Bus?
Printronix Cable
1394 Cable
Video Cable
Laptop PC Example Assumptions:
1. No 1394 Galvanic Isolation Used
2. Laptops Use Isolating Transformers
Wall Power
Wall Power
1394 Cable
Actually 3 Possible Distinct GND
Domains
Wall Power
Wall Power
1394 Cable
Now What about Peripherals!
Wall Power
Wall Power
1394 Cable
Fine Until Plug in Peripherals
Printronix Cable
Video Cable
Wall Power
Wall Power
1394 Cable
Ground Domains Will Try to Equalize.
May Get GND Currents in all 3 cables
Printronix Cable
Video Cable
Wall Power
Wall Power
1394 Cable
If Add Isolation to 1394, Solve Isolation
Problem… For THIS Configuration
Printronix Cable
Video Cable
Wall Power
Wall Power
Isolated 1394 (Cable + PHYs)
Even With 1394 Isolation a Problem is
Possible with Legacy Connections
Printronix Cable
Video Cable
Wall Power
Wall Power
Isolated 1394 (Cable + PHYs)
Only if All Connections are Isolated are
GND Currents Prevented
Isolated 1394 (Cables+PHYs)
Isolated Video
Wall Power
Wall Power
Isolated 1394 (Cables + PHYs)
If Isolation is Required, What Must be
Done?
n Cable Power Isolation
n
Cable Power Isolation
w Must be 8->33V relative to PHY GND,
floating relative to chassis GND
n
Cable Shield Termination Isolation
w DC Isolated via capacitive network
n
Signal Line Isolation
w TI Proprietary Bus Holder Isolation
w Other Solutions Available
w 1394-1995 Annex J covered by Apple Patent
Implementation of Isolation Using Bus
Holder Isolation (see app note)
1 3 9 4 H o s t D e s ig n
D C /D C
C o n v e rte r
LLC
D0 ± D7
CTL0,
CTL1
B
W
G
5 V
H o st
P o w er
S u p p ly
R e g u lato r
0 . 0 0 1 mF
Bus
H o ld e r
12 V
12 V
5 V
Phy
1
Bus
H o ld e r
6
5
0 . 0 0 1 mF 9 1 0 mF
SYSCLK
0 . 1 mF
D0 ± D7
C T L 0,
CTL1
4
3
LREQ
2
C a b le P o w e r
T PA +
T PA ±
TPB+
TPB±
C a b le G r o u n d
1 MW
LLC
GND
Phy
GND
9 0 . 0 0 1 mF
Isolation Boundary
F ig u r e 8 . In t e r n a l B u s - H o ld e r I s o la tio n
1 MW
0 . 1 mF
C a b l e S h i e ld
Te r m in a ls 7
and 8
Implementation of Isolation Using Bus
Holder Isolation - GND Domains
1 3 9 4 H o s t D e s ig n
D C /D C
C o n v e rte r
LLC
D0 ± D7
CTL0,
CTL1
B
W
G
5 V
H o st
P o w er
S u p p ly
R e g u la to r
0 . 0 0 1 mF
Bus
H o ld e r
12 V
12 V
5 V
Phy
1
Bus
H o ld e r
6
5
0 . 0 0 1 mF 9 1 0 mF
SYSCLK
0 . 1 mF
D0 ± D7
CTL0,
CTL1
4
3
LREQ
2
C a b le P o w e r
T PA +
T PA ±
TPB+
TPB±
C a b le G r o u n d
1 MW
LLC
GND
Phy
GND
9 0 . 0 0 1 mF
Is o la tio n B o u n d a r y
F ig u r e 8 . In t e r n a l B u s - H o ld e r I s o la tio n
1 MW
0 . 1 mF
C a b l e S h i e ld
Te r m in a ls 7
and 8
Bus Holder Functionality
Local GND relative
to reference GND = 30V
Local GND relative
to reference GND = 20V
Difference between GNDs is 30-20 = 10V
Voltage Level = 30V
Logic Level = Low
Signal Level
Time->
Voltage Level = 20V
Logic Level = Low
Signal Level
Time->
Isolation Boundary
Reference GND = 0.0 V
No Bus Holders
Local GND relative
to reference GND = 30V
Voltage Level = 33V
Logic Level = High
Signal Level
Time->
Local GND relative
to reference GND = 20V
Voltage Level = 23V->20V
Logic Level = High to Low
Signal Level
Time->
Isolation Boundary
Reference GND = 0.0 V
With Bus Holders
Local GND relative
to reference GND = 30V
Voltage Level = 33V
Logic Level = High
Signal Level
Time->
Local GND relative
to reference GND = 20V
Voltage Level = 23V
Logic Level = Captured High
Signal Level
Time->
Isolation Boundary
Reference GND = 0.0 V
Initialization of Capacitive Isolation
After Power-Up, GND Bounce, etc
Local GND relative
to reference GND = 30V
Local GND relative
to reference GND = 20V
Voltage Level = 30V Voltage Level = 23V
Logic Level = High
Logic Level = low
Signal Level
Time->
Signal Level
Time->
Isolation Boundary
Reference GND = 0.0 V
Assume “Left” Side Begins by Driving
a 0 (low), Bit Propogated is Wrong!
Local GND relative
to reference GND = 30V
Voltage Level = 30V
Logic Level = low
Signal Level
Time->
Local GND relative
to reference GND = 20V
Voltage Level = 23V
Logic Level = High
Signal Level
Time->
Isolation Boundary
Reference GND = 0.0 V
Assume “Left” Side Then Drives a 1
(High), Interface Now Synchronized
Local GND relative
to reference GND = 30V
Voltage Level = 33V
Logic Level = High
Signal Level
Time->
Local GND relative
to reference GND = 20V
Voltage Level = 23.6V
Logic Level = High
Signal Level
Time->
Isolation Boundary
Reference GND = 0.0 V
Assume “Left” Side Then Drives a 0
(Low)
Local GND relative
Local GND relative
to reference GND = 30V
to reference GND = 20V
Voltage Level = 30V
Logic Level = Low
Signal Level
Time->
Voltage Level = 23.6V->20.0V
Logic Level = Low
Signal Level
Time->
Isolation Boundary
Reference GND = 0.0 V
Oscillating Signal Driven to 5V tolerant
Device, Initial State out of Sync
Local GND relative
to reference GND = 30V
Voltage Level = 30V
Logic Level = low
Signal Level
Local GND relative
to reference GND = 20V
Voltage Level = 23.V
Logic Level = High
+5V
Signal Level
Time->
Threshold High
Threshold Low
Local GND Level Time->
Isolation Boundary
Reference GND = 0.0 V
Now Left Side Drives Oscillating Signal
Which Never Crosses Low Threshold
Local GND relative
to reference GND = 30V
Voltage Level = 30V
Logic Level = low
Signal Level
Local GND relative
to reference GND = 20V
Voltage Level = 23.V
Logic Level = High
+5V
Signal Level
Time->
Threshold High
Threshold Low
Local GND Level Time->
Isolation Boundary
Reference GND = 0.0 V
So What Signals do I Need to Initialize?
n
ALL OF THEM
w Every Signal must have HW that initializes
both sides of the isolation barrier to the
same state upon:
w Powerup
w Command from the Microprocessor (Link) side
of the PHY-Link Interface (in case of wrong
state induced during normal operation)
How May Initialization Be Done?
n
n
n
1394a Link and Phy
External Buffers on Each Side of
Isolation Barrier (to drive a state)
Opto-isolators (active drivers to
establish states)
w Currently there are no known optoisolators fast enough and with low
enough latency to operate on the data,
control, SCLK, or LREQ signals
n
Etc.
1394a PHY-Link Interface Initialization
n
n
When SCLK is valid the PHY drives Data
& CTL low for 7 clocks while the link
drives Data, CTL, & LREQ low for 1
clock then makes them high
impedance
On the 8th Cycle the PHY drives
Receive on CTL & Data Prefix on Data
External Bus Holder, Non-1394a PHYLink Interface Initialization
LVCH245
Output_Enable
Output_Enable
Direction
Direction
LinkIF_RESET*
LVCH245
1394
PHY
1394
Link
TIL191B
PHYIF_RESET*
Internal Bus Holder, No 1394a PHYLink Interface Initialization
LVCH244
Output_Enable
Output_Enable
LinkIF_RESET*
LVCH244
PHYIF_RESET*
1394
PHY
1394
Link
TIL191B
What Happens when plug top node
into bottom network?
0.0 V
5.0 V
0.0 V
Wall Power
1394 Cable
20.0 V
Wall Power
0.0 V
Wall Power
0.0 V
Wall Power
1394 Cables
0.0 V
Wall Power
Implementing Isolated Nodes
n
n
Putting in isolation adds unknowns to
board debug
Build Enough Boards to:
w Build the first set of nodes with the
isolation shorted out (replace caps with 0
Ohm resistors) to get 1394 working
w Keep “known good set”(or give to SW
team)
w Build up Isolated boards one step at a
time
n
Implementing Isolated Nodes Continued
Take Task in Steps
Take Task in Steps
w Isolate signals, but leave all GND domains
the same (install signal isolation caps,
leave GND isolation caps shorted)
w After this functions install GND caps
w Offset floating domain to verify isolated
n
n
Need access to both sides of isolated
interface
Be Aware of Different GND Domains!
nf Advantages of Bus Holder Isolation
EXAMPLE COMPARISON FOR 400–Mbits/s NODE (DATA, CTL, LREQ, SYSCLK)
PARAMETERS
ANNEX J METHOD
TI METHOD
TI BUS–HOLDER
BENEFITS
External capacitors
22
12
Reduced PWB area
Reduced complexity
Reduced cost
External resistors
76
2
Reduced PWB area
Reduced power
Reduced complexity
Reduced cost
Voltage swing
VDD/2
Rail to rail
Better noise margin
Digital differentiaters on
Required
None
Reduced complexity
outputs
Reduced cost
Special threshold
Required
None
Reduced complexity
requirements
Reduced cost
Isolation network power
Holds input cells at
Method causes no
Minimal quiescent power
drain
VDD/2
impact
drain
No special input cell
requirement
Reduced cost
Hysteresis on inputs
Requires Schmitt
None
Reduced complexity
triggers on inputs
Reduced cost
References
n
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TI App Note: “Galvanic Isolation of the
IEEE 1394 Serial Bus”- SLLA011 dated
in 1998 - www.ti.com/sc/1394
IEEE 1394-1995 Standard for a High
Performance Serial Bus http://stdsbbs.ieee.org/products/catalog/catalog.html
n
IEEE P1394a Draft 2.0 Standard for a
High Performance Serial Bus
(Supplement)