F
• FEATURES
– single 3.0 V to 3.6 V supply
– 14-Bit DAC Resolution
– 160 MPS Input Data Rate
– 67.5 MHz Reconstruction
Passband @ 160 MPS
– 74 dBc FDR @ 25 MHz
– 2 Interpolation Filter with
High- or Low-Pass
Response
– 73 dB Image Rejection with
0.005 dB Passband Ripple
– “Zero- tuffing” Option for
Enhanced Direct IF
Performance
– Internal 2/4 Clock
Multiplier
– 250 mW Power
Dissipation; 13 mW with
Power-Down Mode
• APPLICATIONS
– Communication Transmit
Channel
– W-CDMA Base stations,
Multicarrier Base stations,
– Direct IF synthesis,
Wideband Cable Systems
– Instrumentation
AD9772A - Functional Block Diagram
1
AD9772 - PRODUCT HIGHLIGHTS
•
•
•
•
•
•
A flexible, low power 2× interpolation filter supporting reconstruction
bandwidths of up to 67.5 MHz can be configured for a low- or highpass response with 73 dB of image rejection for traditional baseband
or direct IF applications.
A “zero-stuffing” option enhances direct IF applications.
A low glitch, fast settling 14-bit DAC provides exceptional dynamic
range for both baseband and direct IF waveform reconstruction
applications.
The AD9772A digital interface, consisting of edge-triggered latches
and a flexible differential or single-ended clock input, can support
input data rates up to 160 MSPS.
On-chip PLL clock multiplier generates all of the internal high-speed
clocks required by the interpolation filter and DAC.
The current output(s) of the AD9772A can easily be configured for
various single-ended or differential circuit topologies. TxDAC+ is a
registered trademark of Analog Devices, Inc.
AD9772A–DC SPECIFICATIONS
• Parameter
Min
Typ
Max
Unit
• RESOLUTION
14
Bits
• DC ACCURACY
– Integral Linearity Error (INL)
±3.5
LSB
– Differential Nonlinearity (DNL)
±2.0
LSB
– Monotonicity (12-Bit) Guaranteed Over Specified Temp. Range
• ANALOG OUTPUT
– Offset Error
–0.025
+0.025 % of FSR
– Gain Error (No Int. Ref.)
–2
±0.5
+2
% of FSR
– Gain Error (With Int. Ref.)
–5
±1.5
+5
% of FSR
– Full-Scale Output Current
2
20
mA
– Output Compliance Range
–1.0
+1.25 V
– Output Resistance
200
kOhm
– Output Capacitance
3
pF
• REFERENCE OUTPUT
– Reference Voltage
1.14
1.20
1.26
V
– Reference Output Current
1
µA
2
AD9772A–Dynamic SPECIFICATIONS
• Parameter
Min
Typ
Max
Unit
• DYNAMIC PERFORMANCE
– Maximum DAC Output Update Rate (fDAC)
400
MSPS
– Output Settling Time (tST) (to 0.025%) 11
ns
– Output Propagation Delay 1 (tPD)
17
ns
– Output Rise Time (10% to 90%)
0.8
ns
– Output Fall Time (10% to 90%)
0.8
ns
– Output Noise (IOUTFS = 20 mA)
50
pA Hz-1/2
• AC LINEARITY—BASEBAND MODE
• Spurious-Free Dynamic Range (SFDR) to Nyquist (fOUT = 0 dBFS)
– fDATA = 65 MSPS; fOUT = 1.01 MHz
82
dBc
– fDATA = 65 MSPS; fOUT = 10.01 MHz 75
dBc
– fDATA = 65 MSPS; fOUT = 25.01 MHz 73
dBc
– fDATA = 160 MSPS; fOUT = 5.02 MHz 82
dBc
– fDATA = 160 MSPS; fOUT = 20.02 MHz 75
dBc
(The difference, in dB, between the rms amplitude of the output signal
and the peak spurious signal over the specified bandwidth)
Digital modes
3
AD9772A Time and Frequency Domain Example
of Low-Pass 2× Digital Interpolation Filter
AD9772A Time and Frequency Domain Example
of High-Pass 2× Digital Interpolation Filter
4
AD9772A
• Zero
stuffing for
Direct IF
conversion
Block Diagram of Internal DAC, 1.2 V
Reference, and Reference Control Circuits
5
Equivalent output circuit
• FEATURES
– 250 MSPS Update Rate
– Low Glitch Impulse
– Complete Composite
Functions
– Internal Voltage Reference
– Single –5.2 V Supply
• APPLICATIONS
– Raster Scan Displays
– Color Graphics
– Automated Test Equipment
– TV Video Reconstruction
GENERAL DESCRIPTION
• The AD9701 is a high speed, 8bit digital-to-analog converter
with fully integrated composite
video functions. High speed ECL
input registers provide
synchronous operation of data
and control functions up to 250
MSPS.
6
AD9701 – Functional Block Diagram
ELECTRICAL CHARACTERISTICS AD9701BQ
• RESOLUTION
• DC ACCURACY
– Differential Linearity (+25°°C)
– Integral Linearity (+25°°C)
– Monotonicity Guaranteed
• INITIAL OFFSET ERROR
– Zero-Scale Offset Error (+25°°C)
– Zero-Scale Offset Drift Coefficient
• DYNAMIC PERFORMANCE
– Update Rate (+25°°C)
– Output Propagation Delay (+25°°C)
– Output Settling Time
Current (+25°°C)
Voltage (+25°°C)
– Output Slew Rate (+25°°C)
– Glitch Impulse (+25°°C)
8 Bits
0.25 LSB
0.25 LSB
0.05 mV
2 µV/°°C
225 MSPS
5 ns
8 ns
12 ns
255 V/µ
µs
60 pV-s
7
ELECTRICAL CHARACTERISTICS AD9701BQ
• DIGITAL INPUTS
– Logic “1” Voltage
– Logic “0” Voltage
– Logic “1” Current
– Logic “0” Current
– Input Capacitance (+25°C)
– Data Setup Time (+25°C)
– Data Hold Time `(+25°C)
• Supply Voltages = –5.2 V;
• RL = 37.5 Ohm;
• FEATURE
– 140 MSPS Guaranteed
Conversion Rate
– 100 MSPS Low Cost Version
Available
– 330 MHz Analog Bandwidth
– 1 V p-p Analog Input Range
– Internal 2.5 V Reference
– Differential or Single-Ended
Clock Input
– 3.3 V/5.0 V Three- State CMOS
Outputs
– Single or Demultiplexed
Output Ports
–1.1 V
–1.5 V
100 mA
15 mA
4 pF
0.1 ns
1.4 ns
– Data Clock Output
Provided
– Low Power: 1.0 W Typical
– 5 V Converter Power
Supply
• APPLICATION
– RGB Graphics Processing
– High Resolution Video
– LCD Monitors and
Projectors
– Micromirror Projectors
– Plasma Display Panels
8
• The AD9483 is a triple 8-bit monolithic analog-to-digital
converter optimized for digitizing RGB graphics signals
from personal computers and workstations. Its 140 MSPS
encode rate capability and full-power analog bandwidth of
330 MHz supports display resolutions of up to 1280 × 1024
at 75 Hz with sufficient input bandwidth to accurately
acquire and digitize each pixel.
• The digital outputs are three-state CMOS outputs.
Separate output power supply pins support interfacing
with 3.3 V or 5 V logic.
• Fabricated in an advanced BiCMOS process, the AD9483
is provided in a space-saving 100-lead MQFP surface
mount plastic package (S-100) and is specified over the
0°C to 85°C temperature range.
AD9483 - Functional Block Diagram
9
AD9483 KS140 – DC Specifications
• Parameter
Min
• RESOLUTION
• DC ACCURACY
– Differential Nonlinearity 25°C
– Integral Nonlinearity 25°C
– No Missing Codes
Guaranteed
– Gain Error 25°C
• ANALOG INPUT
– Input Voltage Range
– Input Offset Voltage 25°C
– Input Resistance (25°C)
– Input Bias Current 25°C
– Analog Bandwidth, Full Power 25°C
Typ
8
Max
Unit
Bits
0.8
0.9
1.25/–1.0 LSB
1.50/–1.50 LSB
±1
±2
% FS
±512
±4
35
17
330
±16
83
36
330
mV p–p
mV
kOhm
µA
MHz
AD9483 KS140 – Dynamic Specifications
• Parameter
Min
Typ
Max
– Maximum Conversion Rate
140
– Minimum Conversion Rate
100
– Signal-to-Noise Ratio (SNR) (Without Harmonics)
– fIN = 19.7 MHz 25°C
45
– fIN = 49.7 MHz 25°C
41
44
– fIN = 69.7 MHz 25°C
44
– Signal-to-Noise Ratio (SINAD) (With Harmonics)
– fIN = 19.7 MHz 25°C
44
– fIN = 49.7 MHz 25°C
40
43
– fIN = 69.7 MHz 25°C
42
– Effective Number of Bits
– fIN = 19.7 MHz 25°C
7.0
– fIN = 49.7 MHz 25°C
6.4
6.8
– fIN = 69.7 MHz 25°C
6.8
Unit
MSPS
MSPS
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
10
AD9843 – Timing – Single Channel Mode
• Pipelined Flash (2 x 4bit Flash ADCs) – latency 4 clock periods -
AD9843 – SNR and SINAD
11
Theory of Operation
• The AD9483 combines Analog Devices’ patented MagAmp bit-per-stage
architecture with flash converter technology to create a high
performance, low power ADC. For ease of use the part includes an on
board reference and input logic that accepts TTL, CMOS or PECL
levels.
• Each of the three analog input signals is buffered by a high speed
differential amplifier and applied to a track-and-hold (T/H) circuit. This
T/H captures the value of the input at the sampling instant and
maintains it for the duration of the conversion. The sampling and
conversion process is initiated by a rising edge on the ENCODE input.
Once the signal is captured by the T/H, the four Most Significant Bits
(MSBs) are sequentially encoded by the MagAmp string. The residue
signal is then encoded by a flash comparator string to generate the four
Least Significant Bits (LSBs). The comparator outputs are decoded and
com-bined into the 8-bit result.
• FEATURES
• APPLICATIONS
– 22-Bit Sigma-Delta ADC
– Biomedical Data
– Dynamic Range of 105 dB (146 Hz Input)
Acquisition
– +- 0.003% Integral Nonlinearity
– ECG Machines
– On-Chip Low-Pass Digital Filter
– EEG Machines
– Cutoff Programmable from 584 Hz to 36.5 Hz – Process Control
– Linear Phase Response
– High Accuracy
– Five Line Serial I/O
Instrumentation
– Twos Complement Coding
– Seismic Systems
– Easy Interface to DSPs and Microcomputers
– Software Control of Filter Cutoff
– +- 5 V Supply
– Low Power Operation: 50 mW
12
General Description
• The AD7716 is a signal processing block for data acquisition
systems. It is capable of processing four channels with band-widths
of up to 584 Hz. Resolution is 22 bits and the usable dynamic range
varies from 111 dB with an input bandwidth of 36.5 Hz to 99 dB with
an input bandwidth of 584 Hz.
• The device consists of four separate A/D converter channels that
are implemented using sigma-delta technology. Sigma-delta ADCs
include on-chip digital filtering and, thus, the system filtering
requirements are eased.
• Three address pins program the device address. This allows a data
acquisition system with up to 32 channels to be set up in a simple
fashion. The output word from the device contains 32 bits of data.
One bit is determined by the state of the DIN1 in-put and may be
used, for example, in an ECG system with an external pacemaker
detect circuit to indicate that the output word is invalid because of
the presence of a pacemaker pulse.
Functional Block Diagram
13
AD7716–SPECIFICATIONS
• fCLKIN = 8 MHz; AVDD = DVDD = +5 V, AVSS = –5 V ; AGND =
DGND = 0 V; VREF = 2.5 V; Filter Cutoff = 146 Hz; Noise
Measurement Bandwidth = 146 Hz
• STATIC PERFORMANCE
B Version
Units
– Resolution
22
Bits
– Integral Linearity Error
0.003
% FSR
– Guaranteed No Missed Codes
– Gain Error
1
%FSR max
– Gain Match Between Channels 0.5
% FSR max
– Offset Error
0.2
% FSR max
– Offset Match Between Channels 0.1
% FSR max
– Noise
11
mV rms max
AD7716–DYNAMIC SPECIFICATIONS
–
–
–
–
–
–
Sampling Rate
fCLKIN/14
570 kHz for fCLKIN = 8 MHz
Output Update Rate
fCLKIN/(14 x 256 x 2N)
Filter Cutoff Frequency fCLKIN/(3.81x14x256x2N )
Settling Time
(3x14x256x2N/fCLKIN)
Total Harmonic Distortion –90 dB typ Input Frequency = 35 Hz
Channel-to-Channel Isolation –85 dB typ
• Feedthrough from Any One Channel to the Other Three, with 35
Hz Full-Scale Sine Wave Applied to that Channel
– ANALOG INPUT
• Input Range ±2.5 Volts
• Input Capacitance 10 pF typ
• Input Bias Current 1 nA typ
14
AD7716 Operation
• The AD7716 uses a second-order sigma-delta modulator and a digital
filter that provides a rolling average of the sampled out-put. After
power-up or if there is a step change in the input voltage, there is a
settling time before valid data is obtained.
Filter Characteristics
• The cutoff frequency of the digital filter is determined by bits FC2,
FC1 and FC0 in the control register (See Table IV). The cutoff
frequency of the filter is fCLKIN /(3.81x14x256x2N), where N is the
decimal equivalent of FC2, FC1, FC0. At the maximum clock
frequency of 8 MHz, with all 0s loaded to FC2, FC1, FC0, the cutoff
frequency of the filter is 584 Hz and the data update rate is 2232 Hz.
• Since the AD7716 contains low-pass filtering, there is a settling time
associated with step function inputs, and data will be in-valid after a
step change until the settling time has elapsed.
AD7716 Operation
Post Filtering
• In the AD7716, the onchip modulator
provides the digital
filter with samples at a
rate of 570 kHz. The
filter decimates these
samples to provide
data at an output rate
which corresponds to
the programmed first
notch frequency of the
filter.
15