Application Report
SPRA968 - November 2003
Connecting TFT LCD Displays to the OMAP5910
Gerald Coley
DSPIEEE Catalog OMAP Applications
ABSTRACT
The OMAP5910 contains an integrated LCD controller. Utilizing internal memory and
dedicated DMA channels, this architecture contains a very efficient LCD control interface.
This appnote describes how to connect two different LCD displays to the OMAP5910. While
there are many sizes and types of LCD displays in the industry, this appnote focuses on two
240 × 320 color thin film transistor (TFT) displays and how they interface to the OMAP5910
processor.
Contents
1
OMAP5910 LCD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 LCD Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2
3
4
2
NEC 240 y 320 QVGA Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Display Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 LCD Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.2 Timing Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 LCD Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 OMAP5910 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3.1 LCD Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.2 Touchscreen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.3 LCD Panel Front Light . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Sharp 240 y 320 Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Display Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.1 Timing Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 OMAP5910 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 LCD Panel Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5 LED Frontlight Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Touchscreen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Appendix A NEC Display Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Appendix B Sharp Display Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Trademarks are the property of their respective owners.
1
SPRA968
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
OMAP5910 LCD Control Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
NEC LCD Timing Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
NEC LCD Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
NEC LCD Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
NEC LCD LED Frontlight Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Sharp LCD Timing Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Sharp Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Sharp LCD Frontlight Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
1
LCD Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
NEC LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
LCD Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
LCD Control Signals Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
LCD Control Signals Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sharp LCD Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Sharp LCD OMA5910 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
OMAP5910 LCD Controller
This section provides a high-level description of the LCD controller as it pertains to the TFT
mode of operation that is being used in this appnote.
1.1
Features
The following features are provided by the OMAP5910 LCD controller:
•
•
•
2
Mono passive: 1 BPP, 2 BPP, 4 BPP, and 8 BPP
−
1 BPP: Two palette entries selecting one of 15 grayscale
−
2 BPP: Four palette entries selecting one of 15 grayscale
−
4 BPP: 16 palette entries selecting one of 15 grayscale
−
8 BPP: 256 palette entries selecting one of 15 grayscale
Color passive: 2 BPP, 4 BPP, 8 BPP, 12, and 16 BPP
−
2 BPP: Four palette entries from 3375 possible colors
−
4 BPP: 16 palette entries from 3375 possible colors
−
8 BPP: 256 palette entries from 3375 possible colors
−
12 BPP: 3375 possible on-screen colors
−
16 BPP: 3375 possible on-screen colors
Active: 2 BPP, 4BPP, 8BPP, 12 BPP, and 16BPP
Connecting TFT LCD Displays to the OMAP5910
SPRA968
−
2 BPP: Four palette entries selecting from 4096 colors
−
4 BPP: 16 palette entries selecting from 4096 colors
−
8 BPP: 256 palette entries selecting from 4096 colors
−
12 BPP: Maximum 64K colors
−
16 BPP: Maximum 64K colors, depending on LCD panel
The TFT is the most commonly used display for hand-held type devices and offers the best
overall quality in terms of color depth, clarity, and overall brightness.
The other modes listed above are not covered in this application note.
1.2
Block Diagram
Figure 1 shows the block diagram of the LCD controller on the OMAP5910.
LCD controller
Frame
buffer
16−bit TFT
M
U
X
12/16 bpp STN
Palette
RAM
Gray−scaler
/serializer
LCD.P
[15:0]
Output
FIFO
LCD.PCLK
MPU private
peripheral bus
LCD_CK
(from clock and
reset management
block)
Registers
Control
LCD panel
timings
generator
LCD.VS
LCD.HS
LCD.AC
DMA request
LCD interrupt (level 1 IRQ_31)
Figure 1. OMAP5910 LCD Control Block Diagram
In the TFT mode, the palette RAM, gray-scalar, and output FIFO are not used. The data is sent
directly to the LCD display via the DMA controller from the internal frame buffer memory.
For more detailed information on the internal workings of the OMAP5910 LCD controller, refer to
the OMAP5910 datasheet or Technical Reference Manual.
Connecting TFT LCD Displays to the OMAP5910
3
SPRA968
1.3
LCD Interface Signals
Table 1 defines the primary pins used by the OMAP5910 to control an external TFT LCD panel.
Table 1. LCD Interface Signals
NAME
TYPE
LCD.P[15:0]
OUT
Pins used to transfer sixteen bit data values at a time to the LCD display.
OUT
Pixel clock used by the LCD display to clock the pixel data into the line shift register. The
pixel clock transitions continuously and the ac-bias pin is used as an output enable to signal
when data is available on the LCD pins.
LCD.HS
OUT
Line clock used by the TFT displays as the horizontal synchronization signal.
LCD.VS
OUT
Frame clock used by the LCD displays to signal the start of a new frame of pixels. Used by
TFT displays as the vertical synchronization signal.
LCD.AC
OUT
Used in TFT mode as the output enable to signal when data is latched from the data pins
using the pixel clock.
LCD.PCLK
DESCRIPTION
Additional signals may be required from the OMAP5910. These signals are typically GPIO pins
and are used to control such things as:
•
LCD power on/off
•
Backlight on/off
•
Brightness control
Depending on the system level design, several pins are available for these and similar functions.
The designer of the board is free to choose if and how these functions are controlled by the
OMAP5910 processor.
2
NEC 240 y 320 QVGA Display
The first display that we will discuss is the NEC NL2432DR22-11B LCD display. The features of
this display include:
•
3.5” (8.9cm) diagonal
•
240 x 320 Resolution (QVGA)
•
Reflective
•
Portrait Mode
The remainder of this section describes how to interconnect the NEC LCD display and the
OMAP5910.
4
Connecting TFT LCD Displays to the OMAP5910
SPRA968
2.1
Display Description
The NEC display is actually comprised of two components:
2.1.1
•
NL2432DR22-11B LCD display
•
The S1L50282F23k100 timing controller
LCD Display
Table 2 lists the specifications of the NEC LCD.
Table 2. NEC LCD Specifications
Parameter
Specification
Units
Screen Diagonal
3.52”(8.9)
in(cm)
Display Area
2.11(53.64)H × 2.82 (71.53)V
in(mm)
Pixel Format
240 × 320
Colors
262,144
Pixel Configuration
R,G,B Vertical Stripe
Outline Dimensions
2.56(65)W × 3.35(85)H × 18(4.5)D
2.1.2
in(mm)
Timing Controller
The OMAP5910 actually connects to the S1L50282F23k100 timing controller provided by NEC.
The timing controller converts the 16-bit LCD data into the row and column scan data to drive
the LCD panel itself. In some cases, the timing controller is integrated with the LCD panel. This
is especially true of the larger size displays. However, in this case, the timing controller is
separate from the LCD panel. Figure 2 shows the pinout of the timing controller.
Connecting TFT LCD Displays to the OMAP5910
5
SPRA968
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
23
22
19
18
17
16
RA10
RA11
RA12
RA13
RA14
RA15
15
13
12
11
10
9
GA10
GA11
GA12
GA13
GA14
GA15
8
6
5
4
3
2
BA10
BA11
BA12
BA13
BA14
BA15
75
76
71
77
73
72
70
79
69
INVSE
HDRES
PCI
PCSE
PANS0
PANS1
DSE
CKS
HOEPW
25
DCK
34
32
35
33
36
39
37
BO0
BO1
BO2
BO3
BO4
BO5
GO0
GO1
GO2
GO3
GO4
GO5
RO0
RO1
RO2
RO3
RO4
RO5
42
43
44
45
46
48
49
50
51
52
53
55
56
57
58
59
62
63
VCK
POC
OEN
TSTEN
VOE
VSP
65
66
67
80
68
64
60
47
40
38
28
26
24
20
7
30
29
78
INV
PC
DLP
HOE
INH
HCK
HSP
DE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
27
74
61
54
41
31
21
14
1
U10
S1L50282F23k100
Figure 2. NEC LCD Timing Controller
The individual signals are discussed in the following sections.
2.2
LCD Control Signals
Table 3 describes the functions of the control signals on the S1L50282F23k100 timing controller
that connects to the OMAP5910 LCD interface. The LCD side of the controller is not covered.
Refer to the schematic in Appendix A for more details.
6
Connecting TFT LCD Displays to the OMAP5910
SPRA968
Table 3. LCD Control Signals
Number
Name
I/O
Freq
Description
6,8,5−2
BI0-5
I
7.5 MHZ
Input data for the color blue.
15,13−9
GI0-5
I
7.5 MHZ
Input data for the color green.
23,22,19−16
RI0-5
I
7.5 MHZ
Input data for the color red.
25
DCK
I
15 MHZ
Dot clock
27
DE
I
18.75 KHZ
29
OEN
I
DC
Gate driver output enable pin
30
POC
I
DC
Power on clear
75
INVSE
I
DC
Output data reverse (0:off,1:on)
76
HDRES
DC
Data reverse of Internal PC (0:off,1:on)
71
PCI
I
DC
Polarity inversion (0:line reverse,1:frame reverse)
77
PCSE
I
DC
PC switching (0:internal PC,1:Internal PC reverse)
73
PANS0
I
DC
Switching resolution setup 0
72
PANS1
I
DC
Switching resolution setup 1
70
DSE
I
DC
Source driver switching
79
CKS
I
DC
DCK reverse (0:no-reverse, 1:reversed)
69
HOEPW
I
DC
HOE Pulse width selection.
78
TSTEN
I
DC
Test terminal (0:non-reversed’1=reversed.
Data enable
NOTE: Not all of these signals are controlled by the OMAP5910 processor.
2.3
OMAP5910 Interface
This section describes the interconnection of the LCD and timing controller into the OMAP5910
processor. Table 4 maps the LCD controller pins to the OMAP595910. In addition, those signals
that do not connect to the OMAP5910, but need to be terminated, are also covered.
Table 4. LCD Control Signals Connections
CONTROLLER SIGNAL
OMAP5910 SIGNAL
CONTROLLER SIGNAL
OMAP5910 SIGNAL
BI0
LCD.P4
DCK
LCD.PCLK
BI1
LCD.P0
DE
LCD.AC
BI2
LCD.P1
OEN
HIGH
BI3
LCD.P2
POC
HIGH via RC
BI4
LCD.P3
INVSE
Ground
BI5
LCD.P4
HDRES
Open
Connecting TFT LCD Displays to the OMAP5910
7
SPRA968
Table 4. LCD Control Signals Connections (Continued)
CONTROLLER SIGNAL
OMAP5910 SIGNAL
CONTROLLER SIGNAL
OMAP5910 SIGNAL
GI0
LCD.P5
PCI
Ground
GI1
LCD.P6
PCSE
Open
GI2
LCD.P7
PANS0
High
GI3
LCD.P8
PANS1
High
GI4
LCD.P9
DSE
Ground
GI5
LCD.P10
CKS
Open
RI0
LCD.P15
HOEPW
Ground
RI1
LCD.P11
TSTEN
Ground
RI2
LCD.P10
RI3
LCD.P9
RI4
LCD.P8
RI5
LCD.P7
If you will note, BI0 and BI5 are connected to the same signal from the OMAP processor. This is
because the timing controller is designed for 18-bit data, or R6:G6:B6, whereas OMAP5910
supports 16-bit data, or R5:G6:B5. Tying these two signals together, BI0, being the least
significant bit, is an easy way of performing the conversion not only for the red component, but
for the blue component as well. Green on the other hand, uses all available bits which results in
a 5:6:5 configuration for the data.
What is unique about the NEC timing controller is that it does not require the vertical or
horizontal sync data; only the pixel clock and the DE signal.
Refer to Appendix A for the complete schematic.
2.3.1
LCD Power
Figure 3 illustratess the design of the LCD power for the NEC display. The power does not
necessarily need to be designed in this manner, only the required power must be provided.
8
Connecting TFT LCD Displays to the OMAP5910
SPRA968
5V_LCDVCC
+
C50
10.0UF
C51
0.1uF
L7
10uH DK PCD1345CT−ND
U34
MAX633
4
3
1
7
LCDVCC_+15V
LX
GND
LBI
VFB
VOUT
LBO
CP
COMP
5
LCDVCC_+15V−1
2
6
LCDVCC_−15V−3
+ C63
+
5V_LCDVCC−1
22uF_25V_(D)
8
C800
10.0UF 25V_(D)
DO−214AC(SMA)
LCDVCC_−15V−2
LCDVCC_−15V
LCDVCC_−15V−1
D6
DK/SS12G1CT−ND
D60
DK/SS12G1CT−ND
C56
2.2UF 25V_(D)
+
5V_LCDVCC
R157
43.6K
U13
TPS79301DBV
C66
15pf
1
2
3
IN
GND
EN
OUT
FB
BYPASS
6
5
4
3V_LCDVCC
3V_LCDVCC−1
F1
DK/F1261CT−ND
+
C68
0.1UF
C70
0.01UF
R158
30.1K
C69
0.1UF
C67
4.7uF
Figure 3. NEC LCD Power
The NEC display requires a + 15 V and a −15 V supply to power the LCD panel. The logic
signals in the LCD panel are all at 3 VDC. In this design, all of the power is generated based on
a 5 VDC supply. In the event the supply is different, Up converters can be used to create the
required voltages.
Pin 2 on the LCD connector (refer to Appendix A) is the contrast control for the LCD panel. A
potentiometer is used to adjust the voltage based on a 5v voltage source as needed.
2.3.2
Touchscreen
In addition to the LCD panel, the NEC display also has an integrated touch panel over the
display. This touch panel provides the ability to connect to a 4-wire touchscreen controller in
order to decode the x and Y coordinates and pressure on the display where a stylus is being
used. Any 4-wire touchscreen controller decodes this information. A good device is the TI
ADS7486 as depicted in Figure 4.
Connecting TFT LCD Displays to the OMAP5910
9
SPRA968
VCC_I/O
+
C107
1UF
C113
0.1UF
R179
10K
J3
R181
10K
1
2
3
4
MOLEX 52207−0490
U25
ADS7846E
1
2
3
4
5
6
7
8
X+
Y+
X−
Y−
VCC_MAIN
C110
C111
C109
C112
1000pF
1000pF
1000pF
1000pF
2
4
6
8
11
13
15
17
1
19
+Vcc
X+
Y+
X−
Y−
GND
Vbat
IN
DCLK
CS
DIN
BUSY
DOUT
IRQ
+Vcc
Vref
16
15
14
13
12
11
10
9
DCLK
TCS#
DIN
BUSY
DOUT
IRQ
U24
SN74LVCH244APW
18
Y1
A1
16
Y2
A2
14
Y3
A3
12
Y4
A4
9
A5
Y5
7
A6
Y6
5
A7
Y7
3
Y8
A8
1OE
2OE
VCC
GND
TS_INT
TS_STATUS
I2S_DATA_OUT
20
10
C108
0.1UF
I2S_CLK
TS_CS
I2S_DATA_IN
CAM_OPTSENS
Figure 4. NEC LCD Power
2.3.3
LCD Panel Front Light
The NEC display has an LED light source configured as a frontlight and integrated into the NEC
panel. Figure 4 shows the frontlight power configuration. The LEDs require 7.9 V. In this case,
however, a 15 V supply was used because it already existed for the LCD panel. The designer
may choose to generate the required power differently.
J400
4
3
2
1
04FLH−SM1−TB/J.S.T
GND
V2
7.9v
max
V1
D400
DK/MA8075CT−ND
R400
392
LCDVCC_+15V
Figure 5. NEC LCD LED Frontlight Power
3
Sharp 240 y 320 Display
This section describes connecting a Sharp LQ035Q7D color TFT display to the OMAP5910. The
schematic for this implementation can be found in Appendix B.
3.1
Display Description
The LQ035Q7D LCD display is a color reflective module based on TFT technology. It has an
LCD panel, Driver ICs, back light, touch panel, and a back sealed casing.
The specifications of this display are included Table 5.
10
Connecting TFT LCD Displays to the OMAP5910
SPRA968
Table 5. LCD Control Signals Connections
Parameter
Specification
Units
Screen diagonal
3.52”(8.9)
in(cm)
Display area
2.11(53.64)H × 2.82 (71.53) V
in(mm)
Pixel format
240 × 320
Colors
262,144
Pixel configuration
R,G,B Vertical stripe
Outline dimensions
2.56(65)W × 3.35(85)H ×.18(4.5)D
3.1.1
in(mm)
Timing Controller
The Sharp LCD also has a separate timing controller chip called the LZ9FC22. This chip
converts the 16bi RGB digital data into the row and column driver information to drive the LCD
panel. Figure 6 contains the pinout of the LCD timing controller.
Connecting TFT LCD Displays to the OMAP5910
11
SPRA968
17
24
10
27
45
63
1
26
71
72
3
4
5
6
7
8
11
12
13
14
15
16
18
19
20
21
22
23
RESET
TEST1
TEST2
VDD0
VDD1
VDD2
VDD3
TV/MOD
UBR
SPS
CLS
CLK
LP
SPL
LBR
SPR
PS
DCLK
ENAB
HSYNC
VSYNC
R0
R1
R2
R3
R4
R5
DR0
DR1
DR2
DR3
DR4
DR5
DG0
DG1
DG2
DG3
DG4
DG5
DB0
DB1
DB2
DB3
DB4
DB5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
B5
TEST0
TEST4
25
66
69
65
62
61
37
36
35
34
33
32
44
43
42
41
40
39
52
51
50
49
48
47
59
58
57
56
55
54
2
70
67
68
VRVE
REVV0
REV
30
LZ9FC22
9
28
38
46
53
60
64
GND
GND
GND
GND
GND
GND
GND
31
NC0/TEST
NC1/SIZECO
HRVE
29
Figure 6. Sharp LCD Timing Controller
3.2
Control Signals
Table 6 defines the signals on the LCD timing controller that are used to connect to the
OMAP5910 processor.
Table 6. Sharp LCD Control Signals
No.
Name
I/O
Description
1
DCLK
I
Input terminal for data clock signal
2
SETR
I
Input terminal for control signal for PS (SIZEC0 = ”L” to the application)
3−8
R0-5
I
Input data for the color red
11−16
G0-5
I
Input data for the color green
18−23
B0-5
I
Input data for the color blue
12
Connecting TFT LCD Displays to the OMAP5910
SPRA968
Table 6. Sharp LCD Control Signals (Continued)
No.
Name
I/O
Description
25
HREV
I
Input terminal for setting up right/left reverse scanning
H level : Normal L level : Reverse scanning
26
ENAB
I
Input terminal for signal to settle the horizontal display position
66
VREV
I
Input terminal for setting up up/down reverse scannning
(H:Normal L:Reverse scanning)
68
SIZECO
I
Input signal for drive condition change
SIZEC0 =
H : Portrait QVGA(240RGB × 320)
L : Landscape QVGA(320RGB × 240)
70
REM
I
Input terminal for reset signal
71
HS
I
Input terminal for horizontal sync. signal
72
VS
I
Input terminal for vertical sync. Signal
3.3
OMAP5910 Interface
Table 7 defines the mapping between the Sharp LCD timing controller chip and the OMAP5910
processor LCD interface. It also shows the state of the pins that are not controlled directly by the
OMAP5910 processor.
Table 7. Sharp LCD OMA5910 Interface
CONTROLLER SIGNAL
OMAP5910 SIGNAL
CONTROLLER SIGNAL
OMAP5910 SIGNAL
B0
LCD.P4
DCK
LCD.PCLK
B1
LCD.P0
DE
LCD.AC
B2
LCD.P1
OEN
HIGH
B3
LCD.P2
POC
HIGH via RC
B4
LCD.P3
INVSE
Ground
B5
LCD.P4
HDRES
Open
G0
LCD.P5
PCI
Ground
G1
LCD.P6
PCSE
Open
G2
LCD.P7
PANS0
High
G3
LCD.P8
PANS1
High
G4
LCD.P9
DSE
Ground
G5
LCD.P10
CKS
Open
R0
LCD.P15
HOEPW
Ground
Connecting TFT LCD Displays to the OMAP5910
13
SPRA968
Table 7. Sharp LCD OMA5910 Interface (Continued)
CONTROLLER SIGNAL
OMAP5910 SIGNAL
CONTROLLER SIGNAL
OMAP5910 SIGNAL
R1
LCD.P11
TSTEN
Ground
R2
LCD.P12
R3
LCD.P13
R4
LCD.P14
R5
LCD.P15
3.4
LCD Panel Power
Figure 7 shows a possible design for the LCD power. The LCD requires a +15 V supply for the
LCD panel itself. The logic section of the LCD requires a 3.3 V supply. The designer may choose
a different way to supply the power to the LCD.
5V_LCDVCC
+
C50
10.0UF
C51
0.1uF
L7
10uH DK PCD1345CT−ND
U34
MAX633
5V_LCDVCC−1
4
3
1
7
LX
LCDVCC_+15V
5
VOUT
GND
LBI
VFB
LCDVCC_+15V−1
2
6
LBO
CP
+ C63
22uF_25V_(D)
8
COMP
DO−214AC(SMA)
5V_LCDVCC
R157
53.6K
U13
TPS79301DBV
C66
15pf
1
2
3
IN
GND
EN
OUT
FB
BYPASS
6
5
4
3.3V_LCDVCC
3V_LCDVCC−1
F1
DK/F1261CT−ND
+
C68
0.1UF
C70
0.01UF
R158
30.1K
C69
0.1UF
C67
4.7uF
Figure 7. Sharp Power Supply
Both of these circuits use a 5 V source to create the required voltages. The fuse is not required
and is a part of this design, only as a precautionary measure.
14
Connecting TFT LCD Displays to the OMAP5910
SPRA968
3.5
LED Frontlight Interface
Figure 8 is the schematic for the control interface for the LED frontlight of the Sharp display.
5V
D1
L1
10UH
J14
24V @ 15MA
DK/10MQ040N−ND
4.7UF TANT 35V
+
DO NOT INSTALL IF
R2 IS INSTALLED
LED CONNECTOR
C1
+
U1
R1
1K DNI
5
SW
CONN MOLEX 54548−0590
C2
4.7UF TANT 35V
1
C PACKAGE
Vin
FB
4
3
EN
GND
2
R3
82
TPS61040DBV
R2
0
1
2
3
4
5
SOT−23 PACKAGE
EN
Figure 8. Sharp LCD Frontlight Controller
The power for the LED is supplied by U1, a 400-ma boost converter, which converts the 5 V
input to the 24 V required by the LEDs. This design actually accepts and inputs a voltage range
from 1.8 V to 6 V. So, depending on the individual designs, there is some flexibility here. Refer to
the TPS61040 datasheet for more details.
The EN signal can be any GPIO pin on the OMAP5910. When it is Hi, U1 is active. As an option,
R1 can be installed if the user wants the LCD to be on all the time.
3.6
Touchscreen
The requirements for the Touchscreen panel on the Sharp LCD are the same as found on the
NEC Touchscreen interface.
4
Summary
The NEC LCD design was verified and produced in the form of the Innovator Development Kit.
The NEC design was used in the production units of the Innovator platform and is still being
used.
A printed circuit board design was made, and 10 units were assembled and tested for the Sharp
design. It was never produced in large quantities. It was intended as a backup in case the NEC
displays could not be obtained.
Connecting TFT LCD Displays to the OMAP5910
15
SPRA968
5
References
1. OMAP1510 Dual-Core Processor Data Manual (literature number SPRS197)
2. OMAP1510 Dual-Core Processor Technical Reference Manual (literature number
SPRU602)
3. Sharp LCD Panel Datasheet LQ035Q7 B02 (LCY-02024, March 14, 2002)
4. NEC LCD Panel Datasheet NL2432DR22-11B (8th Edition, March 4, 2002)
5. Sharp Control IC for TFT-LCD Module LZ9FC22 (LCY-00136, June 26, 2001)
6. NEC LCD Controller S1L50282F23k100 (DOD-N-0192, 3rd Edition)
16
Connecting TFT LCD Displays to the OMAP5910
SPRA968
Appendix A
NEC Display Schematics
3V_LCDVCC
3V_LCDVCC
5V_LCDVCC
R36
C38 C39
0.1UF0.1UF
120K
LCD_B_P[0..15]
LCD_B_P11
R41 200
LCD_B_P12
R42 200
LCD_B_P13
R43 200
LCD_B_P14
R44 200
LCD_B_P15
R45 200
23
22RA10
19RA11
18RA12
17RA13
16RA14
RA15
LCD_B_P5
R47 200
LCD_B_P6
R49 200
LCD_B_P7
R51 200
LCD_B_P8
R53 200
LCD_B_P9
R54 200
LCD_B_P10
R56 200
15
13GA10
12GA11
11GA12
10GA13
9 GA14
GA15
LCD_B_P0
R59 200
LCD_B_P1
R61 200
LCD_B_P2
R63 200
LCD_B_P3
R65 200
LCD_B_P4
R67 200
8
6 BA10
5 BA11
4 BA12
3 BA13
2 BA14
BA15
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
74
61
54
41
31
21
14
1
U10
S1L50282F23k100
34 R46 200
INV32
R48
PC35 R50 200
DLP
33
R52
HOE
36
INH39 R55 100
HCK
37
R57
HSP
R58
R60 200
R62
R64 200
R66
R68 200
R69
R70 200
R72
R73 200
R75
R76 200
R78
R80 200
R82
R83 200
R85
R86 200
PIXEL15MHZ
CLK25
42
BO0
43
BO1
44
BO2
45
BO3
46
BO4
48
BO5
49
GO0
50
GO1
51
GO2
52
GO3
53
GO4
55
GO5
56
RO0
57
RO1
58
RO2
59
RO3
62
RO4
63
RO5
R88 200 DATA ENABLE
27 18.75KHZ
DE
65
VCK
R89 200
R90 100K
66
VOE
R91 200
67
VSP
R92 200
1
TP5
1
TP6
3V_LCDVCC
1
TP7
75
76INVSE
71HDRES
77PCI
73PCSE
72PANS0
70PANS1
79DSE
69CKS
HOEPW
3V_LCDVCC
POWER ON30CLEAR
OUTPUT ENABLE
29POC
78OEN
TSTEN
C43
0.1UF
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
LCD_B_AC
DCK
80
68
64
60
47
40
38
28
26
24
20
7
LCD_B_PCLK
R87 200
J4
JAE/IL−FMR−F455−−HF
R37
1
VAR 100K P5C104CT−ND
COM
2
3
4
C42
C40
5
150pF 0.1UF
6
+ C41
4.7UF 7
8
9
VCOM
10
11
INV
12
POL
200
13
DLP−STB14
AP
200
15
16
HCK
17
HSP
200
18
19
B0
200
20
B1
21
B2
200
22
B3
23
B4
200
24
B5
25
G0
200
26
G1
27
G2
200
28
G3
29
G4
200
30
G5
31
R0
200
32
R1
33
R2
200
34
R3
35
R4
200
36
R5
37
38
39
VCK
40
VGOFF
41
VOE
42
VGON
43
VSP
44
45
LCDVCC_−15V
C44
C45
0.1UF 0.1UF
C46
0.1UF
LCDVCC_+15V
5V_LCDVCC
Connecting TFT LCD Displays to the OMAP5910
17
SPRA968
J400
4
3
2
1
04FLH−SM1−TB/J.S.T
GND
V2
7.9v
max
V1
D400
DK/MA8075CT−ND
R400
392
LCDVCC_+15V
VCC_I/O
+
C113
0.1UF
MOLEX 52207−0490
R179
10K
1
2
3
4
J3
C107
1UF
U25
ADS7846E
X+
Y+
X−
Y−
VCC_MAIN
C110
1000pF
18
C111
1000pF
C109
1000pF
1
2
3
4
5
6
7
8
+Vcc
X+
Y+
X−
Y−
GND
Vbat
IN
R181
10K
2
4
6
8
11
13
15
17
1
19
DCLK
CS
DIN
BUSY
DOUT
IRQ
+Vcc
Vref
16
15
14
13
12
11
10
9
C112
1000pF
Connecting TFT LCD Displays to the OMAP5910
DCLK
TCS#
DIN
BUSY
DOUT
IRQ
U24
SN74LVCH244APW
18
Y1 16
A1
Y2 14
A2
Y3 12
A3
Y4 9
A4
A5
Y5 7
A6
Y6 5
A7
Y7 3
A8
Y8
1OE
2OE
VCC
GND
TS_INT
TS_STATUS
I2S_DATA_OUT
20
10
C108
0.1UF
I2S_CLK
TS_CS
I2S_DATA_IN
CAM_OPTSENS
SPRA968
5V_LCDVCC
+
C50
10.0UF
C51
0.1uF
L7
10uH DK PCD1345CT−ND
U34
MAX633
4
3
1
7
LX
GND
LBI
VFB
LCDVCC_+15V
VOUT
LBO
CP
COMP
5
LCDVCC_+15V−1
2
6
LCDVCC_−15V−3
+ C63
+
5V_LCDVCC−1
22uF_25V_(D)
8
C800
10.0UF 25V_(D)
DO−214AC(SMA)
LCDVCC_−15V−2
LCDVCC_−15V
LCDVCC_−15V−1
D6
DK/SS12G1CT−ND
D60
DK/SS12G1CT−ND
C56
2.2UF 25V_(D)
+
5V_LCDVCC
R157
43.6K
U13
TPS79301DBV
C66
15pf
1
2
3
IN
GND
EN
OUT
FB
BYPASS
6
5
4
3V_LCDVCC
3V_LCDVCC−1
F1
DK/F1261CT−ND
+
C68
0.1UF
C70
0.01UF
R158
30.1K
C69
0.1UF
C67
4.7uF
Connecting TFT LCD Displays to the OMAP5910
19
SPRA968
Appendix B
Sharp Display Schematics
LCDVCC_VCOM
LCDVCC_VEE
3.3V_LCDVCC
5V_LCDVCC
LCDVCC_−15V
LCDVCC_−11.7V
3.3V
C38
0.1UF
C39
0.1UF
C43
0.1UF
LCDVCC_+15V
C46
0.1UF
U405
C44
0.1UF
C440
0.1UF
C45
0.1UF
J4
17
24
10
27
45
63
R87
R88
R68
R69
LCD_B_PCLK
LCD_B_AC
LCD_B_HSYNC
LCD_B_VSYNC
LCD_B_P11
LCD_B_P12 R42
LCD_B_P13
LCD_B_P14 R44
LCD_B_P15
LCD_B_P5 R47
LCD_B_P6
LCD_B_P7 R51
LCD_B_P8
LCD_B_P9 R54
LCD_B_P10
LCD_B_P0
LCD_B_P1
LCD_B_P2
LCD_B_P3
LCD_B_P4
10
10
10
10
10
R43
10
R45
10
R49
10
R53
10
R56
10
R59
10
R63
10
R67
10
10
10
10
10
10
R61
10
R65
10
RESET
29
+15.0V
−11.7V
69
TV/MOD65
UBR 62
SPS 61
CLS 37
CLK 36
LP 35
SPL 34
LBR 33
SPR 32
PS
1
26 DCLK
71 ENAB
72 HSYNC
VSYNC
3
4 R0
5 R1
6 R2
7 R3
8 R4
R5
11
12 G0
13 G1
14 G2
15 G3
16 G4
G5
18
19 B0
20 B1
21 B2
22 B3
23 B4
B5
PIXEL CLK
DATA ENABLE 18.75KHZ
R41
TEST1
TEST2
VDD0
VDD1
VDD2
VDD3
DR0
DR1
DR2
DR3
DR4
DR5
DG0
DG1
DG2
DG3
DG4
DG5
DB0
DB1
DB2
DB3
DB4
DB5
LCD_B_P[0..15]
TEST0
MOD
UBR
SPS
CLS
−15.0V
VEE
VCOM
44
43
42
41
40
39
52
51
50
49
48
47
59
58
57
56
55
54
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
B5
2
PS
LP
CLK
LBR
SPR
3.3V
3.3V_LCDVCC
3.3V_LCDVCC
R90
10
R73
25
10
66
31
70
TEST4
67
NC0/TEST68
NC1/SIZECO
HRVE
VRVE
REVV0
R70
DD DDD DD
NN NNN NN
GG GGG GG
REV
30
5.0V
V0
V1
V2
V3
0
V5
USE WITH LED B/L ONLY.
DNI IF U10 INSTALLED.
9 28 38 46 53 60 64
V8
V9
5V_LCDVCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CONN Hirose FH12−50S−0.5SH
LZ9FC22
BOTTOM CONTACTS
3.3V_LCDVCC
U10
11
12 VCC
VDD
POWER ON RESET
U400
16
U401
13
1
6 NC
NC
13
R403
R401
2
4
2
1.5K
C403
0.1UF
5
SN74LVC1G17DBVR
5 SN74LVC1G17DBVR
+ C41
R402
2.7K
20
USE WITH LED B/L ONLY.
V0
V1
V2
V3
V4
4
5
8
9
10
DNI IF U10 INSTALLED.
4
7
100K
SW
R71
0
Connecting TFT LCD Displays to the OMAP5910
+ C410
4.7UF DNI4.7UF DNI
GND
COM
3
IR3E3044 DNI
DNI
LCD_COM
SPRA968
Connecting TFT LCD Displays to the OMAP5910
21
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