Digital Design — Chapter 1 — Introduction and Methodology
17 February 2010
VHDL
Digital Design
Digital Design:
An Embedded Systems
Approach Using VHDL
„
Digital: circuits that use two voltage
levels to represent information
„
„
Logic: use truth values and logic to analyze
circuits
Design: meeting functional
requirements while satisfying
constraints
Chapter 1
Introduction and Methodology
„
Portions of this work are from the book, Digital Design: An Embedded
Systems Approach Using VHDL, by Peter J. Ashenden, published by Morgan
Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved.
VHDL
Constraints: performance, size, power,
cost, etc.
Digital Design — Chapter 1 — Introduction and Methodology
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Digital Design — Chapter 1 — Introduction and Methodology
4
VHDL
Design using Abstraction
Billions
„
Circuits contain millions of transistors
„
Abstraction
„
„
„
„
How can we manage this complexity?
Focus on aspects relevant aspects, ignoring
other aspects
Don’t break assumptions that allow aspect
to be ignored!
Examples:
„
„
Transistors are on or off
Voltages are low or high
Digital Design — Chapter 1 — Introduction and Methodology
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VHDL
VHDL
More Trends…..
Xilinx XC6VSX475T
2,016 DSP48E1 Slices
25 × 18 bit Multipliers
48 bit Accumulators (600 MHz)
Digital Design — Chapter 1 — Introduction and Methodology
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Digital Design — Chapter 1 — Introduction and Methodology
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Digital Design — Chapter 1 — Introduction and Methodology
VHDL
17 February 2010
VHDL
Digital Systems
„
FPGAs now give the best GFLOPs/Watt performance.
Electronic circuits that use discrete
representations of information
„
Discrete in space and time
In a National Science Foundation benchmark, a Stratix IV FPGA
delivered 171 GFLOPs and was the clear overall leader in
highest GFLOPs/Watt [1].
[1] Altera’s floating-point solutions for military applications.
April 2009, SS-01058-1.1
http://www.altera.co.uk/literature/po/ss-military-floating-point.pdf
Digital Design — Chapter 1 — Introduction and Methodology
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VHDL
Digital Design — Chapter 1 — Introduction and Methodology
8
VHDL
Embedded Systems
„
Most real-world digital systems include
embedded computers
„
„
„
Processor cores, memory, I/O
„
Basic representation for simplest form
of information, with only two states
„
Different functional requirements
can
q
be implemented
„
„
Binary Representation
„
„
by the embedded software
by special-purpose attached circuits
„
„
a switch: open or closed
a light: on or off
a microphone: active or muted
a logical proposition: false or true
a binary (base 2) digit, or bit: 0 or 1
Trade-off among cost, performance,
power, etc.
Digital Design — Chapter 1 — Introduction and Methodology
9
VHDL
Digital Design — Chapter 1 — Introduction and Methodology
10
VHDL
Binary Representation: Example
Binary Representation: Example
+V
+V
lamp_enabled
switch_pressed
sensor
„
Signal represents the state of the switch
„
„
„
high-voltage => pressed,
low-voltage => not pressed
„
Equally, it represents state of the lamp
„
„
lamp_lit = switch_pressed
Digital Design — Chapter 1 — Introduction and Methodology
„
11
lamp_lit
dark
dark: it’s night time
lamp_enabled: turn on lamp at night
lamp_lit: lamp_enabled AND dark
Logically: day time => NOT lamp_lit
Digital Design — Chapter 1 — Introduction and Methodology
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Digital Design — Chapter 1 — Introduction and Methodology
VHDL
17 February 2010
VHDL
Basic Gate Components
„
Combinational Circuits
Primitive components for logic design
„
Circuit whose output values depend
purely on current input values
>30°C
vat 0
AND gate
>25°C
OR gate
low level
0
0
1
buzzer
>30°C
1
+V
inverter
multiplexer
vat 1
>25°C
select vat 1
select vat 0
low level
Digital Design — Chapter 1 — Introduction and Methodology
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VHDL
Digital Design — Chapter 1 — Introduction and Methodology
14
VHDL
Sequential Circuits
„
Circuit whose output values depend on
current and previous input values
„
„
Flipflops and Clocks
„
Edge-triggered D-flipflop
„
stores one bit of information at a time
Include some form of storage of values
rising edge
Nearlyy all digital
systems
are sequential
g
y
q
„
„
D
Mixture of gates and storage components
Combinational parts transform inputs and
stored values
15
VHDL
1
Q
1
0
falling edge
0
Timing diagram
„
Digital Design — Chapter 1 — Introduction and Methodology
D
Q
clk
„
clk
1
0
Graph of signal values versus time
Digital Design — Chapter 1 — Introduction and Methodology
16
VHDL
Real-World Circuits
„
Assumptions behind digital abstraction
„
„
„
„
Integrated Circuits (ICs)
„
ideal circuits, only two voltages,
instantaneous transitions, no delay
„
Greatly simplify functional design
Constraints arise from real components
and real-world physics
Meeting constraints ensures circuits are
“ideal enough” to support abstractions
Digital Design — Chapter 1 — Introduction and Methodology
Circuits formed on surface of silicon wafer
17
„
„
„
Minimum feature size reduced in each
technology generation
Currently 90nm, 65nm 45 nm, 32 nm (Intel Westmere)
Moore’s Law: increasing transistor count
CMOS: complementary MOSFET circuits
+V
input
Digital Design — Chapter 1 — Introduction and Methodology
output
18
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Digital Design — Chapter 1 — Introduction and Methodology
VHDL
17 February 2010
VHDL
Logic Levels
„
Actual voltages for “low” and “high”
„
Example: 1.4V threshold for inputs
receiver threshold
1.5V
nominal 1.4V threshold
1 0V
1.0V
0.5V
signal with added noise
2.5V
logic high threshold
2.0V
driven signal
1.5V
1.0V
logic low threshold
0.5V
Digital Design — Chapter 1 — Introduction and Methodology
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VHDL
Digital Design — Chapter 1 — Introduction and Methodology
20
VHDL
Logic Levels
Static Load and Fanout
TTL logic levels with noise margins
„
„
Current flowing into or out of an output
„
signal with added noise
VOH
2.0V
VIH
1.5V
driven signal
noise margin
R1
„
„
SW1
output
1.0V
VIL
VOL
0.5V
Digital Design — Chapter 1 — Introduction and Methodology
„
„
„
VIL: input low voltage
VIH: input high voltage
VHDL
Voltage drop across R0
Too much current: VO > VOL
Fanout: number of inputs
connected to an output
„
21
Voltage drop across R1
Too much current: VO < VOH
Low: SW0 closed, SW1 open
SW0
noise margin
R0
VOL: output low voltage
VOH: output high voltage
High: SW1 closed, SW0 open
+V
„
2.5V
determines static load
Digital Design — Chapter 1 — Introduction and Methodology
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VHDL
Other Constraints
Capacitive Load and Prop Delay
„
Inputs and wires act as capacitors
„
output
+V
3.0V
R1
R0
tf
„
VOH
„
1 0V
1.0V
S 1
SW1
SW0
tr
2.0V
input
VOL
Cin
„
„
„
„
tr: rise time
tf: fall time
tpd: propagation delay
„
„
„
23
delayy from clk edge
g to Q output
p
D stable before and after clk edge
Power
„
delay from input transition
to output transition
Digital Design — Chapter 1 — Introduction and Methodology
Wire delay: delay for transition to
traverse interconnecting wire
Flipflop timing
current through resistance => heat
must be dissipated, or circuit cooks!
Digital Design — Chapter 1 — Introduction and Methodology
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Digital Design — Chapter 1 — Introduction and Methodology
VHDL
17 February 2010
VHDL
Area and Packaging
„
Circuits implemented on silicon chips
„
„
„
Larger circuit area => greater cost
Abstract representations of aspects of a
system being designed
Chips in packages with connecting wires
„
„
„
Models
„
More wires => g
greater cost
Package dissipates heat
„
Example: Ohm’s
Ohm s Law
„
Packages interconnected on
a printed circuit board (PCB)
„
„
„
Size, shape, cooling, etc,
constrained by final product
Digital Design — Chapter 1 — Introduction and Methodology
„
25
VHDL
Allow us to analyze the system before
building it
V=I×R
Represents electrical aspects of a resistor
Expressed as a mathematical equation
Ignores thermal, mechanical, materials
aspects
Digital Design — Chapter 1 — Introduction and Methodology
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VHDL
VHDL
„
VHSIC Hardware Description Language
„
„
Entity Declarations
VHSIC = very-high speed integrated circuits
The defense department launched the VHSIC program
in the 1980’s, which created VHDL.
„
A computer language for modeling
behavior and structure of digital systems
>30°C
Electronic Design Automation (EDA)
using VHDL
„
„
„
Describes input and outputs of a circuit
>25°C
low level
>30°C
>25°C
temp_bad_0
or_0a
inv_0
or_0b
wake_up_0
b l
below_25_0
25 0
low_level_0
select_mux
above_25_1
buzzer
1
above_30_1
buzzer
temp_bad_1
inv_1
or_1a
or_1b
+V
wake_up_1
select_vat_1
below_25_1
low level
27
VHDL
above_25_0
0
Design entry: alternative to schematics
Verification: simulation, proof of properties
Synthesis: automatic generation of circuits
Digital Design — Chapter 1 — Introduction and Methodology
above_30_0
low_level_1
Digital Design — Chapter 1 — Introduction and Methodology
28
VHDL
Entity Declarations
Structural Architectures
library dld; use dld.gates.all;
library ieee; use ieee.std_logic_1164.all;
architecture struct of vat_buzzer is
signal below_25_0, temp_bad_0, wake_up_0 : std_logic;
signal below_25_1, temp_bad_1, wake_up_1 : std_logic;
entity vat_buzzer is
port ( above_25_0, above_30_0,
_
_ : in std_logic;
_ g ;
low_level_0
above_25_1, above_30_1,
low_level_1 : in std_logic;
select_vat_1 : in std_logic;
buzzer : out std_logic );
begin
-- components for vat 0
inv_0 : inv (above_25_0, below_25_0);
or_0a : or2 (above_30_0, below_25_0, temp_bad_0);
or_0b : or2 (temp_bad_0, low_level_0, wake_up_0);
-- components for vat 1
inv_1 : inv (above_25_1, below_25_1);
or_1a : or2 (above_30_1, below_25_1, temp_bad_1);
or_1b : or2 (temp_bad_1, low_level_1, wake_up_1);
end entity vat_buzzer;
select_mux : mux2 (wake_up_0, wake_up_1, select_vat_1, buzzer);
end architecture struct;
Digital Design — Chapter 1 — Introduction and Methodology
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Digital Design — Chapter 1 — Introduction and Methodology
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Digital Design — Chapter 1 — Introduction and Methodology
VHDL
17 February 2010
VHDL
Behavioral Architectures
Design Methodology
„
Simple systems can be design by one
person using ad hoc methods
Real-world systems are design by teams
„
S
ifi
Specifies
„
architecture behavior of vat_buzzer is
begin
buzzer <=
low_level_1 or
(above 30 1 or not above_25_1)
(above_30_1
above 25 1)
when select_vat_1 = '1' else
low_level_0 or
(above_30_0 or not above_25_0);
end architecture behavior;
„
Require a systematic design methodology
„
Tasks to be undertaken
Information needed and produced
Relationships between tasks
„
EDA tools used
„
„
„
Digital Design — Chapter 1 — Introduction and Methodology
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VHDL
dependencies, sequences
Digital Design — Chapter 1 — Introduction and Methodology
32
VHDL
A Simple Design Methodology
Requirements
and
Constraints
Converts VHDL
to the physical
implementation
of the circuit
(VHDL)
Hierarchical Design
„
For FPGAs there
is a place and
route step, i.e.
which physical
circuits to use.
„
Design
Synthesize
Physical
Implementation
Manufacture
Functional
Verification
Post-synthesis
Verification
Physical
Verification
Test
OK?
Y
OK?
N
N
Y
OK?
„
Circuits are too complex for us to
design all the detail at once
Design subsystems for simple functions
Compose subsystems to form the
t
system
„
„
Y
N
„
Digital Design — Chapter 1 — Introduction and Methodology
Top-down/bottom-up design
33
VHDL
Treating subcircuits as “black box”
components
Verify independently, then verify the
composition
Digital Design — Chapter 1 — Introduction and Methodology
34
VHDL
Hierarchical Design
Synthesis
Architecture
Design
Unit
Design
Design
N
Y
„
OK?
Integration
Verification
N
„
„
the target implementation fabric
constraints on timing, area, etc.
Post-synthesis verification
„
OK?
Higher level of abstraction than gates
Synthesis tool translates to a circuit of gates
that performs the same function
Specify to the tool
„
Y
N
We usually design using register-transferlevel (RTL) VHDL
„
„
Unit
Verification
Functional
Verification
OK?
„
synthesized circuit meets constraints
Y
Digital Design — Chapter 1 — Introduction and Methodology
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Digital Design — Chapter 1 — Introduction and Methodology
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Digital Design — Chapter 1 — Introduction and Methodology
VHDL
17 February 2010
VHDL
Physical Implementation
„
„
„
„
„
Requirements
and
Constraints
Implementation fabrics
„
„
Codesign Methodology
Application-specific ICs (ASICs)
Field-programmable gate arrays (FPGAs)
Partitioning
Floor-planning: arranging the subsystems
Pl
t arranging
i th
t within
ithi
Placement:
the gates
subsystems
Routing: joining the gates with wires
Physical verification
„
„
Software
Requirements
and Constraints
Hardware
Design and
Verification
Software
Design and
Verification
OK?
OK?
N
physical circuit still meets constraints
use better estimates of delays
Digital Design — Chapter 1 — Introduction and Methodology
Hardware
Requirements
and Constraints
N
Manufacture
and Test
37
Digital Design — Chapter 1 — Introduction and Methodology
38
VHDL
Summary
„
„
„
„
Digital systems use discrete (binary)
representations of information
Basic components: gates and flipflops
Combinational and sequential circuits
Real-world constraints
„
„
„
logic levels, loads, timing, area, etc
VHDL models: structural, behavioral
Design methodology
Digital Design — Chapter 1 — Introduction and Methodology
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